SN74LVC1G79-Q1 [TI]
汽车类单路上升沿触发 D 型触发器;
| 型号： | SN74LVC1G79-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类单路上升沿触发 D 型触发器 触发器 |
| 文件： | 总21页 (文件大小：726K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN74LVC1G79-Q1
ZHCSG59 –MARCH 2017
SN74LVC1G79-Q1 单路正缘触发 D 型触发器
1 特性
3 说明
1
•
•
汽车电子 应用认证
具有符合 AEC-Q100 标准的下列结果：
SN74LVC1G79-Q1 器件是一种通过汽车 AEC-Q100
认证的单路正缘触发 D 型触发器，专门为 1.65V 到
5.5V VCC 操作而设计。
–
±4000 V 人体放电模型 (HBM) ESD 分类等级
3A
当数据输入 (D) 处的数据满足设置时间要求时，将该数
据传输到时钟脉冲正向缘上的 Q 输出。时钟触发出现
在一个特定电压电平上，并且不与时钟脉冲的上升时间
直接相关。经过保持时间间隔后，可以更改 D 输入处
的数据而不影响输出处的电平。
–
±1000 V 带电器件模型 (CDM) ESD 分类等级
C5
•
•
•
•
•
•
•
支持 5V VCC 运行
输入接受的电压达到高达 5.5V
支持向下转换到 VCC
3.3V 和 50pF 负载下最大 tpd 为 6ns
低功耗，10µA 最大 ICC
该器件完全 适用于 使用 Ioff 的局部掉电应用。当器件
断电时，Ioff 电路将会禁用输出。这会抑制电流反流到
器件中，从而防止损坏器件。
电压为 3.3V 时，输出驱动为 ±24mA
Ioff 支持部分断电模式和后驱动保护
器件信息(1)
器件型号
封装
封装尺寸
2 应用
SN74LVC1G79QDCKRQ1 SC70 (5)
2.00mm × 1.25mm
•
•
•
•
•
车用信息娱乐
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
汽车仪表盘
汽车 ADAS
汽车车身电子设备
HEV/EV 动力传动系统
逻辑图（正逻辑）
2
C
CLK
C
C
4
TG
Q
C
C
C
C
1
D
TG
TG
TG
C
C
C
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SCES874
SN74LVC1G79-Q1
ZHCSG59 –MARCH 2017
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
7
8
Parameter Measurement Information .................. 9
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements: TA = –40°C to +85°C ............ 6
6.7 Timing Requirements: TA = –40°C to +125°C .......... 6
9
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 14
12 器件和文档支持 ..................................................... 15
12.1 文档支持................................................................ 15
12.2 接收文档更新通知 ................................................. 15
12.3 社区资源................................................................ 15
12.4 商标....................................................................... 15
12.5 静电放电警告......................................................... 15
12.6 Glossary................................................................ 15
13 机械、封装和可订购信息....................................... 15
6.8 Switching Characteristics: CL = 15 pF, TA = –40°C to
+85°C......................................................................... 7
6.9 Switching Characteristics: CL = 30 or 50 pF, TA
=
–40°C to +85°C.......................................................... 7
6.10 Switching Characteristics: CL = 30 pF or 50 pF, TA
= –40°C to +125°C..................................................... 7
6.11 Operating Characteristics........................................ 7
6.12 Typical Characteristics............................................ 8
4 修订历史记录
日期
修订版本
注释
2017 年 3 月
*
首次发布。
2
Copyright © 2017, Texas Instruments Incorporated
SN74LVC1G79-Q1
www.ti.com.cn
ZHCSG59 –MARCH 2017
5 Pin Configuration and Functions
DCK Package
5-Pin SC70
Top View
See mechanical drawings for dimensions.
Pin Functions
PIN
I/O
DESCRIPTION
NAME
D
DCK
1
2
3
4
5
I
Data input
CLK
GND
Q
I
Positive-Edge-Triggered Clock input
Ground
—
O
—
Non-inverted output
Positive Supply
VCC
Copyright © 2017, Texas Instruments Incorporated
3
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ZHCSG59 –MARCH 2017
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
MAX
6.5
UNIT
V
VCC
VI
Supply voltage
Input voltage(2)
6.5
V
VO
VO
IIK
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
6.5
V
VCC + 0.5
–50
V
Input clamp current
VI < 0
mA
mA
mA
mA
°C
°C
IOK
IO
Output clamp current
VO < 0
–50
Continuous output current
Continuous current through VCC or GND
Storage temperature
±50
±100
150
Tstg
TJ
–65
Junction temperature
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
4
Copyright © 2017, Texas Instruments Incorporated
SN74LVC1G79-Q1
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ZHCSG59 –MARCH 2017
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
1.65
MAX
UNIT
Operating
5.5
VCC
Supply voltage
V
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
1.5
0.65 × VCC
1.7
VIH
High-level input voltage
V
V
2
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.7 × VCC
0.35 × VCC
0.7
0.8
0.3 × VCC
5.5
VCC
–4
VIL
Low-level input voltage
VCC = 4.5 V to 5.5 V
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
–8
IOH
High-level output current
Low-level output current
–16
–24
–32
4
mA
mA
VCC = 3 V
VCC = 4.5 V
VCC = 1.65 V
VCC = 2.3 V
8
IOL
16
VCC = 3 V
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
20
Δt/Δv Input transition rise or fall rate
10
ns/V
°C
5
TA
Operating free-air temperature
–40
125
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
6.4 Thermal Information
SN74LVC1G79-Q1
THERMAL METRIC(1)
DCK
5 PINS
277.6
179.5
75.9
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
49.7
ψJB
75.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017, Texas Instruments Incorporated
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
TA = –40°C to +85°C
TA = –40°C to +125°C
MIN TYP(1) MAX
VCC – 0.1
PARAMETER
TEST CONDITIONS
VCC
UNIT
MIN TYP(1) MAX
IOH = –100 µA
1.65 V to 5.5 V
1.65 V
VCC – 0.1
1.2
IOH = –4 mA
IOH = –8 mA
IOH = –16 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 µA
IOL = 4 mA
1.2
1.9
2.4
2.3
3.8
2.3 V
1.9
VOH
V
2.4
3 V
2.3
4.5 V
1.65 V to 5.5 V
1.65 V
3.8
0.1
0.1
0.45
0.3
0.45
0.3
IOL = 8 mA
2.3 V
VOL
V
IOL = 16 mA
0.4
0.4
3 V
IOL = 24 mA
0.55
0.55
±10
±10
10
0.55
0.55
±5
IOL = 32 mA
4.5 V
0 to 5.5 V
0
II
All inputs
VI = 5.5 V or GND
VI or VO = 5.5 V
VI = 5.5 V or GND,
µA
µA
µA
Ioff
ICC
±10
10
IO = 0
1.65 V to 5.5 V
One input at VCC – 0.6 V,
Other inputs at VCC or GND
ΔICC
3 V to 5.5 V
3.3 V
500
500
µA
pF
Ci
VI = VCC or GND
4
4
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Timing Requirements: TA = –40°C to +85°C
over operating free-air temperature range (unless otherwise noted) (see Figure 3)
TA = –40°C to +85°C
VCC = 1.8
± 0.15 V
VCC = 2.5
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
160
MIN
MAX
fclock
tw
Clock frequency
160
160
160
MHz
ns
Pulse duration, CLK high or low
2.5
2.2
2.6
0.3
2.5
1.4
1.4
0.4
2.5
1.3
1.3
1
2.5
1.2
1.2
0.5
Data high
Data low
tsu
th
Setup time before CLK↑
ns
ns
Hold time, data after CLK↑
6.7 Timing Requirements: TA = –40°C to +125°C
over operating free-air temperature range (unless otherwise noted) (see Figure 3)
TA = –40°C to +125°C
VCC = 1.8
± 0.15 V
VCC = 2.5
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
fclock
tw
Clock frequency
160
160
160
160
MHz
ns
Pulse duration, CLK high or low
2.5
2.2
2.6
0.3
2.5
1.4
1.4
0.4
2.5
1.3
1.3
1
2.5
1.2
1.2
0.5
Data high
Data low
tsu
th
Setup time before CLK↑
ns
ns
Hold time, data after CLK↑
6
Copyright © 2017, Texas Instruments Incorporated
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ZHCSG59 –MARCH 2017
6.8 Switching Characteristics: CL = 15 pF, TA = –40°C to +85°C
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3)
TA = –40°C to +85°C
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
PARAMETER
UNIT
MIN MAX
MIN MAX
MIN MAX
MIN MAX
fmax
tpd
160
160
160
160
MHz
ns
CLK
Q
2.5
9.1
1.2
6
1
4
0.8
3.8
6.9 Switching Characteristics: CL = 30 or 50 pF, TA = –40°C to +85°C
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 4)
TA = –40°C to +85°C
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
PARAMETER
UNIT
MIN MAX
MIN MAX
MIN MAX
MIN MAX
fmax
tpd
160
160
160
160
MHz
ns
CLK
Q
3.9
9.9
2
7
1.7
5
1
4.5
6.10 Switching Characteristics: CL = 30 pF or 50 pF, TA = –40°C to +125°C
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 4)
TA = –40°C to +125°C
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
PARAMETER
UNIT
MIN MAX
MIN MAX
MIN MAX
MIN MAX
fmax
tpd
160
160
160
160
MHz
ns
CLK
Q
3.9
12
2
8.5
1.7
6
1
5
6.11 Operating Characteristics
TA = 25°C
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
VCC = 5 V
TYP
TEST
CONDITIONS
PARAMETER
UNIT
Cpd
Power dissipation capacitance
f = 10 MHz
26
26
27
30
pF
Copyright © 2017, Texas Instruments Incorporated
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6.12 Typical Characteristics
This plot shows the different ICC values for various voltages on the data input (D). Voltage sweep on the input is from 0 V to
6.5 V.
2
1.8
1.6
1.4
1.2
1
20
18
16
14
12
10
8
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5.0 V
0.8
0.6
0.4
0.2
0
6
4
2
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Data (D) Input Voltage [V]
Data (D) Input Voltage [V]
ICCv
ICCv
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
Figure 1. Supply Current (ICC) vs Data (D) Input Voltage
Figure 2. Supply Current (ICC) vs Data (D) Input Voltage
8
Copyright © 2017, Texas Instruments Incorporated
SN74LVC1G79-Q1
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ZHCSG59 –MARCH 2017
7 Parameter Measurement Information
VLOAD
Open
GND
S1
RL
From Output
Under Test
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
VLOAD
GND
CL
(see Note A)
RL
LOAD CIRCUIT
INPUTS
VCC
VM
VLOAD
CL
RL
V
D
VI
tr/tf
VCC
VCC
3 V
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
£2 ns
£2 ns
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6 V
15 pF
15 pF
15 pF
15 pF
1 MW
0.15 V
0.15 V
0.3 V
1 MW
1 MW
1 MW
£2.5 ns
£2.5 ns
2 × VCC
0.3 V
VI
Timing Input
Data Input
VM
0 V
tW
tsu
th
VI
VI
Input
VM
VM
VM
VM
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VI
Output
Control
VM
VM
Input
VM
VM
0 V
0 V
tPZL
tPLZ
tPLH
tPHL
VM
Output
Waveform 1
S1 at VLOAD
VOH
VOL
VLOAD/2
VOL
VM
VM
Output
Output
VOL + V
D
(see Note B)
tPHL
tPLH
tPZH
tPHZ
VOH
VOL
Output
Waveform 2
S1 at GND
VOH
VOH – V
D
VM
VM
VM
»0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
VLOAD
Open
GND
S1
RL
From Output
Under Test
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
VLOAD
GND
CL
(see Note A)
RL
LOAD CIRCUIT
INPUTS
VCC
VM
VLOAD
CL
RL
V
D
VI
tr/tf
VCC
VCC
3 V
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
£2 ns
£2 ns
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6 V
30 pF
30 pF
50 pF
50 pF
1 kW
0.15 V
0.15 V
0.3 V
500 W
500 W
500 W
£2.5 ns
£2.5 ns
2 × VCC
0.3 V
VI
Timing Input
Data Input
VM
0 V
tW
tsu
th
VI
VI
Input
VM
VM
VM
VM
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VI
Output
Control
VM
VM
Input
VM
VM
0 V
0 V
tPZL
tPLZ
tPLH
tPHL
VM
Output
Waveform 1
S1 at VLOAD
VOH
VOL
VLOAD/2
VOL
VM
VM
Output
Output
VOL + V
D
(see Note B)
tPHL
tPLH
tPZH
tPHZ
VOH
VOL
Output
Waveform 2
S1 at GND
VOH
VOH – V
D
VM
VM
VM
»0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
10
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ZHCSG59 –MARCH 2017
8 Detailed Description
8.1 Overview
The SN74LVC1G79-Q1 is a single positive-edge-triggered D-type flip-flop and is AEC-Q100 qualified for
automotive applications. Data at the input (D) is transferred to the output (Q) on the positive-going edge of the
clock pulse when the setup time requirement is met. Because the clock triggering occurs at a voltage level, it is
not directly related to the rise time of the clock pulse. This allows for data at the input to be changed without
affecting the level at the output, following the hold-time interval.
8.2 Functional Block Diagram
2
C
CLK
C
C
4
TG
Q
C
C
C
C
1
D
TG
TG
TG
C
C
C
Copyright © 2017, Texas Instruments Incorporated
Figure 5. Logic Diagram (Positive Logic)
8.3 Feature Description
8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and
damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings must
be followed at all times.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Recommended Operating Conditions, and the maximum input leakage current, given
in the Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions to avoid excessive currents and oscillations. If tolerance to a slow or noisy input signal is required, a
device with a Schmitt-trigger input should be utilized to condition the input signal prior to the standard CMOS
input.
Copyright © 2017, Texas Instruments Incorporated
11
SN74LVC1G79-Q1
ZHCSG59 –MARCH 2017
www.ti.com.cn
Feature Description (continued)
8.3.3 Clamp Diodes
The inputs and outputs to this device have negative clamping diodes.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
VCC
Device
Input
Output
Logic
GND
-IIK
-IOK
Figure 6. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.4 Partial Power Down (Ioff
)
The inputs and outputs for this device enter a high impedance state when the supply voltage is 0 V. The
maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical
Characteristics.
8.3.5 Over-Voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Absolute Maximum Ratings.
8.4 Device Functional Modes
Table 1 lists the functional modes of SN74LVC1G79-Q1.
Table 1. Function Table
INPUTS
OUTPUT
Y
CLK
D
H
L
↑
↑
L
H
L
X
Q0
12
Copyright © 2017, Texas Instruments Incorporated
SN74LVC1G79-Q1
www.ti.com.cn
ZHCSG59 –MARCH 2017
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A useful application for the SN74LVC1G79-Q1 is using it as a data latch with low-voltage data retention. This
application implements the use of a microcontroller GPIO pin to act as a clock to set the output state and a
second GPIO to provide the input data. If the SN74LVC1G79-Q1 is being powered from 1.8 V and there is
concern that a power glitch could exist as low as 1.5 V, the device will retain the state of the Q output. An
example of this data retention is shown in Figure 8 where the VCC drops to 1.5 V and the Q output maintains the
HIGH output state when VCC returns to 1.8 V. If the VCC voltage drops below 1.5 V, data retention is not
guaranteed.
9.2 Typical Application
VCC > 1.65V for Operation
VCC > 1.50V for Data Retention
GPIO
CLK
VCC
D
5
4
1
2
3
MCU
{b74[ë/1D79
CLK
GND
Q
Copyright © 2017, Texas Instruments Incorporated
Figure 7. Low Voltage Data Retention With SN74LVC1G79-Q1
9.2.1 Design Requirements
The SN74LVC1G79-Q1 device uses CMOS technology and has balanced output drive. Take care to avoid bus
contention because it can drive currents that would exceed maximum limits.
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
–
–
–
For rise time and fall time specifications, see Δt/Δv in Recommended Operating Conditions.
For specified high and low levels, see VIH and VIL in Recommended Operating Conditions.
Input voltages are recommended to not go below 0 V and not exceed 5.5 V for any VCC. See
Recommended Operating Conditions.
2. Recommended output conditions:
–
–
Load currents should not exceed ±50 mA. See Absolute Maximum Ratings.
Output voltages are recommended to not go below 0 V and not exceed the VCC voltage. See
Recommended Operating Conditions.
Copyright © 2017, Texas Instruments Incorporated
13
SN74LVC1G79-Q1
ZHCSG59 –MARCH 2017
www.ti.com.cn
Typical Application (continued)
9.2.3 Application Curve
ꢁositive {upply ëoltage (ë//)
bon-inverted hutput (ꢀ)
Figure 8. Data Retention With VCC Glitch Down to 1.5 V
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in
Recommended Operating Conditions. A 0.1-µF bypass capacitor is recommended to be connected from the VCC
terminal to GND to prevent power disturbance. To reject different frequencies of noise, use multiple bypass
capacitors in parallel. Capacitors with values of 0.1 µF and 1 µF are commonly used in parallel. The bypass
capacitor must be installed as close to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. Figure 9 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
11.2 Layout Example
WORST
BETTER
BEST
1W min.
W
Figure 9. Trace Example
14
版权 © 2017, Texas Instruments Incorporated
SN74LVC1G79-Q1
www.ti.com.cn
ZHCSG59 –MARCH 2017
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
相关文档请参阅以下部分：
•
•
•
《慢速或浮点 CMOS 输入的影响》，SCBA004
《了解和解读标准逻辑器件数据表》，SZZA036
《计时器件的加电行为》，SCHA005
12.2 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械封装、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且
不对本文档进行修订的情况下发生改变。要获得这份数据表的浏览器版本，请查阅左侧导航栏。
版权 © 2017, Texas Instruments Incorporated
15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74LVC1G79QDCKRQ1
SN74LVC1G79QDCKTQ1
ACTIVE
ACTIVE
SC70
SC70
DCK
DCK
5
5
3000 RoHS & Green
250 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
16S
16S
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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