SN74LVC1G86QDCKRQ1 [TI]
汽车类单路 2 输入、1.65V 至 5.5V XOR（异或）门 | DCK | 5 | -40 to 125;
| 型号： | SN74LVC1G86QDCKRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类单路 2 输入、1.65V 至 5.5V XOR（异或）门 | DCK | 5 | -40 to 125 光电二极管 逻辑集成电路 石英晶振 触发器 |
| 文件： | 总19页 (文件大小：672K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN74LVC1G86-Q1
ZHCSG58 –MARCH 2017
SN74LVC1G86-Q1 单路 2 输入异或门
1 特性
3 说明
1
•
•
符合汽车应用 要求
具有符合 AEC-Q100 标准的下列结果：
SN74LVC1G86-Q1 是一款符合汽车要求的器件，并以
正逻辑执行布尔函数 Y = AB + AB。该单路 2 输入异
或门适用于 1.65V 至 5.5V VCC 运行环境。
–
±4000 V 人体放电模型 (HBM) ESD 分类等级
3A
如果一个输入为低电平，另一个输入则可在输出时重新
生成真实形态。如果一个输入为高电平，另一个输入的
信号则可在输出时重新生成反向信号。该器件功耗
低，3.3V 和 50pF 电容性负载条件下 tpd 最大值为
6ns。最大输出驱动为 ±32mA/4.5V 和 ±24mA/3.3V。
–
±1000 V 带电器件模型 (CDM) ESD 分类等级
C5
•
•
•
•
•
•
•
•
支持 5V VCC 运行
输入为高达 5.5V 过压容差
支持下行转换到 VCC
低功耗，ICC 最大值为 15µA
3.3V 和 50pF 负载条件下 tpd 最大值为 6ns
电压为 3.3V 时，输出驱动为 ±24mA
该器件完全 适用于 使用 Ioff 的局部掉电应用。Ioff 电路
可禁用输出，以防在器件断电时电流回流对器件造成损
坏。
Ioff 支持部分断电模式和后驱动保护
器件信息(1)
封装
锁断性能超过 100mA，符合 JESD 78 II 类规范的
要求
器件型号
封装尺寸（标称值）
SN74LVC1G86QDCKRQ1
SC70 (5)
2.00mm × 1.25mm
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
2 应用
•
•
•
•
混合动力汽车/电动汽车 (HEV/EV) 和动力总成
汽车信息娱乐系统与组合仪表
汽车高级驾驶员辅助系统
汽车车身电子设备
功能框图
EXCLUSIVE OR
= 1
Copyright © 2017, Texas Instruments Incorporated
异或门具有多种 应用，并可用其他逻辑符号更好地表示其中部分应用。
共有五种等效异或门符号适用于采用正逻辑的 SN74LVC1G86-Q1 门；任意两个端口可能显示否定逻辑。
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SCES873
SN74LVC1G86-Q1
ZHCSG58 –MARCH 2017
www.ti.com.cn
目录
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Function Table .......................................................... 9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics, CL = 30 pF or 50 pF........ 6
6.7 Operating Characteristics.......................................... 6
6.8 Typical Characteristics.............................................. 6
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
9
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 器件和文档支持 ..................................................... 13
12.1 接收文档更新通知 ................................................. 13
12.2 社区资源................................................................ 13
12.3 商标....................................................................... 13
12.4 静电放电警告......................................................... 13
12.5 Glossary................................................................ 13
13 机械、封装和可订购信息....................................... 13
7
8
4 修订历史记录
日期
修订版本
注释
2017 年 3 月
*
初始发行版。
2
Copyright © 2017, Texas Instruments Incorporated
SN74LVC1G86-Q1
www.ti.com.cn
ZHCSG58 –MARCH 2017
5 Pin Configuration and Functions
DCK Package
5-Pin SC70
Top View
VCC
1
2
3
5
A
B
4
GND
Y
Pin Functions(1)
PIN
I/O
DESCRIPTION
NO.
1
NAME
A
I
Input A
Input B
Ground
Output Y
2
B
I
3
GND
Y
—
O
—
4
5
VCC
Positive Supply
(1) See mechanical drawings for dimensions.
Copyright © 2017, Texas Instruments Incorporated
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ZHCSG58 –MARCH 2017
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
MAX
UNIT
V
VCC Supply voltage
6.5
6.5
VI
Input voltage(2)
V
VO
VO
IIK
Voltage applied to any output in the high-impedance or power-off state(2)
Voltage applied to any output in the high or low state(2)(3)
Input clamp current
6.5
V
VCC + 0.5
–50
V
VI < 0
mA
mA
mA
mA
°C
°C
IOK
IO
Output clamp current
VO < 0
–50
Continuous output current
±50
Continuous current through VCC or GND
Junction temperature
±100
150
TJ
Tstg
Storage temperature
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
1.65
MAX
UNIT
Operating
5.5
VCC Supply voltage
V
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
1.5
0.65 × VCC
1.7
VIH
High-level input voltage
V
2
0.7 × VCC
0.35 × VCC
0.7
VIL
Low-level input voltage
V
0.8
0.3 × VCC
5.5
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC
VCC = 1.65 V
VCC = 2.3 V
–4
–8
IOH
High-level output current
–16
mA
VCC = 3 V
–24
VCC = 4.5 V
–32
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
4
Copyright © 2017, Texas Instruments Incorporated
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ZHCSG58 –MARCH 2017
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
4
UNIT
VCC = 1.65 V
VCC = 2.3 V
8
IOL
Low-level output current
16
24
32
20
10
5
mA
VCC = 3 V
VCC = 4.5 V
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
Δt/Δv Input transition rise or fall rate
ns/V
°C
TA
Operating free-air temperature
DCK package
–40
125
6.4 Thermal Information
SN74LVC1G86-Q1
DCK (SC70)
5 PINS
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
277.6
°C/W
°C/W
°C/W
°C/W
°C/W
179.5
75.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
49.7
ψJB
75.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 5.5 V
1.65 V
MIN
VCC – 0.1
1.2
TYP(1)
MAX UNIT
IOH = –100 µA
IOH = –4 mA
IOH = –8 mA
IOH = –16 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 µA
IOL = 4 mA
2.3 V
1.9
VOH
V
2.4
3 V
2.3
4.5 V
1.65 V to 5.5 V
1.65 V
3.8
0.1
0.45
IOL = 8 mA
2.3 V
0.3
V
VOL
IOL = 16 mA
IOL = 24 mA
IOL = 32 mA
0.4
3 V
0.55
0.55
4.5 V
0 to 5.5 V
0
II A or B input VI = 5.5 V or GND
±5
±10
15
µA
µA
µA
Ioff
VI or VO = 5.5 V
ICC
VI = VCC or GND, IO = 0
1.65 V to 5.5 V
One input at VCC – 0.6 V,
Other inputs at VCC or GND
ΔICC
3 V to 5.5 V
3.3 V
500
µA
pF
Ci
VI = VCC or GND
6
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
Copyright © 2017, Texas Instruments Incorporated
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6.6 Switching Characteristics, CL = 30 pF or 50 pF
over recommended operating free-air temperature range (unless otherwise noted)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
UNIT
MIN MAX
MIN MAX
MIN MAX
MIN MAX
–40°C to 125°C temperature
range, see Figure 2
tpd
A or B
Y
3.5
12
1.8
7
1.3
6
1
5
ns
6.7 Operating Characteristics
TA = 25°C
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
TYP
TYP
Cpd
Power dissipation capacitance
f = 10 MHz
22
22
22
24
pF
6.8 Typical Characteristics
ëhI(ë)
5
4.5
4
3.5
3
ë// =4.5 ë
ëLI =3.1 ë
ëL[ =1.35 ë
2.5
2
1.5
85o
25o
/
/
1
0.5
-40o
/
0
-0.5
-1
0
20
40
60
80
100
120
140
160
180
200
LhI(m!)
Figure 1. Voh vs Ioh at 4.5 V
6
Copyright © 2017, Texas Instruments Incorporated
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ZHCSG58 –MARCH 2017
7 Parameter Measurement Information
VLOAD
Open
GND
S1
RL
From Output
Under Test
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
VLOAD
GND
CL
(see Note A)
RL
LOAD CIRCUIT
INPUTS
VCC
VM
VLOAD
CL
RL
VD
VI
tr/tf
VCC
VCC
3 V
VCC
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5 V 0.5 V
≤2 ns
≤2 ns
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6 V
15 pF
15 pF
15 pF
15 pF
1 MΩ
0.15 V
0.15 V
0.3 V
1 MΩ
1 MΩ
1 MΩ
≤2.5 ns
≤2.5 ns
2 × VCC
0.3 V
VI
Timing Input
Data Input
VM
0 V
tW
tsu
th
VI
VI
Input
VM
VM
VM
VM
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VI
Output
Control
VM
VM
Input
VM
VM
0 V
0 V
tPZL
tPLZ
tPLH
tPHL
VM
Output
Waveform 1
S1 at VLOAD
VOH
VOL
VLOAD/2
VOL
VM
VM
Output
Output
VOL + VD
(see Note B)
tPHL
tPLH
tPZH
tPHZ
VOH
VOL
Output
Waveform 2
S1 at GND
VOH
VOH – VD
VM
VM
VM
»0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
Copyright © 2017, Texas Instruments Incorporated
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8 Detailed Description
8.1 Overview
The SN74LVC1G86-Q1 is an automotive qualified device that performs the Boolean function Y = AB + AB in
positive logic. This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
A common application is as a true and complement element. If the input is low, the other input is reproduced in
true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram
EXCLUSIVE OR
= 1
Copyright © 2017, Texas Instruments Incorporated
These are five equivalent exclusive-OR symbols valid for an SN74LVC1G86-Q1 gate in positive logic; negation may
be shown at any two ports.
8.3 Feature Description
8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and
damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings must
be followed at all times.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Recommended Operating Conditions, and the maximum input leakage current, given
in the Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions to avoid excessive currents and oscillations. If tolerance to a slow or noisy input signal is required, a
device with a Schmitt-trigger input should be utilized to condition the input signal prior to the standard CMOS
input.
8
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ZHCSG58 –MARCH 2017
Feature Description (continued)
8.3.3 Clamp Diodes
The inputs and outputs to this device have negative clamping diodes.
CAUTION
Avoid any voltage below or above the input or output voltage specified in the Absolute
Maximum Ratings. In this event, the current must be limited to the maximum input or
output clamp current value indicated in the Absolute Maximum Ratings to avoid
damage to the device.
VCC
Device
Input
Output
Logic
GND
-IIK
-IOK
Figure 3. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.4 Partial Power Down (Ioff
)
The inputs and outputs for this device enter a high impedance state when the supply voltage is 0 V. The
maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical
Characteristics.
8.3.5 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Recommended Operating Conditions.
8.4 Function Table
Table 1 lists the functional modes of the SN74LVC1G86-Q1 device.
Table 1. Function Table
INPUTS
OUTPUT
Y
A
L
B
L
L
H
H
L
L
H
L
H
H
H
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G86-Q1 device can accept input voltages up to 5.5 V at any valid VCC which makes the device
suitable for down translation. This feature of the SN74LVC1G86-Q1 makes it ideal for various bus interface
applications.
9.2 Typical Application
3.3-V or 5-V regulated
0.1 µF
5-V accessory
µC or
System
Logic
5-V
System
Logic
Figure 4. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads,
so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
–
–
–
For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table.
For specified High and low levels, see VIH and VIL in the Recommended Operating Conditions table.
Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC
.
2. Recommended Output Conditions
–
–
Load currents should not exceed 32 mA per output and 50 mA total for the part.
Outputs should not be pulled above VCC
.
10
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ZHCSG58 –MARCH 2017
Typical Application (continued)
9.2.3 Application Curve
100
90
80
70
60
ëLI = 4.5ë
ëL[= 0ë
ë// = 5.5ë
Çemp =25o /
50
40
[ow->Iigh
Iigh->[ow
30
20
10
0
0
0.5
1
1.5
6
2
2.5
3
3.5
4
4.5
5
5.5
ëLb (ë)
Figure 5. ICC vs. VIN
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,
0.1 µF is recommended. If there are multiple VCC pins, 0.01 µF or 0.022 µF is recommended for each power pin.
It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1-µF and 1-µF are
commonly used in parallel. The bypass capacitor must be installed as close to the power pin as possible for best
results.
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11 Layout
11.1 Layout Guidelines
Even low data rate digital signals can have high frequency signal components due to fast edge rates. When a
PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the
change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. Figure 6 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
11.2 Layout Example
WORST
BETTER
BEST
1W min.
W
Figure 6. Trace Example
12
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ZHCSG58 –MARCH 2017
12 器件和文档支持
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。请单击右上角的通知我进行注册，即可收到任意产品
信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
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版权 © 2017, Texas Instruments Incorporated
13
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74LVC1G86QDCKRQ1
SN74LVC1G86QDCKTQ1
ACTIVE
ACTIVE
SC70
SC70
DCK
DCK
5
5
3000 RoHS & Green
250 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
16T
16T
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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