SN74LVC1G97YZAR [TI]
CONFIGURABLE MULTIPLE-FUNCTION GATE; 可配置多函数栅型号: | SN74LVC1G97YZAR |
厂家: | TEXAS INSTRUMENTS |
描述: | CONFIGURABLE MULTIPLE-FUNCTION GATE |
文件: | 总17页 (文件大小:516K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN74LVC1G97
CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES416I–DECEMBER 2002–REVISED MARCH 2006
FEATURES
•
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
•
•
•
•
•
•
Supports 5-V VCC Operation
ESD Protection Exceeds JESD 22
Inputs Accept Voltages to 5.5 V
Max tpd of 6.3 ns at 3.3 V
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
– 1000-V Charged-Device Model (C101)
Choose From Nine Specific Logic Functions
•
Ioff Supports Partial-Power-Down Mode
Operation
YEA, YEP, YZA,
DCK PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
OR YZP PACKAGE
(BOTTOM VIEW)
3
4
Y
V
In0
GND
In1
1
2
3
6
5
4
In1
GND
In0
In2
In1
GND
In0
In2
1
2
3
6
5
4
1
2
3
6
In1
GND
In0
In2
V
2 5
CC
V
Y
CC
V
Y
CC
1
6
In2
5
4
CC
Y
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This configurable multiple-function gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G97 features configurable multiple functions. The output state is determined by eight patterns of
3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. All
inputs can be connected to VCC or GND.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)
NanoStar™ – WCSP (DSBGA)
0.17-mm Small Bump – YEA
SN74LVC1G97YEAR
NanoFree™ – WCSP (DSBGA)
0.17-mm Small Bump – YZA (Pb-free)
SN74LVC1G97YZAR
_ _ _CS_
Tape and reel
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
SN74LVC1G97YEPR
–40°C to 85°C
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SN74LVC1G97YZPR
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
SOT (SOT-563) – DRL
Tape and reel
Tape and reel
Reel of 4000
SN74LVC1G97DBVR
SN74LVC1G97DCKR
SN74LVC1G97DRLR
C97_
CS_
CS_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA,YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC1G97
CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES416I–DECEMBER 2002–REVISED MARCH 2006
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device functions as an independent gate, but because of Schmitt action, it may have different input
threshold levels for positive-going (VT+) and negative-going (VT–) signals.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
INPUTS
OUTPUT
In2
L
In1
L
In0
L
Y
L
L
L
H
L
L
L
H
H
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
L
H
H
H
H
LOGIC DIAGRAM (POSITIVE LOGIC)
3
1
In0
In1
4
Y
6
In2
FUNCTION SELECTION TABLE
LOGIC FUNCTION
2-to-1 data selector
FIGURE NO.
1
2
3
3
4
4
5
6
7
2-input AND gate
2-input OR gate with one inverted input
2-input NAND gate with one inverted input
2-input AND gate with one inverted input
2-input NOR gate with one inverted input
2-input OR gate
Inverter
Noninverted buffer
2
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SN74LVC1G97
CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES416I–DECEMBER 2002–REVISED MARCH 2006
LOGIC CONFIGURATIONS
V
CC
V
CC
A/B
A
1
2
3
6
5
4
A/B
Y
1
2
3
6
5
4
A
Y
A
B
Y
A
B
Y
B
B
GND
GND
Figure 2. 2-Input AND Gate
Figure 1. 2-to-1 Data Selector
V
CC
V
CC
A
B
A
B
Y
Y
Y
Y
1
2
3
6
5
4
A
Y
B
1
2
3
6
5
4
A
Y
A
B
A
B
B
GND
GND
Figure 3. 2-Input OR Gate With One Inverted Input
2-Input NAND Gate With One Inverted Input
Figure 4. 2-Input AND Gate With One Inverted Input
2-Input NOR Gate With One Inverted Input
V
CC
V
CC
A
B
1
2
3
6
5
4
A
Y
1
2
3
6
5
4
A
Y
B
Y
A
Y
GND
GND
Figure 6. Inverter
Figure 5. 2-Input OR Gate
V
CC
A
1
2
3
6
5
4
A
Y
Y
GND
Figure 7. Noninverted Buffer
3
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SN74LVC1G97
CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES416I–DECEMBER 2002–REVISED MARCH 2006
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
6.5
6.5
V
V
VO
VO
IIK
6.5
V
VCC + 0.5
–50
V
Input clamp current
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
–50
Continuous output current
Continuous current through VCC or GND
±50
±100
165
DBV package
DCK package
259
θJA
Package thermal impedance(4)
DRL package
142 °C/W
143
YEA/YZA package
YEP/YZP package
123
Tstg
Storage temperature range
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
1.65
1.5
0
MAX UNIT
Operating
5.5
V
VCC
Supply voltage
Data retention only
VI
Input voltage
5.5
VCC
–4
V
V
VO
Output voltage
0
VCC = 1.65 V
VCC = 2.3 V
–8
IOH
High-level output current
–16
–24
–32
4
mA
VCC = 3 V
VCC = 4.5 V
VCC = 1.65 V
VCC = 2.3 V
8
IOL
Low-level output current
16
mA
°C
VCC = 3 V
24
VCC = 4.5 V
32
TA
Operating free-air temperature
–40
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SN74LVC1G97
CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES416I–DECEMBER 2002–REVISED MARCH 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V
2.3 V
MIN TYP(1)
0.79
1.11
1.5
MAX
1.16
1.56
1.87
2.74
3.33
0.62
0.87
1.19
1.9
UNIT
VT+
Positive-going input
threshold voltage
3 V
V
4.5 V
2.16
2.61
0.35
0.58
0.84
1.41
1.87
0.3
5.5 V
1.65 V
2.3 V
VT–
Negative-going input
threshold voltage
3 V
V
V
4.5 V
5.5 V
2.29
0.62
0.8
1.65 V
2.3 V
0.4
∆VT
3 V
0.53
0.71
0.71
0.87
1.04
1.11
Hysteresis (VT+ – VT–
)
4.5 V
5.5 V
IOH = –100 µA
1.65 V to 5.5 V
1.65 V
2.3 V
VCC – 0.1
IOH = –4 mA
1.2
1.9
2.4
2.3
3.8
IOH = –8 mA
VOH
V
V
IOH = –16 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 µA
IOL = 4 mA
3 V
4.5 V
1.65 V to 5.5 V
1.65 V
0.1
0.45
0.3
IOL = 8 mA
2.3 V
VOL
IOL = 16 mA
0.4
3 V
IOL = 24 mA
0.55
0.55
±5
IOL = 32 mA
4.5 V
0 to 5.5 V
0
II
VI = 5.5 V or GND
VI or VO = 5.5 V
VI = 5.5 V or GND, IO = 0
µA
µA
µA
Ioff
ICC
±10
10
1.65 V to 5.5 V
One input at VCC – 0.6 V,
Other inputs at VCC or GND
∆ICC
3 V to 5.5 V
3.3 V
500
µA
Ci
VI = VCC or GND
3.5
pF
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
5
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SN74LVC1G97
CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES416I–DECEMBER 2002–REVISED MARCH 2006
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 8)
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
3.2 14.4 8.3 1.5 6.3 1.1 5.1
tpd
Any In
Y
2
ns
Operating Characteristics
TA = 25°C
VCC = 1.8 V
TYP
VCC = 2.5 V
VCC = 3.3 V
TYP
VCC = 5 V
TYP
TEST
CONDITIONS
PARAMETER
UNIT
TYP
Cpd
Power dissipation capacitance
f = 10 MHz
22
23
23
26
pF
6
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SN74LVC1G97
CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES416I–DECEMBER 2002–REVISED MARCH 2006
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
V
R
L
PLZ PZL
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
V
V
3 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
/2
/2
2 × V
2 × V
6 V
2 × V
CC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
V
CC
CC
CC
1.5 V
/2
V
CC
V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
LOAD
V
OL
+ V
∆
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
− V
∆
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 8. Load Circuit and Voltage Waveforms
7
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2006
PACKAGING INFORMATION
Orderable Device
SN74LVC1G97DBVR
SN74LVC1G97DBVRE4
SN74LVC1G97DBVT
SN74LVC1G97DBVTE4
SN74LVC1G97DCKR
SN74LVC1G97DCKRE4
SN74LVC1G97DCKRG4
SN74LVC1G97DCKT
SN74LVC1G97DCKTE4
SN74LVC1G97DRLR
SN74LVC1G97DRLRG4
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
6
6
6
6
6
6
6
6
6
6
6
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT-23
SOT-23
SOT-23
SC70
SC70
SC70
SC70
SC70
SOP
DBV
DBV
DBV
DCK
DCK
DCK
DCK
DCK
DRL
DRL
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOP
4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC1G97YEAR
SN74LVC1G97YEPR
SN74LVC1G97YZAR
NRND
NRND
NRND
WCSP
WCSP
WCSP
YEA
YEP
YZA
6
6
6
3000
3000
3000
TBD
TBD
SNPB
SNPB
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Pb-Free
(RoHS)
SNAGCU
SN74LVC1G97YZPR
ACTIVE
WCSP
YZP
6
3000
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2006
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
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