SN74LVC1G99DCUT [TI]
ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE WITH 3-STATE OUTPUTS; 具有三态输出超可配置的多功能的门
| 型号： | SN74LVC1G99DCUT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE WITH 3-STATE OUTPUTS |
| 文件： | 总18页 (文件大小：399K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCES609B − SEPTEMBER 2004 – REVISED JANUARY 2005
DCT OR DCU PACKAGE
(TOP VIEW)
D
Available in Texas Instruments NanoStar
and NanoFree Packages
D
D
D
D
D
D
Supports 5-V V
Operation
CC
OE
A
B
V
Y
D
C
1
2
3
4
8
7
6
5
CC
Inputs Accept Voltages to 5.5 V
Max t of 6.7 ns at 3.3 V
pd
Low Power Consumption, 10-µA Max I
GND
CC
24-mA Output Drive at 3.3 V
YEP OR YZP PACKAGE
(BOTTOM VIEW)
Offers Nine Different Logic Functions in a
Single Package
4 5
3 6
2 7
1 8
GND
B
A
OE
C
D
Y
D
D
I
Supports Partial-Power-Down Mode
off
Operation
Input Hysteresis Allows for Slow Input
Transition Time and Better Noise Immunity
at Input
V
CC
D
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
The SN74LVC1G99 is operational from 1.65 V to 5.5 V.
The SN74LVC1G99 features configurable multiple functions with a 3-state output. The output is disabled when
the output-enable (OE) input is high. When OE is low, the output state is determined by 16 patterns of 4-bit input.
The user can choose logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and buffer.
All inputs can be connected to V
or GND.
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
‡
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
SN74LVC1G99YEPR
SN74LVC1G99YZPR
Reel of 3000
DE_
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
−40°C to 85°C
Reel of 3000
Reel of 250
Reel of 3000
SN74LVC1G99DCTR
SN74LVC1G99DCTT
SN74LVC1G99DCUR
SSOP − DCT
C99_ _ _
C99_
VSSOP − DCU
Reel of 250
SN74LVC1G99DCUT
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin
1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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Copyright 2005, Texas Instruments Incorporated
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ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉꢉ
ꢊ ꢄꢋ ꢌ ꢍꢎ ꢆꢏꢁ ꢐ ꢑ ꢈꢊ ꢌꢍꢒ ꢄꢓ ꢔꢊ ꢄꢋꢑ ꢕ ꢄ ꢓꢎꢐ ꢊꢁꢆꢋ ꢑ ꢏꢁ ꢈ ꢍꢋ ꢓ
ꢖꢑ ꢋ ꢗ ꢘ ꢎꢀꢋꢍꢋ ꢓ ꢏꢊꢋ ꢕꢊ ꢋꢀ
SCES609B − SEPTEMBER 2004 – REVISED JANUARY 2005
description/ordering information (continued)
This device functions as an independent inverter, but because of Schmitt action, it has different input threshold
levels for positive-going (V ) and negative-going (V ) signals.
T+
T−
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
FUNCTION TABLE
INPUTS
OUTPUT
Y
OE
L
D
L
L
C
L
L
B
L
L
A
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
H
L
L
H
L
L
H
H
H
H
L
L
L
H
L
L
L
H
H
L
H
H
H
L
L
H
L
H
H
H
H
H
H
L
L
H
L
L
H
H
L
H
L
L
H
L
H
H
H
H
L
H
L
L
H
H
H
H
H
H
L
H
L
L
Z
H
H or L
H or L
H or L
H or L
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCES609B − SEPTEMBER 2004 – REVISED JANUARY 2005
logic diagram (positive logic)
1
OE
2
A
3
B
7
5
Y
C
6
D
FUNCTION SELECTION TABLE
COMPLEMENTARY FUNCTION
PRIMARY FUNCTION
PAGE
3-state buffer
3
3
4
4
5
3-state inverter
3-state 2-in-1 data selector MUX
3-state 2-in-1 data selector MUX, inverted out
3-state 2-input AND
3-state 2-input NOR, both inputs inverted
3-state 2-input AND, one input inverted
3-state 2-input AND, both inputs inverted
3-state 2-input NAND
3-state 2-input NOR, one input inverted
3-state 2-input NOR
5
5
6
6
6
7
7
3-state 2-input OR, both inputs inverted
3-state 2-input OR, one input inverted
3-state 2-input OR
3-state 2-input NAND, one input inverted
3-state 2-input NAND, both inputs inverted
3-state 2-input XOR
3-state 2-input XNOR
3-state 2-input XOR, one input inverted
3-STATE BUFFER FUNCTIONS AVAILABLE
OE
Input
Y
FUNCTION
OE
A
Input
H or L
L
B
H or L
Input
H
C
D
L
L
H
L
Input
Input
L
L
3-state buffer
L
H
L
H
H
H or L
L
Input
Input
Input
H or L
L
H
L
H or L
3
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ꢖꢑ ꢋ ꢗ ꢘ ꢎꢀꢋꢍꢋ ꢓ ꢏꢊꢋ ꢕꢊ ꢋꢀ
SCES609B − SEPTEMBER 2004 – REVISED JANUARY 2005
3-STATE INVERTER FUNCTIONS AVAILABLE
OE
Input
Y
FUNCTION
OE
A
B
H or L
Input
H
C
L
D
H
Input
X
H
H
L
H
Input
Input
L
H
3-state inverter
L
L
L
H
H or L
H
Input
Input
Input
H or L
H
H
H
H or L
3-STATE MUX FUNCTIONS AVAILABLE
OE
OE
A/B
A/B
Input 1
Input 2
Input 1
Input 2
Y
Y
FUNCTION
OE
A
B
C
D
L
3-state 2-to-1
3-state 2-to-1
3-state 2-to-1
3-state 2-to-1
Input 1
Input 2
Input 1
Input 2
Input 2
Input 1
Input 2
Input 1
Input 1 or Input 2
Input 2 or Input 1
Input 1 or Input 2
Input 2 or Input 1
L
L
H
H
4
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SCES609B − SEPTEMBER 2004 – REVISED JANUARY 2005
3-STATE AND/NOR FUNCTIONS AVAILABLE
OE
OE
Input 1
Input 1
Input 2
Y
Y
Input 2
NO. OF INPUTS
AND/NAND FUNCTION
3-state AND
OR/NOR FUNCTION
3-state NOR
OE
A
L
L
B
C
D
L
L
2
2
Input 1 Input 2
Input 2 Input 1
L
3-state AND
3-state NOR
OE
OE
Input 1
Input 2
Input 1
Input 2
Y
Y
NO. OF INPUTS
AND/NAND FUNCTION
3-state AND
OR/NOR FUNCTION
3-state NOR
OE
A
Input 2
H
B
C
D
L
2
2
L
Input 1
L
3-state AND
3-state NOR
Input 1 Input 2
H
OE
OE
Input 1
Input 2
Input 1
Input 2
Y
Y
NO. OF INPUTS
AND/NAND FUNCTION
3-state AND
OR/NOR FUNCTION
3-state NOR
OE
A
Input 1
H
B
C
D
L
2
2
L
Input 2
L
3-state AND
3-state NOR
Input 2 Input 1
H
OE
OE
Input 1
Input 2
Input 1
Input 2
Y
Y
NO. OF INPUTS
AND/NAND FUNCTION
3-state AND
OR/NOR FUNCTION
3-state NOR
OE
A
B
H
H
C
D
L
L
2
2
Input 1
Input 2
Input 2
Input 1
L
3-state AND
3-state NOR
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉꢉ
ꢊ ꢄꢋ ꢌ ꢍꢎ ꢆꢏꢁ ꢐ ꢑ ꢈꢊ ꢌꢍꢒ ꢄꢓ ꢔꢊ ꢄꢋꢑ ꢕ ꢄ ꢓꢎꢐ ꢊꢁꢆꢋ ꢑ ꢏꢁ ꢈ ꢍꢋ ꢓ
ꢖꢑ ꢋ ꢗ ꢘ ꢎꢀꢋꢍꢋ ꢓ ꢏꢊꢋ ꢕꢊ ꢋꢀ
SCES609B − SEPTEMBER 2004 – REVISED JANUARY 2005
3-STATE NAND/OR FUNCTIONS AVAILABLE
OE
OE
Input 1
Input 2
Input 1
Y
Y
Input 2
NO. OF INPUTS
AND/NAND FUNCTION
3-state NAND
OR/NOR FUNCTION
3-state OR
OE
A
L
L
B
C
D
H
H
2
2
Input 1 Input 2
Input 2 Input 1
L
3-state NAND
3-state OR
OE
OE
Input 1
Input 2
Input 1
Input 2
Y
Y
NO. OF INPUTS
AND/NAND FUNCTION
3-state NAND
OR/NOR FUNCTION
3-state OR
OE
A
Input 2
H
B
C
D
H
L
2
2
L
Input 1
L
3-state NAND
3-state OR
Input 1 Input 2
OE
OE
Input 1
Input 2
Input 1
Input 2
Y
Y
NO. OF INPUTS
AND/NAND FUNCTION
3-state NAND
OR/NOR FUNCTION
3-state OR
OE
A
Input 1
H
B
C
D
H
L
2
2
L
Input 2
L
3-state NAND
3-state OR
Input 2 Input 1
OE
OE
Input 1
Input 2
Input 1
Input 2
Y
Y
NO. OF INPUTS
AND/NAND FUNCTION
3-state NAND
OR/NOR FUNCTION
3-state OR
OE
A
B
H
H
C
D
L
L
2
2
Input 1
Input 2
Input 2
Input 1
L
3-state NAND
3-state OR
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCES609B − SEPTEMBER 2004 – REVISED JANUARY 2005
3-STATE XOR/XNOR FUNCTIONS AVAILABLE
OE
Input 1
Y
Input 2
FUNCTION
OE
A
B
C
D
Input 1
Input 2
H or L
H or L
L
H or L
H or L
Input 1
Input 2
H
L
L
Input 2
Input 1
Input 2
Input 1
Input 2
Input 1
H
3-state XOR
L
H
Input 1
Input 2
L
H
OE
Input 1
Input 2
Y
Y
Y
FUNCTION
OE
A
B
C
D
3-state XOR
L
H
L
Input 1
Input 2
OE
Input 1
Input 2
FUNCTION
3-state XOR
OE
A
B
C
D
L
H
L
Input 1
Input 2
OE
Input 1
Input 2
FUNCTION
3-state XNOR
3-state XNOR
OE
A
H
H
B
L
L
C
D
Input 1
Input 2
Input 2
Input 1
L
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉꢉ
ꢊ ꢄꢋ ꢌ ꢍꢎ ꢆꢏꢁ ꢐ ꢑ ꢈꢊ ꢌꢍꢒ ꢄꢓ ꢔꢊ ꢄꢋꢑ ꢕ ꢄ ꢓꢎꢐ ꢊꢁꢆꢋ ꢑ ꢏꢁ ꢈ ꢍꢋ ꢓ
ꢖꢑ ꢋ ꢗ ꢘ ꢎꢀꢋꢍꢋ ꢓ ꢏꢊꢋ ꢕꢊ ꢋꢀ
SCES609B − SEPTEMBER 2004 – REVISED JANUARY 2005
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
IK
I
Output clamp current, I
OK
O
O
Continuous current through V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 3): DCT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C/W
JA
DCU package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 102°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
MIN
1.65
1.5
0
MAX
UNIT
Operating
5.5
V
Supply voltage
V
CC
Data retention only
V
V
Input voltage
5.5
V
V
I
Output voltage
0
V
CC
−4
O
V
V
= 1.65 V
= 2.3 V
CC
−8
CC
−16
−24
−32
4
I
High-level output current
Low-level output current
mA
OH
OL
V
= 3 V
CC
V
CC
V
CC
V
CC
= 4.5 V
= 1.65 V
= 2.3 V
8
16
24
32
20
10
5
I
mA
V
CC
= 3 V
V
CC
V
CC
V
CC
V
CC
= 4.5 V
= 1.8 V 0.15 V, 2.5 V 0.2 V
= 3.3 V 0.3 V
= 5 V 0.5 V
∆t/∆v Input transition rise or fall rate
ns/V
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢊꢄꢋ ꢌꢍꢎꢆꢏ ꢁꢐ ꢑ ꢈꢊꢌ ꢍꢒꢄ ꢓ ꢔ ꢊꢄꢋ ꢑꢕ ꢄꢓ ꢎꢐꢊ ꢁꢆꢋꢑ ꢏ ꢁ ꢈ ꢍꢋ
ꢉ
ꢉ
ꢓ
ꢀ
ꢖ ꢑꢋ ꢗ ꢘ ꢎꢀꢋꢍꢋ ꢓ ꢏ ꢊꢋ ꢕꢊ ꢋ
SCES609B − SEPTEMBER 2004 – REVISED JANUARY 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
V
MIN
0.79
1.11
1.5
MAX
1.26
1.66
1.97
2.84
3.43
0.72
0.97
1.24
1.89
2.39
0.72
0.87
0.97
1.14
1.21
UNIT
CC
1.65 V
2.3 V
V
T+
Positive-going
input threshold
voltage
3 V
V
4.5 V
2.16
2.61
0.39
0.58
0.84
1.41
1.87
0.37
0.48
0.56
0.71
0.71
5.5 V
1.65 V
2.3 V
V
T−
Negative-going
input threshold
voltage
3 V
V
V
4.5 V
5.5 V
1.65 V
2.3 V
∆V
T
3 V
Hysteresis
(V − V
)
T+ T−
4.5 V
5.5 V
I
I
I
I
= −100 mA
= −4 mA
= −8 mA
= −16 mA
1.65 V to 5.5 V
1.65 V
2.3 V
V
CC
− 0.1
OH
OH
OH
OH
1.2
1.9
2.4
2.3
V
OH
V
3 V
I
= −24 mA
OH
4.5 V
1.65 V to 5.5 V
1.65 V
3.8
I
I
I
I
I
= −32 mA
= 100 mA
= 4 mA
OH
OL
OL
OL
OL
0.1
0.45
0.3
= 8 mA
2.3 V
V
OL
V
= 16 mA
0.4
3 V
0.55
I
I
= 24 mA
= 32 mA
OL
OL
4.5 V
0 to 5.5 V
0
0.55
5
I
V = 5.5 V or GND
mA
mA
mA
mA
mA
pF
pF
I
I
I
V or V = 5.5 V
10
off
I
O
I
V
= V
CC
or GND
1.65 V to 5.5 V
1.65 V to 5.5 V
3 V to 5.5 V
3.3 V
10
OZ
O
I
V = 5.5 V or GND,
I
I
= 0
10
CC
O
∆I
CC
One input at V
CC
− 0.6 V,
Other inputs at V
CC
or GND
500
C
V = V
I CC
or GND
or GND
3.5
6
i
C
V
= V
3.3 V
o
O CC
†
T
A
= 25°C
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉꢉ
ꢊ ꢄꢋ ꢌ ꢍꢎ ꢆꢏꢁ ꢐ ꢑ ꢈꢊ ꢌꢍꢒ ꢄꢓ ꢔꢊ ꢄꢋꢑ ꢕ ꢄ ꢓꢎꢐ ꢊꢁꢆꢋ ꢑ ꢏꢁ ꢈ ꢍꢋ ꢓ
ꢖꢑ ꢋ ꢗ ꢘ ꢎꢀꢋꢍꢋ ꢓ ꢏꢊꢋ ꢕꢊ ꢋꢀ
SCES609B − SEPTEMBER 2004 – REVISED JANUARY 2005
switching characteristics over recommended operating free-air temperature range, C = 15 pF
L
(unless otherwise noted) (see Figure 1)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
V
= 5 V
CC
0.15 V
CC
0.2 V
CC
0.3 V
CC
0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
30.1
28.3
29.1
25.1
MIN
MAX
11.3
10.8
11.7
10.2
MIN
MAX
7.5
MIN
1.3
1.3
1.3
1.3
MAX
A
B
4.5
4.4
4.4
4.3
3.4
4
2.5
2.4
2.4
2.4
2.1
2.7
1.8
1.8
1.9
1.7
1.3
3.5
4.8
4.7
5
7.2
t
t
Y
ns
pd
C
7.6
D
6.7
4.5
3.8
5.5
OE
OE
Y
Y
24.7
15.5
10
5.8
7
1
2
ns
ns
en
t
7.5
dis
switching characteristics over recommended operating free-air temperature range, C = 30 pF or
L
50 pF (unless otherwise noted) (see Figure 2)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
V
= 5 V
CC
0.15 V
CC
0.2 V
CC
0.3 V
CC
0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
30.8
28.9
29.8
25.7
MIN
MAX
11.7
11.3
12.3
10.7
MIN
MAX
8.4
MIN
1.8
1.8
1.8
1.6
MAX
A
B
4.6
4.6
4.4
4.3
4.2
3.7
2.6
2.6
2.5
2.5
2.4
2
2.4
2.3
2.5
2.4
2
5.5
5.4
5.7
5.2
4.7
4.5
8.2
t
t
Y
ns
pd
C
8.6
D
7.6
OE
OE
Y
Y
25.2
15
11.3
5.8
7
1.7
1
ns
ns
en
t
2.1
5.6
dis
operating characteristics, T = 25°C
A
V
CC
= 1.8 V
V
= 2.5 V
V
CC
= 3.3 V
V
= 5 V
TEST
CONDITIONS
CC
TYP
20
CC
TYP
27
PARAMETER
UNIT
TYP
TYP
22
C
Power dissipation capacitance
f = 10 MHz
19
pF
pd
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢊꢄꢋ ꢌꢍꢎꢆꢏ ꢁꢐ ꢑ ꢈꢊꢌ ꢍꢒꢄ ꢓ ꢔ ꢊꢄꢋ ꢑꢕ ꢄꢓ ꢎꢐꢊ ꢁꢆꢋꢑ ꢏ ꢁ ꢈ ꢍꢋ
ꢉ
ꢉ
ꢓ
ꢀ
ꢖ
ꢑ
ꢋ
ꢗ
ꢘ
ꢎ
ꢀ
ꢋ
ꢍ
ꢋ
ꢓ
ꢏ
ꢊ
ꢋ
ꢕ
ꢊ
ꢋ
SCES609B − SEPTEMBER 2004 – REVISED JANUARY 2005
PARAMETER MEASUREMENT INFORMATION
V
LOAD
Open
S1
R
L
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
PLH PHL
/t
C
L
t
V
R
PLZ PZL
LOAD
GND
L
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
C
R
L
V
LOAD
L
∆
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5 V 0.5 V
V
V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
V
/2
/2
2 × V
2 × V
6 V
2 × V
CC
15 pF
15 pF
15 pF
15 pF
1 MΩ
1 MΩ
1 MΩ
1 MΩ
0.15 V
0.15 V
0.3 V
CC
CC
CC
CC
CC
CC
3 V
1.5 V
/2
V
CC
V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
su
h
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
V
0 V
t
t
t
t
t
PHL
PZL
PLZ
+ V
PLH
PHL
Output
Waveform 1
V
/2
OH
LOAD
V
V
V
M
Output
M
V
V
M
S1 at V
(see Note B)
V
LOAD
OL
∆
V
OL
V
OL
t
PLH
t
t
PZH
PHZ
− V
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
V
M
OH
∆
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉꢉ
ꢊ ꢄꢋ ꢌ ꢍꢎ ꢆꢏꢁ ꢐ ꢑ ꢈꢊ ꢌꢍꢒ ꢄꢓ ꢔꢊ ꢄꢋꢑ ꢕ ꢄ ꢓꢎꢐ ꢊꢁꢆꢋ ꢑ ꢏꢁ ꢈ ꢍꢋ ꢓ
ꢖꢑ ꢋ ꢗ ꢘ ꢎꢀꢋꢍꢋ ꢓ ꢏꢊꢋ ꢕꢊ ꢋꢀ
SCES609B − SEPTEMBER 2004 – REVISED JANUARY 2005
PARAMETER MEASUREMENT INFORMATION
V
LOAD
Open
S1
R
L
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
PLH PHL
/t
C
L
t
V
R
PLZ PZL
LOAD
GND
L
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
C
R
L
V
LOAD
L
∆
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5 V 0.5 V
V
V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
V
/2
/2
2 × V
2 × V
6 V
2 × V
CC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
CC
CC
CC
3 V
1.5 V
/2
V
CC
V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
su
h
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
V
0 V
t
t
t
t
t
PHL
PZL
PLZ
+ V
PLH
PHL
Output
Waveform 1
V
/2
OH
LOAD
V
V
V
M
Output
M
V
V
M
S1 at V
(see Note B)
V
LOAD
OL
∆
V
OL
V
OL
t
PLH
t
t
PZH
PHZ
− V
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
V
M
OH
∆
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2006
PACKAGING INFORMATION
Orderable Device
SN74LVC1G99DCTR
SN74LVC1G99DCTT
SN74LVC1G99DCTTE4
SN74LVC1G99DCUR
SN74LVC1G99DCURE4
SN74LVC1G99DCUT
SN74LVC1G99DCUTE4
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SM8
DCT
8
8
8
8
8
8
8
3000
Pb-Free
(RoHS)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
SM8
SM8
US8
US8
US8
US8
DCT
DCT
DCU
DCU
DCU
DCU
250
Pb-Free
(RoHS)
250
Pb-Free
(RoHS)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC1G99YEPR
SN74LVC1G99YZPR
NRND
WCSP
WCSP
YEP
YZP
8
8
3000
3000
TBD
SNPB
Level-1-260C-UNLIM
Level-1-260C-UNLIM
ACTIVE
Pb-Free
(RoHS)
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,13
0,65
8
5
0,15 NOM
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
0,25
1
4
0° – 8°
0,60
0,20
3,15
2,75
1,30 MAX
Seating Plane
0,10
0,10
0,00
4188781/C 09/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion
D. Falls within JEDEC MO-187 variation DA.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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