SN74LVC1T45_07 [TI]
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS; 可配置电压转换和3态输出的单位双电源总线收发器
| 型号： | SN74LVC1T45_07 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS |
| 文件： | 总22页 (文件大小：466K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES515H–DECEMBER 2003–REVISED JANUARY 2007
FEATURES
•
Available in the Texas Instruments
NanoFree™ Package
•
Max Data Rates
–
–
–
–
420 Mbps (3.3-V to 5-V Translation)
210 Mbps (Translate to 3.3 V)
140 Mbps (Translate to 2.5 V)
75 Mbps (Translate to 1.8 V)
•
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.65-V to
5.5-V Power-Supply Range
•
VCC Isolation Feature – If Either VCC Input Is at
GND, Both Ports Are in the High-Impedance
State
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
•
•
•
•
DIR Input Circuit Referenced to VCCA
Low Power Consumption, 4-µA Max ICC
±24-mA Output Drive at 3.3 V
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
Ioff Supports Partial-Power-Down Mode
Operation
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
C2
C1
3
2
4
5
6
A
GND
B
1
2
3
6
5
4
V
V
V
V
CCB
1
2
3
6
5
4
CCA
CCB
CCA
1
2
3
6
V
V
CCB
B1
B2
A2
CCA
DIR
V
GND
A
DIR
B
GND
A
DIR
B
A1 1
V
CCA
CCB
DIR
B
GND
A
5
4
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is
designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track
VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional
translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(2)
NanoFree™ – WCSP (DSBGA)
Reel of 3000
SN74LVC1T45YZPR
_ _ _TA_
0.23-mm Large Bump – YZP (Pb-free)
SOT (SOT-23) – DBV
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 4000
SN74LVC1T45DBVR
SN74LVC1T45DBVT
SN74LVC1T45DCKR
SN74LVC1T45DCKT
SN74LVC1T45DRLR
CT1_
TA_
–40°C to 85°C
SOT (SC-70) – DCK
SOT (SOT-533) – DRL
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES515H–DECEMBER 2003–REVISED JANUARY 2007
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The SN74LVC1T45 is designed for asynchronous communication between two data buses. The logic levels of
the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits
data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when
the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic
HIGH or LOW level applied to prevent excess ICC and ICCZ
.
The SN74LVC1T45 is designed so that the DIR input is powered by VCCA
.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance
state.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
FUNCTION TABLE(1)
INPUT
OPERATION
DIR
L
B data to A bus
A data to B bus
H
(1) Input circuits of the data I/Os
always are active.
LOGIC DIAGRAM (POSITIVE LOGIC)
5
3
DIR
A
4
B
V
CCA
V
CCB
2
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SN74LVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES515H–DECEMBER 2003–REVISED JANUARY 2007
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCCA
Supply voltage range
VCCB
–0.5
6.5
V
VI
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
–0.5
–0.5
6.5
6.5
V
V
VO
A port
Voltage range applied to any output in the high or low state(2)(3)
B port
–0.5 VCCA + 0.5
VO
V
–0.5 VCCB + 0.5
IIK
IOK
IO
Input clamp current
VI < 0
–50
–50
±50
±100
165
259
142
123
mA
mA
mA
mA
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
DBV package
DCK package
DRL package
YZP package
θJA
Package thermal impedance(4)
°C/W
°C
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
3
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SN74LVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES515H–DECEMBER 2003–REVISED JANUARY 2007
Recommended Operating Conditions(1)(2)(3)
VCCI
VCCO
MIN
1.65
MAX
UNIT
VCCA
VCCB
5.5
5.5
Supply voltage
V
1.65
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
VCCI × 0.65
1.7
High-level
input voltage
VIH
VIL
VIH
VIL
Data inputs(4)
Data inputs(4)
V
2
4.5 V to 5.5 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
VCCI × 0.7
VCCI × 0.35
0.7
Low-level
input voltage
V
V
V
0.8
4.5 V to 5.5 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
VCCI × 0.3
VCCA × 0.65
1.7
2
High-level
input voltage
DIR
(5)
(5)
(referenced to VCCA
)
)
4.5 V to 5.5 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
VCCA × 0.7
VCCA × 0.35
0.7
Low-level
input voltage
DIR
(referenced to VCCA
0.8
4.5 V to 5.5 V
VCCA × 0.3
VI
Input voltage
0
0
5.5
VCCO
–4
–8
–24
–32
4
V
V
VO
Output voltage
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
IOH
High-level output current
Low-level output current
mA
mA
4.5 V to 5.5 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
8
IOL
24
32
20
20
10
5
4.5 V to 5.5 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
Data inputs
Input transition
rise or fall rate
∆t/∆v
ns/V
4.5 V to 5.5 V
1.65 V to 5.5 V
Control inputs
Operating free-air temperature
5
TA
–40
85
°C
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
(3) All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(4) For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V.
(5) For VCCI values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V.
4
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SN74LVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES515H–DECEMBER 2003–REVISED JANUARY 2007
Electrical Characteristics(1)(2)
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
–40°C to 85°C
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VCCA
VCCB
UNIT
MIN
TYP
MAX
MIN
MAX
VCCO
– 0.1
1.65 V to 4.5 V
1.65 V to 4.5 V
IOH = –4 mA
IOH = –8 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 µA
IOL = 4 mA
1.65 V
2.3 V
1.65 V
2.3 V
1.2
1.9
2.4
3.8
VOH
VI = VIH
V
3 V
3 V
4.5 V
4.5 V
1.65 V to 4.5 V
1.65 V
1.65 V to 4.5 V
1.65 V
0.1
0.45
0.3
VOL
IOL = 8 mA
VI = VIL
2.3 V
2.3 V
V
IOL = 24 mA
IOL = 32 mA
VI = VCCA or GND
3 V
3 V
0.55
0.55
±2
4.5 V
4.5 V
II
DIR
1.65 V to 5.5 V
0 V
1.65 V to 5.5 V
0 to 5.5 V
0 V
±1
±1
±1
µA
µA
A port
B port
±2
Ioff
VI or VO = 0 to 5.5 V
VO = VCCO or GND
0 to 5.5 V
±2
A or B
port
IOZ
1.65 V to 5.5 V
1.65 V to 5.5 V
±1
±2
µA
µA
1.65 V to 5.5 V
5.5 V
1.65 V to 5.5 V
0 V
3
2
ICCA
VI = VCCI or GND, IO = 0
0 V
5.5 V
-2
3
1.65 V to 5.5 V
5.5 V
1.65 V to 5.5 V
0 V
ICCB
VI = VCCI or GND, IO = 0
VI = VCCI or GND, IO = 0
-2
2
µA
µA
0 V
5.5 V
ICCA + ICCB
(see Table 1)
1.65 V to 5.5 V
3 V to 5.5 V
1.65 V to 5.5 V
3 V to 5.5 V
4
A port at VCCA – 0.6 V,
DIR at VCCA, B port = open
A port
50
∆ICCA
µA
DIR at VCCA – 0.6 V,
B port = open,
A port at VCCA or GND
DIR
50
50
B port at VCCB – 0.6 V,
DIR at GND,
∆ICCB B port
3 V to 5.5 V
3 V to 5.5 V
µA
A port = open
Ci
DIR
VI = VCCA or GND
3.3 V
3.3 V
3.3 V
3.3 V
2.5
6
pF
pF
A or B
port
Cio
VO = VCCA/B or GND
(1) VCCO is the VCC associated with the output port.
(2) VCCI is the VCC associated with the input port.
5
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SN74LVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES515H–DECEMBER 2003–REVISED JANUARY 2007
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (see Figure 1)
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
± 0.2 V
± 0.3 V
PARAMETER
UNIT
MIN
3
MAX
MIN
2.2
2.2
2.3
2.1
4.8
2.1
4.9
3.7
MAX
MIN
1.7
1.8
2.1
2
MAX
MIN
1.4
1.7
1.9
1.8
5.1
3.1
2.8
2.4
MAX
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
17.7
14.3
17.7
14.3
19.4
10.5
21.9
16
10.3
8.5
8.3
7.1
7.2
7
A
B
A
A
B
A
B
ns
ns
ns
ns
ns
ns
2.8
3
16
15.5
12.6
18.4
10.7
10.3
8.4
15.1
12.2
17.1
10.9
8.2
B
2.8
5.2
2.3
7.4
4.2
12.9
18.5
10.5
11.5
9.2
4.7
2.4
4.6
3.3
DIR
DIR
DIR
DIR
6.4
(1)
tPZH
33.7
36.2
28.2
33.7
25.2
24.4
20.8
27
23.9
22.9
19
21.5
20.4
18.1
24.1
(1)
tPZL
(1)
tPZH
(1)
tPZL
25.5
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (see Figure 1)
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
± 0.2 V
PARAMETER
UNIT
MIN
2.3
2.1
2.2
2.2
3
MAX
MIN
1.5
1.4
1.5
1.4
3.1
1.3
4.1
3.2
MAX
MIN
MAX
6.4
MIN
1.1
0.9
1
MAX
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
16
12.9
10.3
8.5
8.5
7.5
1.3
1.3
1.4
1.3
2.8
1.3
3.9
2.8
5.1
4.6
A
B
A
A
B
A
B
ns
ns
ns
ns
ns
ns
5.4
8.5
8
7.5
B
7.5
7
0.9
3.2
1
6.2
8.1
8.1
8.1
8.1
DIR
DIR
DIR
DIR
1.3
6.5
3.9
5.9
5.9
5.9
5.8
23.7
18.9
29.2
32.2
21.9
21
11.4
9.6
10.2
8.4
2.4
1.8
7.1
5.3
(1)
tPZH
18.1
18.9
14.4
15.6
16.4
17.2
12.3
13.5
12.8
13.3
10.9
12.7
(1)
tPZL
(1)
tPZH
(1)
tPZL
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
6
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SN74LVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES515H–DECEMBER 2003–REVISED JANUARY 2007
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (see Figure 1)
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
± 0.2 V
± 0.3 V
PARAMETER
UNIT
MIN
2.1
2
MAX
MIN
1.4
1.3
1.3
1.3
3
MAX
MIN
0.7
0.8
0.7
0.8
2.8
2.2
2.9
2.4
MAX
MIN
0.7
0.7
0.6
0.7
3.4
2.2
2.4
1.7
MAX
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
15.5
12.6
8.3
8
7
5.8
5
4.4
4
A
B
A
A
B
A
B
ns
ns
ns
ns
ns
ns
1.7
1.8
2.9
1.8
5.4
3.3
6.4
5.8
5
5.4
B
7.1
5.4
4.5
7.3
7.3
7.3
5.7
8.8
7.1
12.9
13.8
11.5
12.3
7.3
DIR
DIR
DIR
DIR
5.6
1.6
3.9
2.9
5.6
5.7
20.5
14.5
22.8
27.6
21.1
19.9
10.1
7.8
6.8
4.9
(1)
tPZH
14.2
15.5
13.6
14.3
10.3
11.3
10.1
11.3
(1)
tPZL
(1)
tPZH
(1)
tPZL
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 5 V ±0.5 V (see Figure 1)
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
± 0.2 V
PARAMETER
UNIT
MIN
1.9
1.8
1.4
1.7
2.1
0.9
4.8
4.2
MAX
MIN
1
MAX
MIN
MAX
5.4
4.5
4.4
4
MIN
0.5
0.5
0.5
0.5
2.2
0.9
2.5
1.6
MAX
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
15.1
12.2
7.2
7.5
6.2
0.6
0.7
0.7
0.7
2.2
1
3.9
3.5
3.9
3.5
5.4
3.7
6.5
4.5
8.4
10
A
B
A
A
B
A
B
ns
ns
ns
ns
ns
ns
0.9
1
5.1
B
7
0.9
2.2
1
4.6
5.4
5.4
5.5
3.7
8.5
7
DIR
DIR
DIR
DIR
3.8
3.8
20.2
14.8
22
2.5
2.5
9.8
1
7.4
2.5
(1)
tPZH
12.5
14.4
11.3
11.6
11.4
12.5
9.1
10
(1)
tPZL
27.2
18.9
17.6
(1)
tPZH
7.6
8.6
(1)
tPZL
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
Operating Characteristics
TA = 25°C
VCCA
VCCB = 1.8 V
=
VCCA
VCCB = 2.5 V
=
VCCA
VCCB = 3.3 V
=
VCCA =
VCCB = 5 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
TYP
TYP
TYP
A-port input, B-port output
B-port input, A-port output
A-port input, B-port output
B-port input, A-port output
CL = 0 pF,
f = 10 MHz,
tr = tf = 1 ns
3
4
4
4
(1)
(1)
CpdA
pF
pF
18
18
3
19
19
4
20
20
4
21
21
4
CL = 0 pF,
f = 10 MHz,
tr = tf = 1 ns
CpdB
(1) Power dissipation capacitance per transceiver
7
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SN74LVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES515H–DECEMBER 2003–REVISED JANUARY 2007
Power-Up Considerations
A proper power-up sequence always should be followed to avoid excessive supply current, bus contention,
oscillations, or other anomalies. To guard against such power-up problems, take the following precautions:
1. Connect ground before any supply voltage is applied.
2. Power up VCCA
.
3. VCCB can be ramped up along with or after VCCA
.
Table 1. Typical Total Static Power Consumption (ICCA + ICCB
)
VCCA
VCCB
UNIT
0 V
0
1.8 V
<1
<2
<2
<2
2
2.5 V
<1
3.3 V
<1
5 V
<1
2
0 V
1.8 V
2.5 V
3.3 V
5 V
<1
<1
<1
<1
<2
<2
<2
<2
<2
<2
<2
µA
<2
<2
<2
<2
8
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SN74LVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES515H–DECEMBER 2003–REVISED JANUARY 2007
TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 1.8 V
10
10
9
9
8
7
6
5
4
3
2
V
CCB
= 1.8 V
8
7
6
5
4
3
2
1
0
V
= 1.8 V
= 2.5 V
CCB
V
V
= 2.5 V
= 3.3 V
CCB
V
V
CCB
CCB
V
CCB
= 5 V
= 3.3 V
= 5 V
CCB
V
CCB
1
0
20
0
5
10
15
C − pF
25
30
35
10
15
20
25
30
35
0
5
C − pF
L
L
TYPICAL PROPAGATION DELAY (B to A) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 1.8 V
10
9
10
9
V
V
= 1.8 V
= 2.5 V
CCB
8
7
6
8
7
6
5
4
3
2
1
0
CCB
V
= 1.8 V
CCB
V
V
= 3.3 V
= 5 V
CCB
CCB
5
4
3
2
1
0
V
CCB
V
CCB
V
CCB
= 2.5 V
= 3.3 V
= 5 V
0
5
10
15
20
C − pF
25
30
35
35
10
15
20
25
30
0
5
C − pF
L
L
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SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
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SCES515H–DECEMBER 2003–REVISED JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 2.5 V
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
V
= 1.8 V
CCB
V
= 1.8 V
= 2.5 V
CCB
V
CCB
= 2.5 V
V
CCB
V
V
= 3.3 V
= 5 V
CCB
CCB
V
V
= 3.3 V
= 5 V
CCB
CCB
10
15
20
25
30
35
0
5
10
15
C − pF
20
25
30
35
0
5
C − pF
L
L
TYPICAL PROPAGATION DELAY (B to A) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 2.5 V
10
9
10
9
8
7
6
5
4
3
2
1
0
8
7
6
V
CCB
= 1.8 V
V
= 1.8 V
= 2.5 V
CCB
5
4
3
2
1
0
V
V
= 2.5 V
= 3.3 V
CCB
CCB
V
CCB
V
CCB
= 5 V
V
V
= 3.3 V
= 5 V
CCB
CCB
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
C − pF
L
C − pF
L
10
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SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES515H–DECEMBER 2003–REVISED JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 3.3 V
10
9
10
9
8
7
6
5
4
3
2
1
0
8
7
6
V
CCB
= 1.8 V
V
V
= 1.8 V
= 2.5 V
CCB
5
4
3
2
1
0
V
V
= 2.5 V
= 3.3 V
CCB
CCB
CCB
V
CCB
= 5 V
V
V
= 3.3 V
= 5 V
CCB
CCB
15
C − pF
25
10
20
30
35
0
5
10
15
C − pF
25
0
5
20
30
35
L
L
TYPICAL PROPAGATION DELAY (B to A) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 3.3 V
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
V
= 1.8 V
= 2.5 V
CCB
V
= 1.8 V
CCB
V
CCB
V
CCB
= 2.5 V
V
V
= 3.3 V
= 5 V
CCB
V
V
= 3.3 V
= 5 V
CCB
CCB
CCB
35
10
15
20
25
30
35
0
5
10
15
20
25
30
0
5
C − pF
L
C − pF
L
11
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SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES515H–DECEMBER 2003–REVISED JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 5 V
10
9
8
7
6
5
4
3
2
1
0
10
9
8
V
= 1.8 V
CCB
7
V
= 1.8 V
= 2.5 V
CCB
6
5
4
3
2
V
V
= 2.5 V
= 3.3 V
CCB
V
CCB
CCB
V
= 5 V
10
CCB
V
V
= 3.3 V
= 5 V
CCB
1
0
CCB
35
20
15
C − pF
25
30
0
5
0
5
10
15
20
25
30
35
C − pF
L
L
TYPICAL PROPAGATION DELAY (B to A) vs LOAD CAPACITANCE
TA = 25°C, VCCA = 5 V
10
9
10
9
8
7
6
5
4
3
2
1
0
8
7
6
5
V
V
= 1.8 V
= 2.5 V
CCB
V
= 1.8 V
= 2.5 V
CCB
4
3
2
CCB
V
CCB
V
V
= 3.3 V
= 5 V
CCB
V
V
= 3.3 V
= 5 V
CCB
CCB
1
0
CCB
5
0
10
15
20
25
30
35
25
30
35
10
15
20
0
5
C − pF
L
C − pF
L
12
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SN74LVC1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES515H–DECEMBER 2003–REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
2 × V
CCO
TEST
S1
S1
R
L
Open
GND
t
Open
pd
From Output
Under Test
t
t
/t
/t
2 × V
CCO
GND
PLZ PZL
PHZ PZH
C
L
R
L
(see Note A)
t
w
LOAD CIRCUIT
V
CCI
V
CCI
/2
V
CCI
/2
Input
C
L
V
TP
R
L
V
CCO
0 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
2 kΩ
2 kΩ
2 kΩ
2 kΩ
0.15 V
0.15 V
0.3 V
15 pF
15 pF
15 pF
15 pF
VOLTAGE WAVEFORMS
PULSE DURATION
0.3 V
V
CCA
Output
Control
(low-level
enabling)
V /2
CCA
V
CCA
/2
t
0 V
t
PZL
PLZ
V
V
CCO
Output
Waveform 1
V
CCI
V
/2
/2
CCO
Input
V
CCI
/2
V
CCI
/2
V
+ V
OL
TP
S1 at 2 × V
CCO
OL
0 V
(see Note B)
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
OH
− V
TP
V
CCO
Output
V /2
CCO
V
CCO
/2
(see Note B)
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR v10 MHz, Z = 50 Ω, dv/dt ≥ 1 V/ns.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
H.
I.
t
t
t
V
V
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
pd
PHL
is the V associated with the input port.
CC
CCI
is the V associated with the output port.
CCO
CC
J. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES515H–DECEMBER 2003–REVISED JANUARY 2007
APPLICATION INFORMATION
Figure 2 shows an example of the SN74LVC1T45 being used in a unidirectional logic level-shifting application.
V
CC1
V
CC1
V
CC2
V
CC2
1
2
3
6
5
4
SYSTEM-1
SYSTEM-2
PIN
1
NAME
VCCA
GND
A
FUNCTION
VCC1
GND
OUT
DESCRIPTION
SYSTEM-1 supply voltage (1.65 V to 5.5 V)
Device GND
2
3
Output level depends on VCC1 voltage.
Input threshold value depends on VCC2 voltage.
GND (low level) determines B-port to A-port direction.
SYSTEM-2 supply voltage (1.65 V to 5.5 V)
4
B
IN
5
DIR
VCCB
DIR
6
VCC2
Figure 2. Unidirectional Logic Level-Shifting Application
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SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES515H–DECEMBER 2003–REVISED JANUARY 2007
APPLICATION INFORMATION
Figure 3 shows the SN74LVC1T45 being used in a bidirectional logic level-shifting application. Since the
SN74LVC1T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
V
CC1
V
CC1
V
CC2
V
CC2
Pullup/Down
or Bus Hold
Pullup/Down
or Bus Hold
I/O-1
I/O-2
(1)
(1)
1
2
3
6
5
4
DIR CTRL
SYSTEM-1
SYSTEM-2
The following table shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to
SYSTEM-1.
STATE DIR CTRL
I/O-1
I/O-2
DESCRIPTION
1
H
Out
In
SYSTEM-1 data to SYSTEM-2
SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The
bus-line state depends on pullup or pulldown.(1)
2
H
Hi-Z
Hi-Z
DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or
pulldown.(1)
3
4
L
L
Hi-Z
Out
Hi-Z
In
SYSTEM-2 data to SYSTEM-1
(1) SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown.
Figure 3. Bidirectional Logic Level-Shifting Application
Enable Times
Calculate the enable times for the SN74LVC1T45 using the following formulas:
•
•
•
•
tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74LVC1T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B
port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2007
PACKAGING INFORMATION
Orderable Device
SN74LVC1T45DBVR
SN74LVC1T45DBVRE4
SN74LVC1T45DBVT
SN74LVC1T45DBVTE4
SN74LVC1T45DCKR
SN74LVC1T45DCKRE4
SN74LVC1T45DCKRG4
SN74LVC1T45DCKT
SN74LVC1T45DCKTE4
SN74LVC1T45DCKTG4
SN74LVC1T45DRLR
SN74LVC1T45DRLRG4
SN74LVC1T45YZPR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
6
6
6
6
6
6
6
6
6
6
6
6
6
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT-23
SOT-23
SOT-23
SC70
DBV
DBV
DBV
DCK
DCK
DCK
DCK
DCK
DCK
DRL
DRL
YZP
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT-533
SOT-533
WCSP
4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2007
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to
discontinue any product or service without notice. Customers should obtain the latest relevant information
before placing orders and should verify that such information is current and complete. All products are sold
subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent
TI deems necessary to support this warranty. Except where mandated by government requirements, testing
of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible
for their products and applications using TI components. To minimize the risks associated with customer
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent
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solutions:
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