SN74LVC2G08-Q1_V01 [TI]
SN74LVC2G08-Q1 Dual 2-Input Positive-AND Gate;
| 型号： | SN74LVC2G08-Q1_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SN74LVC2G08-Q1 Dual 2-Input Positive-AND Gate 栅 |
| 文件： | 总20页 (文件大小：848K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC2G08-Q1
SCES557E – MARCH 2004 – REVISED OCTOBER 2020
SN74LVC2G08-Q1 Dual 2-Input Positive-AND Gate
1 Features
3 Description
•
AEC-Q100 Qualified With the Following Results:
This dual 2-input positive-AND gate is designed for
1.65-V to 5.5-V VCC operation.
– Device Temperature Grade 1: –40°C to +125°C
Ambient Operating Temperature Range (DCU
package)
– Device Temperature Grade 3: –40°C to +85°C
Ambient Operating Temperature Range (DCT
package)
The SN74LVC2G08-Q1 performs the Boolean
Y + A • B or Y + A ) B
function
in positive logic.
This device is fully specified for partial-power-down
applications using I off. The I off circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
•
•
•
•
•
•
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Device Information (1)
Low Power Consumption, 10-μA Max ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Partial-Power-Down Mode Operation
Can be Used as a Down Translator to Translate
Input from a Maximum of 5.5 V Down to the VCC
Level.
PART NUMBER
PACKAGE
BODY SIZE (NOM)
2.95 mm × 2.80 mm
2.30 mm × 2.00 mm
SN74LVC2G08DCT-Q1 SM8 (8)
SN74LVC2G08DCU-Q1 VSSOP (8)
1
•
Latch-Up Performance Exceeds 100 mA Per JESD
78, Class II
1A
7
2
1Y
1B
2 Applications
5
2A
•
•
•
Combine Power Good signals for Muliple Power
Rails
Prevent a Signal from Being Passed Until a
Condition is True
3
6
2Y
2B
Figure 3-1. Logic Diagram (Positive Logic)
Combine Active-Low Error Signals
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC2G08-Q1
SCES557E – MARCH 2004 – REVISED OCTOBER 2020
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics............................................6
6.7 Operating Characteristics........................................... 6
7 Typical Characteristics................................................... 7
8 Parameter Measurement Information............................8
9 Detailed Description........................................................9
9.1 Overview.....................................................................9
9.2 Functional Block Diagram...........................................9
9.3 Feature Description.....................................................9
9.4 Device Functional Modes..........................................10
10 Application and Implementation................................ 11
10.1 Application Information............................................11
10.2 Typical Application.................................................. 11
11 Application Curves......................................................12
12 Power Supply Recommendations..............................12
13 Layout...........................................................................12
13.1 Layout Guidelines................................................... 12
13.2 Layout Example...................................................... 12
14 Device and Documentation Support..........................13
14.1 Receiving Notification of Documentation Updates..13
14.2 Support Resources................................................. 13
14.3 Trademarks.............................................................13
14.4 Glossary..................................................................13
14.5 Electrostatic Discharge Caution..............................13
15 Mechanical, Packaging, and Orderable
Information.................................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2010) to Revision E (October 2020)
Page
•
•
•
•
•
•
•
•
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Removed Typical VOLP (Output Ground Bound) <0.8 V at VCC = 3.3 V, TA = 25°C from Features section........1
Removed Typical VOHV (Output VOHV Undershoot) >2 V at VCC = 3.3 V, TA = 25°C from Features section......1
Removed the Ordering Information table from Description section....................................................................1
Added a Device Information table to the Description section............................................................................. 1
Added the Logic Diagram (Positive Logic) figure to the Description section...................................................... 1
Added the Pin Configuration and Functions section...........................................................................................3
Added SN74LVC2G08DCT-Q1 and SN74LVC2G08DCU-Q1 minimum and maximum operating free-air
temperature ranges to the Recommended Operating Conditions section..........................................................5
Added the TA temperature ranges (–40°C to 85°C and –40°C to 125°C) for the tpd parameter to the Switching
Characteristics section .......................................................................................................................................6
Added the Typical Characteristics section.......................................................................................................... 7
Added the Overview section...............................................................................................................................9
Added the Functional Block Diagram section.....................................................................................................9
Added the Features Description section.............................................................................................................9
Added the Device Funcational Modes section..................................................................................................10
Added the Application and Implementation section..........................................................................................11
Added the Application Information section........................................................................................................11
Added the Power Supply Recommendations section.......................................................................................12
Added the Layout section................................................................................................................................. 12
Added the Layout Guidelines section............................................................................................................... 12
Added the Layout Example section.................................................................................................................. 12
Updated the Device and Documentation Support section................................................................................13
•
•
•
•
•
•
•
•
•
•
•
•
•
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5 Pin Configuration and Functions
VCC
1Y
2B
2A
1
2
3
4
8
7
6
5
1A
1B
VCC
1Y
2B
2A
1
2
3
4
8
7
6
5
1A
1B
2Y
GND
2Y
Figure 5-2. DCU Package
8-Pin VSSOP
GND
Top View
Figure 5-1. DCT Package
8-Pin SM8
Top View
Pin Functions
PIN
I/O
DESCRIPTION
NAME
1A
NO.
1
I
I
Channel 1 logic input
1B
2
Channel 1 logic input
Logic level output
Channel 2 logic input
Channel 2 logic input
Logic level output
Ground
1Y
7
O
I
2A
5
2B
6
I
2Y
3
O
—
—
GND
VCC
4
8
Power Supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
MAX
6.5
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(1)
6.5
V
VO
VO
IIK
Voltage range applied to any output in the high-impedance or power-off state(1)
Voltage range applied to any output in the high or low state(1) (2)
Input clamp current
6.5
V
VCC + 0.5
–50
V
mA
mA
mA
mA
°C
°C
IOK
IO
Output clamp current
–50
Continuous output current
±50
Continuous current through VCC or GND
Junction temperature
±100
150
TJ
Tstg
Storage temperature range
–65
150
(1) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(2) The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
±2000
±1000
Electrostatic
discharge
V(ESD)
V
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
MIN
1.65
MAX
UNIT
Operating
5.5
VCC
Supply voltage
V
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
1.5
0.65 × VCC
1.7
VIH
High-level input voltage
V
V
2
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.7 × VCC
0.35 × VCC
0.7
VIL
Low-level input voltage
0.8
VCC = 4.5 V to 5.5 V
0.3 × VCC
5.5
VCC
–4
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
–8
IOH
High-level output current
Low-level output current
–16
–24
–32
4
mA
mA
VCC = 3 V
VCC = 4.5 V
VCC = 1.65 V
VCC = 2.3 V
8
IOL
16
VCC = 3 V
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
20
Δt/Δv Input transition rise or fall rate
10
ns/V
°C
VCC = 5 V ± 0.5 V
5
SN74LVC2G08DCU-Q1
SN74LVC2G08DCT-Q1
–40
–40
125
85
TA
Operating free-air temperature
6.4 Thermal Information
SN74LVC2G08-Q1
THERMAL METRIC(1)
DCT (SM8)
DCU (VSSOP)
8 PINS
201.5
UNIT
8 PINS
220
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
117.2
100
91.9
122.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
42.4
98.9
31.8
ΨJB
122.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 5.5 V
1.65 V
MIN
VCC – 0.1
1.2
TYP(1)
MAX
UNIT
IOH = –100 µA
IOH = –4 mA
IOH = –8 mA
IOH = –16 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 µA
IOL = 4 mA
2.3 V
1.9
VOH
V
2.4
3 V
2.3
4.5 V
1.65 V to 5.5 V
1.65 V
3.8
0.1
0.45
0.3
IOL = 8 mA
2.3 V
VOL
V
IOL = 16 mA
IOL = 24 mA
IOL = 32 mA
VI = 5.5 V or GND
VI or VO = 5.5 V
0.4
3 V
0.55
0.55
±5
4.5 V
0 to 5.5 V
0
II
A or B inputs
µA
µA
µA
Ioff
ICC
±10
10
VI = 5.5 V or GND, IO = 0
1.65 V to 5.5 V
One input at VCC – 0.6 V,
Other inputs at VCC or GND,
TA = –40°C to 85°C
ΔICC
Ci
3 V to 5.5 V
3.3 V
500
µA
pF
VI = VCC or GND, TA = –40°C to 85°C
5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Switching Characteristics
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TA
VCC
MIN
MAX
UNIT
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
2.6
1
9
5.1
4.7
3.8
9.8
5.8
5.3
4.8
–40°C to 85°C
1
1
tpd
A or B
Y
ns
2.6
1
–40°C to 125°C
1
1
6.7 Operating Characteristics
TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
VCC = 5 V
TYP
PARAMETER
TEST CONDITIONS
f = 10 MHz
UNIT
TYP
TYP
TYP
Cpd
Power dissipation capacitance
17
17
17
20
pF
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7 Typical Characteristics
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
TPD
TPD
150
0
1
2
3
4
5
6
-100
-50
0 50
Temperature - °C
100
Vcc - V
D002
D001
Figure 7-2. tPD Across VCC at 25°C
Figure 7-1. tPD Across Temperature at 3.3-V VCC
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8 Parameter Measurement Information
VLOAD
Open
GND
S1
RL
From Output
Under Test
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
VLOAD
GND
CL
(see Note A)
RL
LOAD CIRCUIT
INPUTS
VCC
VM
VLOAD
CL
RL
VD
VI
tr/tf
VCC
VCC
3 V
VCC
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5 V 0.5 V
£2 ns
£2 ns
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6 V
30 pF
30 pF
50 pF
50 pF
1 kW
0.15 V
0.15 V
0.3 V
500 W
500 W
500 W
£2.5 ns
£2.5 ns
2 × VCC
0.3 V
VI
Timing Input
Data Input
VM
0 V
tW
tsu
th
VI
VI
Input
VM
VM
VM
VM
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VI
Output
Control
VM
VM
Input
VM
VM
0 V
0 V
tPZL
tPLZ
tPLH
tPHL
VM
Output
Waveform 1
S1 at VLOAD
VOH
VOL
VLOAD/2
VOL
VM
VM
Output
Output
VOL + VD
(see Note B)
tPHL
tPLH
tPZH
tPHZ
VOH
VOL
Output
Waveform 2
S1 at GND
VOH
VOH – VD
VM
VM
VM
»0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
}
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D.iiThe outputs are measured one at a time, with one transition per measurement.
Figure 8-1. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
The SN74LVC2G08-Q1 device contains two 2-input positive AND gates and performs the Boolean function
Y + A • B or Y + A ) B
. This device is fully specified for partial-power-down applications using Ioff. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down.
9.2 Functional Block Diagram
1
1A
7
2
1Y
2Y
1B
5
6
2A
2B
3
9.3 Feature Description
9.3.1 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term "balanced" indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
9.3.2 Standard CMOS Inputs
This device includes standard CMOS inputs. Standard CMOS inputs are high impedance and are typically
modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case
resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the
maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I).
Standard CMOS inputs require that input signals transition between valid logic states quickly, as defined by the
input transition time or rate in the Recommended Operating Conditions table. Failing to meet this specification
will result in excessive power consumption and could cause oscillations. More details can be found in
Implications of Slow or Floating CMOS Inputs.
Do not leave standard CMOS inputs floating at any time during operation. Unused inputs must be terminated at
VCC or GND. If a system will not be actively driving an input at all times, a pull-up or pull-down resistor can be
added to provide a valid input voltage during these times. The resistor value will depend on multiple factors,
however a 10-kΩ resistor is recommended and will typically meet all requirements.
9.3.3 Clamp Diode Structure
The inputs and outputs to this device have negative clamping diodes only as depicted in Figure 9-1.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.
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VCC
Logic
GND
Device
Input
Output
-IIK
-IOK
Figure 9-1. Electrical Placement of Clamping Diodes for Each Input and Output
9.3.4 Partial Power Down (Ioff)
This device includes circuitry to disable all outputs when the supply pin is held at 0 V. When disabled, the
outputs will neither source nor sink current, regardless of the input voltages applied. The amount of leakage
current at each output is defined by the Ioff specification in the Electrical Characteristics table.
9.4 Device Functional Modes
Table 9-1 lists the functional modes of the SN74LVC2G08-Q1.
Table 9-1. Function Table
INPUTS
OUTPUT
A
H
L
B
H
X
L
Y
H
L
X
L
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
The SN74LVC2G08-Q1 is a high-drive CMOS device that can be used for implementing AND logic with a high
output drive, such as an LED application. It can produce 24 mA of drive current at 3.3 V, making it Ideal for
driving multiple outputs and good for high-speed applications up to 100 MHz. The inputs are 5.5-V tolerant
allowing it to translate down to VCC
.
10.2 Typical Application
Figure 10-1. Typical Application
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads
so routing and load conditions must be considered to prevent ringing.
10.2.1.1 Detailed Design Procedure
1. Recommended Input Conditions
•
•
•
Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
Inputs are overvoltage tolerant allowing them to go as high as (VI maximum) in the Recommended
Operating Conditions table at any valid VCC
.
2. Recommended Output Conditions
•
•
Load currents must not exceed (IO maximum) per output and must not exceed total current (continuous
current through VCC or GND) for the part. These limits are located in the Recommended Operating
Conditions table.
Outputs must not be pulled above VCC in normal operating conditions.
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11 Application Curves
10
8
Icc 1.8V
Icc 2.5V
Icc 3.3V
Icc 5V
6
4
2
0
-2
-20
0
20 40
Frequency - MHz
60
80
D003
Figure 11-1. ICC vs Frequency
12 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table. Each VCC pin must have a good bypass capacitor to prevent power
disturbance. For devices with a single supply, a 0.1-μF capacitor is recommended and if there are multiple VCC
pins then 0.01-μF or 0.022-μF capacitor is recommended for each power pin. It is ok to parallel multiple bypass
capacitors to reject different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel.
The bypass capacitor must be installed as close to the power pin as possible for best results
13 Layout
13.1 Layout Guidelines
When using multiple bit logic devices inputs must not ever float. In many cases, functions or parts of functions of
digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3
of the 4 buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at
the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that must be applied to any particular unused input depends
on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more
convenient.
13.2 Layout Example
V
Input
CC
Unused Input
Output
Unused Input
Output
Input
Figure 13-1. Layout Example
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14 Device and Documentation Support
14.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
14.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
14.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
14.4 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: SN74LVC2G08-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Oct-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PCLVC2G08QDCURQ1
SN74LVC2G08IDCTRQ1
ACTIVE
ACTIVE
VSSOP
SM8
DCU
DCT
8
8
3000
3000
TBD
Call TI
Call TI
-40 to 125
-40 to 85
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
Level-1-260C-UNLIM
C08
Z
SN74LVC2G08QDCURQ1
PREVIEW
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
-40 to 125
1HLRQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Oct-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC2G08-Q1 :
Catalog: SN74LVC2G08
•
Enhanced Product: SN74LVC2G08-EP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 2
PACKAGE OUTLINE
DCT0008A
SSOP - 1.3 mm max height
S
C
A
L
E
3
.
5
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
4.25
3.75
TYP
PIN 1 ID
AREA
A
6X 0.65
8
1
2X
3.15
2.75
1.95
NOTE 3
4
5
0.30
0.15
8X
2.9
2.7
NOTE 4
1.3
1.0
0.13
C A B
B
(0.15) TYP
0.25
SEE DETAIL A
GAGE PLANE
0.1
0.0
0.6
0.2
0 - 8
DETAIL A
TYPICAL
4220784/B 07/2020
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-187.
www.ti.com
EXAMPLE BOARD LAYOUT
DCT0008A
SSOP - 1.3 mm max height
SMALL OUTLINE PACKAGE
8X (1.1)
SYMM
(R0.05)
TYP
1
8
8X (0.4)
SYMM
6X (0.65)
5
4
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220784/B 07/2020
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCT0008A
SSOP - 1.3 mm max height
SMALL OUTLINE PACKAGE
8X (1.1)
SYMM
1
8
8X (0.4)
SYMM
6X (0.65)
5
4
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4220784/B 07/2020
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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