SN74LVC2G126YEAR [TI]
DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS; 具有三态输出的双总线缓冲器门
| 型号： | SN74LVC2G126YEAR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS |
| 文件： | 总13页 (文件大小：333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢓ ꢔꢒ ꢕ ꢖ ꢗꢀꢒꢍꢒ ꢐ ꢘ ꢌꢒ ꢙꢌ ꢒꢀ
SCES205H − APRIL 1999 − REVISED SEPTEMBER 2003
DCT OR DCU PACKAGE
(TOP VIEW)
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
D
D
D
D
D
D
Supports 5-V V
Operation
CC
1OE
1A
2Y
V
CC
2OE
1Y
2A
1
2
3
4
8
7
6
5
Inputs Accept Voltages to 5.5 V
Max t of 4 ns at 3.3 V
pd
Low Power Consumption, 10-µA Max I
GND
CC
24-mA Output Drive at 3.3 V
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
Typical V
<0.8 V at V
(Output Ground Bounce)
= 3.3 V, T = 25°C
OLP
CC
A
D
D
D
D
Typical V
(Output V
Undershoot)
4 5
3 6
2 7
1 8
GND
2Y
1A
2A
1Y
2OE
OHV
OH
>2 V at V
= 3.3 V, T = 25°C
CC
A
I
Supports Partial-Power-Down Mode
off
1OE
V
Operation
CC
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This dual bus buffer gate is designed for 1.65-V to 5.5-V V
operation.
CC
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
‡
NanoStar − WCSP (DSBGA)
0.17-mm Small Bump − YEA
SN74LVC2G126YEAR
SN74LVC2G126YZAR
SN74LVC2G126YEPR
SN74LVC2G126YZPR
NanoFree − WCSP (DSBGA)
0.17-mm Small Bump − YZA (Pb-free)
Reel of 3000
_ _ _CN_
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
−40°C to 85°C
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
SSOP − DCT
Reel of 3000
Reel of 3000
SN74LVC2G126DCTR
SN74LVC2G126DCUR
C26_ _ _
C26_
VSSOP − DCU
Reel of 250
SN74LVC2G126DCUT
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA,YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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Copyright 2003, Texas Instruments Incorporated
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1
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ꢓꢔ ꢒ ꢕ ꢖ ꢗꢀꢒꢍꢒ ꢐ ꢘꢌꢒ ꢙ ꢌꢒꢀ
SCES205H − APRIL 1999 − REVISED SEPTEMBER 2003
description/ordering information (continued)
The SN74LVC2G126 is a dual bus driver/line driver with 3-state outputs. The outputs are disabled when the
associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
Y
OE
A
H
L
H
H
L
H
L
X
Z
logic diagram (positive logic)
1
2
1OE
1A
6
3
1Y
2Y
7
5
2OE
2A
2
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SCES205H − APRIL 1999 − REVISED SEPTEMBER 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
IK
I
Output clamp current, I
OK
O
O
Continuous current through V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 3): DCT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C/W
JA
DCU package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 140°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 102°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51-7.
3
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SCES205H − APRIL 1999 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 4)
MIN
1.65
MAX
UNIT
Operating
5.5
V
Supply voltage
V
CC
IH
Data retention only
1.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
0.65 × V
1.7
CC
V
High-level input voltage
V
V
2
= 4.5 V to 5.5 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
0.7 × V
CC
0.35 × V
0.7
CC
V
IL
Low-level input voltage
0.8
= 4.5 V to 5.5 V
0.3 × V
5.5
CC
V
V
Input voltage
0
0
0
V
V
I
High or low state
3-state
V
CC
5.5
Output voltage
O
V
V
= 1.65 V
= 2.3 V
−4
−8
CC
CC
−16
−24
−32
4
I
High-level output current
Low-level output current
mA
mA
OH
OL
V
= 3 V
CC
V
CC
V
CC
V
CC
= 4.5 V
= 1.65 V
= 2.3 V
8
16
24
32
20
10
5
I
V
CC
= 3 V
V
CC
V
CC
V
CC
V
CC
= 4.5 V
= 1.8 V 0.15 V, 2.5 V 0.2 V
= 3.3 V 0.3 V
= 5 V 0.5 V
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
−40
85
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SCES205H − APRIL 1999 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
V
MIN
V −0.1
CC
MAX
UNIT
CC
I
I
I
I
= −100 mA
= −4 mA
= −8 mA
= −16 mA
1.65 V to 5.5 V
1.65 V
OH
OH
OH
OH
1.2
1.9
2.4
2.3
2.3 V
V
OH
V
3 V
I
= −24 mA
OH
4.5 V
1.65 V to 5.5 V
1.65 V
3.8
I
I
I
I
I
= −32 mA
= 100 mA
= 4 mA
OH
OL
OL
OL
OL
0.1
0.45
0.3
= 8 mA
2.3 V
V
OL
V
= 16 mA
0.4
3 V
0.55
I
= 24 mA
= 32 mA
OL
OL
4.5 V
0.55
5
I
A or OE
inputs
I
I
V = 5.5 V or GND
0 to 5.5 V
mA
I
I
I
I
V or V = 5.5 V
0
3.6 V
10
10
mA
mA
mA
mA
off
I
O
V
O
= 0 to 5.5 V
OZ
CC
V = 5.5 V or GND,
I
I
= 0
1.65 V to 5.5 V
3 V to 5.5 V
10
O
∆I
One input at V
CC
− 0.6 V,
Other inputs at V
CC
or GND
500
CC
Data inputs
3.5
4
C
V = V
CC
or GND
3.3 V
3.3 V
pF
pF
Control
inputs
i
I
C
V
= V
or GND
= 3.3 V, T = 25°C.
6.5
o
O CC
†
All typical values are at V
CC
A
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
V
= 5 V
CC
0.15 V
CC
0.2 V
CC
0.3 V
CC
0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
9.8
MIN
MAX
4.9
5
MIN
MAX
4
MIN
1
MAX
t
A
3.5
3.5
1.7
1.7
1.7
1
1.4
1.5
1
3.2
3.1
3.3
ns
ns
ns
Y
Y
Y
pd
t
en
OE
OE
10
4.1
4.4
1
t
12.6
5.7
1
dis
operating characteristics, T = 25°
A
V
CC
= 1.8 V
V
= 2.5 V
V
CC
= 3.3 V
V
= 5 V
TEST
CONDITIONS
CC
TYP
CC
TYP
PARAMETER
UNIT
TYP
19
2
TYP
Outputs enabled
Outputs disabled
19
2
20
2
22
3
Power dissipation
capacitance
C
f = 10 MHz
pF
pd
5
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SCES205H − APRIL 1999 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
LOAD
Open
S1
R
L
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
PLH PHL
/t
C
L
t
V
R
PLZ PZL
LOAD
GND
L
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
C
R
L
V
LOAD
L
∆
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5 V 0.5 V
V
V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
V
/2
/2
2 × V
2 × V
6 V
2 × V
CC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
CC
CC
CC
3 V
1.5 V
/2
V
CC
V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
su
h
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
V
0 V
t
t
t
t
t
PHL
PZL
PLZ
+ V
PLH
PHL
Output
Waveform 1
V
/2
OH
LOAD
V
V
V
M
Output
M
V
V
M
S1 at V
(see Note B)
V
LOAD
OL
∆
V
OL
V
OL
t
PLH
t
t
PZH
PHZ
− V
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
V
M
OH
∆
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
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MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,13
0,65
8
5
0,15 NOM
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
0,25
1
4
0° – 8°
0,60
0,20
3,15
2,75
1,30 MAX
Seating Plane
0,10
0,10
0,00
4188781/C 09/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion
D. Falls within JEDEC MO-187 variation DA.
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IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
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logic.ti.com
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power.ti.com
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microcontroller.ti.com
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