SN74LVC2G32-Q1 [TI]
汽车类 2 通道、2 输入、1.65V 至 5.5V 或门;
| 型号： | SN74LVC2G32-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 2 通道、2 输入、1.65V 至 5.5V 或门 |
| 文件： | 总17页 (文件大小：877K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC2G32-Q1
www.ti.com.cn
ZHCSA64 –AUGUST 2012
双路双输入正或门
查询样品: SN74LVC2G32-Q1
1
特性
•
•
•
在VCC=3.3 V，TA=25°C 时，典型电压输出低峰
值（输出地弹反射）
<0.8V
2
•
符合汽车应用要求
具有符合 AEC-Q100 的下列结果：
•
在 VCC=3.3V，TA=25°C 时，典型电压输出高谷值
(VOH下冲)
>2V
–
–
–
器件温度 1 级：-40°C 至 125°C 的环境运行温
度范围
器件人体模型 (HBM) 静电放电 (ESD) 分类等级
H2
I
关闭状态电流支持部分断电模式运行
器件充电器件模型 (CDM) ESD 分类等级 C3B
应用范围
•
•
•
•
输入接受的电压达到 5.5V
•
•
车载应用
3.3V 时，最大传播（延迟）时间为 3.8ns
低功耗，最大电源电流 10μA
3.3V 时，输出驱动 ±24mA
逻辑和栅极
DCU PACKAGE
(TOP VIEW)
1A
1B
2Y
VCC
1Y
2B
2A
1
2
3
4
8
7
6
5
GND
说明
这个双路上输入正或门被设计用于 1.65V 至 5.5V 集流器电源电压运行。
Y + A ) B or Y + A • B
SN74LVC2G32-Q1 在正逻辑中 执行布尔函数 。
NanoFree™ 封装技术是IC 封装概念的一项重大突破，它将硅晶片用作封装。
该器件完全符合使用关闭状态电流的部分断电应用的规范要求。 关闭状态电流电路禁用输出，从而可防止其断电时
破坏性电流从该器件回流。
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–40°C to 125°C
VSSOP - DCU Reel of 3000
SN74LVC2G32QDCURQ1
SUCQ
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
English Data Sheet: SCES842
SN74LVC2G32-Q1
ZHCSA64 –AUGUST 2012
www.ti.com.cn
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTION TABLE
(EACH GATE)
INPUTS
OUTPUT
Y
A
H
X
L
B
X
H
L
H
H
L
LOGIC DIAGRAM (POSITIVE LOGIC)
1
1A
1B
7
1Y
2Y
2
5
6
2A
2B
3
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX UNIT
VCC Supply voltage range
6.5
6.5
6.5
V
V
VI
Input voltage range(2)
VO
VO
IIK
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2) (3)
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–50
–50
mA
mA
mA
mA
°C
kV
V
IOK
IO
Output clamp current
VO < 0
Continuous output current
±50
Continuous current through VCC or GND
Storage temperature range
±100
Tstg
–65
150
2
Human body model (HBM) AEC-Q100 classification level H2
Charged device model (CDM) AEC-Q100 classification level C3B
ESD Rating
750
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
THERMAL INFORMATION
SN74LVC2G32-Q1
THERMAL METRIC(1)
UNIT
DCU (8 PINS)
θJA
Junction-to-ambient thermal resistance
204.4
77
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
83.2
7.1
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
82.7
N/A
θJCbot
(1) 有关传统和新的热 度量的更多信息，请参阅IC 封装热度量应用报告， SPRA953。
2
Copyright © 2012, Texas Instruments Incorporated
SN74LVC2G32-Q1
www.ti.com.cn
ZHCSA64 –AUGUST 2012
RECOMMENDED OPERATING CONDITIONS(1)
MIN
MAX UNIT
Operating
1.65
1.5
5.5
V
VCC
Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.65 × VCC
1.7
VIH
High-level input voltage
V
2
0.7 × VCC
0.35 × VCC
0.7
VIL
Low-level input voltage
V
0.8
0.3 × VCC
5.5
VCC
–4
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
–8
IOH
High-level output current
Low-level output current
–16
–24
–32
4
mA
mA
VCC = 3 V
VCC = 4.5 V
VCC = 1.65 V
VCC = 2.3 V
8
IOL
16
VCC = 3 V
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
20
Δt/Δv
Input transition rise or fall rate
Operating free-air temperature
10
ns/V
°C
5
TA
–40
125
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 2012, Texas Instruments Incorporated
3
SN74LVC2G32-Q1
ZHCSA64 –AUGUST 2012
www.ti.com.cn
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 5.5 V
1.65 V
MIN TYP(1)
VCC – 0.1
MAX UNIT
IOH = –100 μA
IOH = –4 mA
IOH = –8 mA
IOH = –16 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 μA
IOL = 4 mA
1.2
1.9
2.4
2.3
3.8
2.3 V
VOH
V
3 V
4.5 V
1.65 V to 5.5 V
1.65 V
0.1
0.45
IOL = 8 mA
2.3 V
0.3
V
VOL
IOL = 16 mA
0.4
3 V
IOL = 24 mA
0.6
0.6
IOL = 32 mA
4.5 V
0 to 5.5 V
0
II
A or B inputs
VI = 5.5 V or GND
VI or VO = 5.5 V
VI = 5.5 V or GND,
±5
±10
10
μA
μA
μA
μA
pF
Ioff
ICC
IO = 0
1.65 V to 5.5 V
3 V to 5.5 V
3.3 V
ΔICC
One input at VCC – 0.6 V, Other inputs at VCC or GND
VI = VCC or GND
500
Ci
5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
7.5
MIN MAX
5.8
MIN
MAX
4.7
tpd
A or B
Y
2.4
11
1
1
1
ns
OPERATING CHARACTERISTICS
TA = 25°C
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
VCC = 5 V
PARAMETER
TEST CONDITIONS
f = 10 MHz
UNIT
TYP
Cpd
Power dissipation capacitance
17
17
17
19
pF
4
Copyright © 2012, Texas Instruments Incorporated
SN74LVC2G32-Q1
www.ti.com.cn
ZHCSA64 –AUGUST 2012
PARAMETER MEASUREMENT INFORMATION
VLOAD
Open
GND
S1
RL
From Output
Under Test
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
CL
(see Note A)
VLOAD
GND
RL
LOAD CIRCUIT
INPUTS
VCC
VM
VLOAD
CL
RL
V
D
VI
tr/tf
VCC
VCC
3 V
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
£2 ns
£2 ns
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6 V
30 pF
30 pF
50 pF
50 pF
1 kW
0.15 V
0.15 V
0.3 V
500 W
500 W
500 W
£2.5 ns
£2.5 ns
2 × VCC
0.3 V
VI
Timing Input
Data Input
VM
0 V
tW
tsu
th
VI
VI
Input
VM
VM
VM
VM
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VI
Output
Control
VM
VM
Input
VM
VM
0 V
0 V
tPZL
tPLZ
tPLH
tPHL
VM
Output
Waveform 1
S1 at VLOAD
VOH
VOL
VLOAD/2
VOL
VM
VM
Output
Output
VOL + V
D
(see Note B)
tPHL
tPLH
tPZH
tPHZ
VOH
VOL
Output
Waveform 2
S1 at GND
VOH
VOH – V
D
VM
VM
VM
»0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 2012, Texas Instruments Incorporated
5
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74LVC2G32DCTR
SN74LVC2G32DCTRE4
SN74LVC2G32DCTRG4
SN74LVC2G32DCUR
ACTIVE
SM8
SM8
DCT
8
8
8
8
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
C32
(R, Z)
ACTIVE
ACTIVE
ACTIVE
DCT
NIPDAU
NIPDAU
C32
(R, Z)
SM8
DCT
C32
(R, Z)
VSSOP
DCU
NIPDAU | SN
(C32J, C32Q, C32R)
CR
SN74LVC2G32DCURE4
SN74LVC2G32DCURG4
SN74LVC2G32DCUT
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
VSSOP
DCU
DCU
DCU
8
8
8
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
C32R
C32R
250
RoHS & Green
NIPDAU | SN
(C32J, C32Q, C32R)
CR
SN74LVC2G32QDCURQ1
SN74LVC2G32YZPR
ACTIVE
ACTIVE
VSSOP
DSBGA
DCU
YZP
8
8
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 85
SUCQ
SNAGCU
CGN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
YZP0008
DSBGA - 0.5 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.05 C
0.19
0.15
BALL TYP
0.5 TYP
D
C
B
SYMM
1.5
TYP
0.5
TYP
A
0.25
0.21
8X
1
2
0.015
C A B
SYMM
4223082/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YZP0008
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
8X ( 0.23)
2
1
A
(0.5) TYP
B
C
SYMM
D
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
(
0.23)
SOLDER MASK
OPENING
0.05 MAX
0.05 MIN
SOLDER MASK
OPENING
(
0.23)
METAL
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4223082/A 07/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZP0008
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
8X ( 0.25)
(R0.05) TYP
1
2
A
(0.5)
TYP
B
C
SYMM
METAL
TYP
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4223082/A 07/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
DCT0008A
SSOP - 1.3 mm max height
S
C
A
L
E
3
.
5
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
4.25
3.75
TYP
PIN 1 ID
AREA
A
6X 0.65
8
1
2X
3.15
2.75
1.95
NOTE 3
4
5
0.30
0.15
8X
2.9
2.7
NOTE 4
1.3
1.0
0.13
C A B
B
(0.15) TYP
0.25
SEE DETAIL A
GAGE PLANE
0.1
0.0
0.6
0.2
0 - 8
DETAIL A
TYPICAL
4220784/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DCT0008A
SSOP - 1.3 mm max height
SMALL OUTLINE PACKAGE
8X (1.1)
SYMM
(R0.05)
TYP
1
8
8X (0.4)
SYMM
6X (0.65)
5
4
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220784/C 06/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCT0008A
SSOP - 1.3 mm max height
SMALL OUTLINE PACKAGE
8X (1.1)
SYMM
1
8
8X (0.4)
SYMM
6X (0.65)
5
4
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4220784/C 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DCU0008A
VSSOP - 0.9 mm max height
S
C
A
L
E
6
.
0
0
0
SMALL OUTLINE PACKAGE
3.2
3.0
TYP
C
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
6X 0.5
8
1
2X
2.1
1.9
1.5
NOTE 3
4
5
0.25
0.17
8X
2.4
2.2
B
0.08
C A B
NOTE 3
SEE DETAIL A
0.9
0.6
0.12
GAGE PLANE
0.1
0.0
0.35
0.20
0 -6
(0.13) TYP
A
30
DETAIL A
TYPICAL
4225266/A 09/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-187 variation CA.
www.ti.com
EXAMPLE BOARD LAYOUT
DCU0008A
VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE
SEE SOLDER MASK
DETAILS
SYMM
8X (0.85)
(R0.05) TYP
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(3.1)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
OPENING
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4225266/A 09/2014
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DCU0008A
VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE
8X (0.85)
SYMM
(R0.05) TYP
8
1
8X (0.3)
SYMM
6X (0.5)
4
5
(3.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 25X
4225266/A 09/2014
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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