SN74LVC3G07DCTR [TI]

TRIPLE BUFFER / DRIVER WITH OPEN DRAIN OUTPUTS; 三重缓冲/驱动器,具有漏极开路输出
SN74LVC3G07DCTR
型号: SN74LVC3G07DCTR
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

TRIPLE BUFFER / DRIVER WITH OPEN DRAIN OUTPUTS
三重缓冲/驱动器,具有漏极开路输出

驱动器 逻辑集成电路 光电二极管 输出元件
文件: 总13页 (文件大小:339K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SN74LVC3G07  
TRIPLE BUFFER/DRIVER  
WITH OPEN-DRAIN OUTPUTS  
www.ti.com  
SCES365HAUGUST 2001REVISED JUNE 2005  
FEATURES  
DCT OR DCU PACKAGE  
(TOP VIEW)  
Available in the Texas Instruments  
NanoStar™ and NanoFree™ Packages  
1A  
3Y  
2A  
V
CC  
1
2
3
4
8
7
6
5
Supports 5-V VCC Operation  
Max tpd of 3.7 ns at 3.3 V  
1Y  
3A  
2Y  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
GND  
Input and Open-Drain Output Accepts  
Voltages up to 5.5 V  
YEA, YEP, YZA, OR YZP PACKAGE  
(BOTTOM VIEW)  
Typical VOLP (Output Ground Bounce) <0.8 V  
at VCC = 3.3 V, TA = 25°C  
4
3
2
1
5
6
7
8
GND  
2A  
2Y  
3A  
1Y  
Typical VOHV (Output VOH Undershoot) >2 V at  
VCC = 3.3 V, TA = 25°C  
3Y  
1A  
V
CC  
Ioff Supports Partial-Power-Down Mode  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This triple buffer/driver is designed for 1.65-V to 5.5-V VCC operation.  
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
NanoStar™ – WCSP (DSBGA)  
0.17-mm Small Bump – YEA  
SN74LVC3G07YEAR  
NanoFree™ – WCSP (DSBGA)  
0.17-mm Small Bump – YZA (Pb-free)  
SN74LVC3G07YZAR  
SN74LVC3G07YEPR  
SN74LVC3G07YZPR  
Reel of 3000  
_ _ _CV_  
NanoStar™ – WCSP (DSBGA)  
0.23-mm Large Bump – YEP  
–40°C to 85°C  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SSOP – DCT  
Reel of 3000  
Reel of 3000  
Reel of 250  
SN74LVC3G07DCTR  
SN74LVC3G07DCUR  
SN74LVC3G07DCUT  
C07_ _ _  
C07_  
VSSOP – DCU  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one  
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2001–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
SN74LVC3G07  
TRIPLE BUFFER/DRIVER  
WITH OPEN-DRAIN OUTPUTS  
www.ti.com  
SCES365HAUGUST 2001REVISED JUNE 2005  
DESCRIPTION/ORDERING INFORMATION (CONTINUED)  
The output of the SN74LVC3G07 is open drain and can be connected to other open-drain outputs to implement  
active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32 mA.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
FUNCTION TABLE  
(EACH BUFFER/DRIVER)  
INPUT  
A
OUTPUT  
Y
H
L
H
L
LOGIC DIAGRAM (POSITIVE LOGIC)  
1
3
6
7
5
2
1A  
2A  
3A  
1Y  
2Y  
3Y  
Absolute Maximum Ratings(1)  
over operating free-air temperature range (unless otherwise noted)  
MIN  
–0.5  
–0.5  
–0.5  
–0.5  
MAX UNIT  
VCC Supply voltage range  
6.5  
6.5  
6.5  
6.5  
–50  
–50  
V
V
VI  
Input voltage range(2)  
VO  
VO  
IIK  
Voltage range applied to any output in the high-impedance or power-off state(2)  
Voltage range applied to any output in the high or low state(2)(3)  
V
V
Input clamp current  
VI < 0  
mA  
mA  
IOK  
IO  
Output clamp current  
VO < 0  
Continuous output current  
Continuous current through VCC or GND  
±50 mA  
±100 mA  
220  
DCT package  
DCU package  
227  
θJA  
Package thermal impedance(4)  
°C/W  
140  
YEA/YZA package  
YEP/YZP package  
102  
Tstg  
Storage temperature range  
–65  
150  
°C  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.  
(3) The value of VCC is provided in the recommended operating conditions table.  
(4) The package thermal impedance is calculated in accordance with JESD 51-7.  
2
SN74LVC3G07  
TRIPLE BUFFER/DRIVER  
WITH OPEN-DRAIN OUTPUTS  
www.ti.com  
SCES365HAUGUST 2001REVISED JUNE 2005  
Recommended Operating Conditions(1)  
MIN  
1.65  
MAX UNIT  
Operating  
5.5  
V
VCC  
Supply voltage  
Data retention only  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 3 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 3 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
1.5  
0.65 × VCC  
1.7  
VIH  
High-level input voltage  
V
2
0.7 × VCC  
0.35 × VCC  
0.7  
VIL  
Low-level input voltage  
V
0.8  
0.3 × VCC  
VI  
Input voltage  
0
0
5.5  
5.5  
4
V
V
VO  
Output voltage  
VCC = 1.65 V  
VCC = 2.3 V  
8
IOL  
Low-level output current  
16  
24  
32  
20  
10  
5
mA  
VCC = 3 V  
VCC = 4.5 V  
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V  
VCC = 3.3 V ± 0.3 V  
VCC = 5 V ± 0.5 V  
t/v  
Input transition rise or fall rate  
Operating free-air temperature  
ns/V  
°C  
TA  
–40  
85  
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
Electrical Characteristics  
over recommended operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
1.65 V to 5.5 V  
1.65 V  
MIN TYP(1) MAX UNIT  
IOL = 100 µA  
IOL = 4 mA  
0.1  
0.45  
IOL = 8 mA  
2.3 V  
0.3  
V
VOL  
IOL = 16 mA  
0.4  
3 V  
IOL = 24 mA  
0.55  
0.55  
IOL = 32 mA  
4.5 V  
0 to 5.5 V  
0
II  
A inputs  
VI = 5.5 V or GND  
VI or VO = 5.5 V  
VI = 5.5 V or GND,  
±5  
±10  
10  
µA  
µA  
µA  
µA  
pF  
Ioff  
ICC  
ICC  
Ci  
IO = 0  
1.65 V to 5.5 V  
3 V to 5.5 V  
3.3 V  
One input at VCC – 0.6 V,  
VI = VCC or GND  
Other inputs at VCC or GND  
500  
3.5  
(1) All typical values are at VCC = 3.3 V, TA = 25°C.  
3
SN74LVC3G07  
TRIPLE BUFFER/DRIVER  
WITH OPEN-DRAIN OUTPUTS  
www.ti.com  
SCES365HAUGUST 2001REVISED JUNE 2005  
Switching Characteristics  
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)  
VCC = 1.8 V  
± 0.15 V  
VCC = 2.5 V  
± 0.2 V  
VCC = 3.3 V  
± 0.3 V  
VCC = 5 V  
± 0.5 V  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
MIN  
MAX  
MIN  
MAX  
4.3  
MIN  
MAX  
3.7  
MIN MAX  
2.9  
tpd  
A
Y
1.5  
7.8  
1
1.1  
1
ns  
Operating Characteristics  
TA = 25°C  
VCC = 1.8 V  
VCC = 2.5 V  
VCC = 3.3 V  
VCC = 5 V  
PARAMETER  
TEST CONDITIONS  
UNIT  
TYP  
TYP  
TYP  
TYP  
Cpd  
Power dissipation capacitance  
f = 10 MHz  
3
3
4
5
pF  
4
SN74LVC3G07  
TRIPLE BUFFER/DRIVER  
WITH OPEN-DRAIN OUTPUTS  
www.ti.com  
SCES365HAUGUST 2001REVISED JUNE 2005  
PARAMETER MEASUREMENT INFORMATION  
(OPEN DRAIN)  
V
LOAD  
S1  
Open  
GND  
R
L
TEST  
S1  
From Output  
Under Test  
t
(see Notes E and F)  
(see Notes E and G)  
V
V
V
PZL  
LOAD  
LOAD  
LOAD  
C
L
t
PLZ  
R
L
(see Note A)  
t
/t  
PHZ PZH  
LOAD CIRCUIT  
INPUT  
t /t  
r f  
V
M
V
LOAD  
V
C
L
R
L
V
CC  
V
I
1.8 V ± 0.15 V  
2.5 V ± 0.2 V  
3.3 V ± 0.3 V  
5 V ± 0.5 V  
V
V
3 V  
V
V
/2  
/2  
2 × V  
2 × V  
6 V  
1 k  
500 Ω  
500 Ω  
500 Ω  
0.15 V  
0.15 V  
0.3 V  
2 ns  
2 ns  
2.5 ns  
2.5 ns  
30 pF  
30 pF  
50 pF  
50 pF  
CC  
CC  
CC  
CC  
CC  
CC  
1.5 V  
/2  
V
CC  
V
CC  
2 × V  
CC  
0.3 V  
V
I
Timing Input  
Data Input  
V
M
0 V  
t
w
t
t
h
su  
V
I
V
I
V
M
V
M
Input  
V
M
V
M
0 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
V
V
I
I
Output  
Control  
V
M
V
M
V
M
V
M
Input  
0 V  
0 V  
t
t
t
t
t
PHL  
PZL  
PLZ  
PLH  
Output  
Waveform 1  
S1 at V  
LOAD  
(see Note B)  
V
/2  
/2  
LOAD  
V
V
OH  
V
V
V
V
V
M
M
M
Output  
V
V
+ V  
OL  
V
OL  
OL  
t
t
t
PHL  
PLH  
PZH  
PHZ  
Output  
Waveform 2  
S1 at V  
LOAD  
(see Note B)  
V
LOAD  
V
V
OH  
− V  
LOAD/2  
M
V
M
M
Output  
0 V  
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 .  
O
D. The outputs are measured one at a time, with one transition per measurement.  
E. Since this device has open-drain outputs, t  
and t are the same as t .  
PZL pd  
PLZ  
F.  
G.  
t
t
is measured at V .  
M
is measured at V + V .  
OL  
PZL  
PLZ  
H. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuit and Voltage Waveforms  
5
PACKAGE OPTION ADDENDUM  
www.ti.com  
6-Jun-2005  
PACKAGING INFORMATION  
Orderable Device  
SN74LVC3G07DCTR  
SN74LVC3G07DCUR  
SN74LVC3G07DCURE4  
SN74LVC3G07DCUT  
SN74LVC3G07DCUTE4  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SM8  
DCT  
8
8
8
8
8
3000  
3000  
3000  
250  
Pb-Free  
(RoHS)  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
US8  
US8  
US8  
US8  
DCU  
DCU  
DCU  
DCU  
Pb-Free  
(RoHS)  
Pb-Free  
(RoHS)  
Pb-Free  
(RoHS)  
250  
Pb-Free  
(RoHS)  
SN74LVC3G07YEAR  
SN74LVC3G07YEPR  
SN74LVC3G07YZAR  
ACTIVE  
ACTIVE  
ACTIVE  
WCSP  
WCSP  
WCSP  
YEA  
YEP  
YZA  
8
8
8
3000  
3000  
3000  
TBD  
TBD  
SNPB  
SNPB  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Pb-Free  
(RoHS)  
SNAGCU  
SN74LVC3G07YZPR  
ACTIVE  
WCSP  
YZP  
8
3000  
Pb-Free  
(RoHS)  
SNAGCU  
Level-1-260C-UNLIM  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
MECHANICAL DATA  
MPDS049B – MAY 1999 – REVISED OCTOBER 2002  
DCT (R-PDSO-G8)  
PLASTIC SMALL-OUTLINE PACKAGE  
0,30  
0,15  
M
0,13  
0,65  
8
5
0,15 NOM  
2,90  
2,70  
4,25  
3,75  
Gage Plane  
PIN 1  
INDEX AREA  
0,25  
1
4
0° – 8°  
0,60  
0,20  
3,15  
2,75  
1,30 MAX  
Seating Plane  
0,10  
0,10  
0,00  
4188781/C 09/02  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion  
D. Falls within JEDEC MO-187 variation DA.  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process  
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does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.  
Use of such information may require a license from a third party under the patents or other intellectual property  
of the third party, or a license from TI under the patents or other intellectual property of TI.  
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