SN74LVC3G17DCURG4 [TI]
具有施密特触发输入的 3 通道、1.65V 至 5.5V 缓冲器 | DCU | 8 | -40 to 125;型号: | SN74LVC3G17DCURG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有施密特触发输入的 3 通道、1.65V 至 5.5V 缓冲器 | DCU | 8 | -40 to 125 栅 光电二极管 逻辑集成电路 触发器 |
文件: | 总12页 (文件大小:259K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SCES470A − AUGUST 2003 − REVISED AUGUST 2003
DCT OR DCU PACKAGE
(TOP VIEW)
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
D
D
D
D
D
D
Supports 5-V V
Operation
CC
1A
3Y
2A
V
CC
1
2
3
4
8
7
6
5
Inputs Accept Voltages to 5.5 V
1Y
3A
2Y
Max t of 5.4 ns at 3.3 V
pd
Low Power Consumption, 10-µA Max I
GND
CC
24-mA Output Drive at 3.3 V
YEP OR YZP PACKAGE
(BOTTOM VIEW)
Typical V
<0.8 V at V
(Output Ground Bounce)
= 3.3 V, T = 25°C
OLP
CC
A
4 5
3 6
2 7
1 8
GND
2A
3Y
2Y
3A
1Y
D
D
D
D
Typical V
(Output V
Undershoot)
OHV
OH
>2 V at V
= 3.3 V, T = 25°C
CC
A
I
Supports Partial-Power-Down Mode
off
1A
V
CC
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This triple Schmitt-trigger buffer is designed for 1.65-V to 5.5-V V
operation.
CC
The SN74LVC3G17 contains three buffers, and performs the Boolean function Y = A. The device functions as
three independent buffers, but because of Schmitt action, it may have different input threshold levels for
positive-going (V ) and negative-going (V ) signals.
T+
T−
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
‡
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
SN74LVC3G17YEPR
SN74LVC3G17YZPR
Tape and reel
_ _ _C7_
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
−40°C to 85°C
SSOP − DCT
Tape and reel
Tape and reel
SN74LVC3G17DCTR
SN74LVC3G17DCUR
C17_ _ _
C17_
VSSOP − DCU
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin
1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCES470A − AUGUST 2003 − REVISED AUGUST 2003
FUNCTION TABLE
(each inverter)
INPUT
A
OUTPUT
Y
H
L
H
L
logic diagram (positive logic)
1
3
6
7
5
2
1A
1Y
2Y
3Y
2A
3A
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 3): DCT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C/W
JA
DCU package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 102°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCES470A − AUGUST 2003 − REVISED AUGUST 2003
recommended operating conditions (see Note 4)
MIN
1.65
0
MAX
5.5
UNIT
V
V
V
Supply voltage
Input voltage
Output voltage
Operating
V
V
V
CC
5.5
I
0
V
CC
−4
O
V
V
= 1.65 V
= 2.3 V
CC
−8
CC
−16
−24
−32
4
I
High-level output current
mA
OH
OL
V
= 3 V
CC
V
CC
V
CC
V
CC
= 4.5 V
= 1.65 V
= 2.3 V
8
16
24
32
85
I
Low-level output current
mA
V
= 3 V
CC
CC
V
= 4.5 V
T
Operating free-air temperature
−40
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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SCES470A − AUGUST 2003 − REVISED AUGUST 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
0.79
1.11
1.5
MAX
1.16
1.56
1.87
2.74
3.33
0.62
0.87
1.14
1.79
2.29
0.62
0.77
0.87
1.04
1.11
UNIT
V
CC
1.65 V
2.3 V
V
T+
3 V
Positive-going input
threshold voltage
V
4.5 V
2.16
2.61
0.39
0.58
0.84
1.41
1.87
0.37
0.48
0.56
0.71
0.71
5.5 V
1.65 V
2.3 V
V
T−
3 V
Negative-going input
threshold voltage
V
V
4.5 V
5.5 V
1.65 V
2.3 V
∆V
T
3 V
Hysteresis
(V − V
)
T+ T−
4.5 V
5.5 V
I
I
I
I
I
I
I
I
I
I
I
I
= −100 µA
= −4 mA
= −8 mA
= −16 mA
= −24 mA
= −32 mA
= 100 µA
= 4 mA
1.65 V to 5.5 V
1.65 V
2.3 V
V
−0.1
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
CC
1.2
1.9
2.4
2.3
3.8
V
OH
V
3 V
4.5 V
1.65 V to 5.5 V
1.65 V
0.1
0.45
0.3
0.4
0.55
0.55
1
= 8 mA
2.3 V
V
OL
V
= 16 mA
= 24 mA
= 32 mA
3 V
4.5 V
0 to 5.5 V
0
I
I
I
V = 5.5 V or GND
µA
µA
µA
µA
pF
I
I
V or V = 5.5 V
5
off
I
O
V = 5.5 V or GND,
I = 0
O
1.65 V to 5.5 V
3 V to 5.5 V
3.3 V
10
CC
I
∆I
CC
One input at V
CC
− 0.6 V, Other inputs at V
CC
or GND
500
C
V = V
or GND
= 3.3 V, T = 25°C.
4
i
I
CC
†
All typical values are at V
CC
A
switching characteristics over recommended operating free-air temperature range, C = 15 pF
L
(unless otherwise noted) (see Figure 1)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
V
= 5 V
CC
0.15 V
CC
0.2 V
CC
0.3 V
CC
0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
MIN
MAX
MIN
MAX
MIN
MAX
‡
‡
‡
‡
‡
‡
‡
‡
t
pd
A
ns
Y
‡
This information was not available at the time of publication.
4
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SCES470A − AUGUST 2003 − REVISED AUGUST 2003
switching characteristics over recommended operating free-air temperature range, C = 30 pF or
L
50 pF (unless otherwise noted) (see Figure 2)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
V
= 5 V
CC
0.15 V
CC
0.2 V
CC
0.3 V
CC
0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
4.3
MAX
MIN
MAX
MIN
1.2
MAX
MIN
MAX
4.1
t
pd
A
9.2
2
6.2
5.4
1
ns
Y
operating characteristics, T = 25°C
A
V
CC
= 1.8 V
V
= 2.5 V
V
CC
= 3.3 V
V
= 5 V
CC
TYP
19
CC
TYP
22
PARAMETER
TEST CONDITIONS
f = 10 MHz
UNIT
TYP
TYP
19
C
Power dissipation capacitance
18
pF
pd
5
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ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉꢂ
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SCES470A − AUGUST 2003 − REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
V
LOAD
Open
S1
R
L
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
PLH PHL
/t
C
L
t
V
R
PLZ PZL
LOAD
GND
L
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
C
R
L
V
LOAD
L
∆
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5 V 0.5 V
V
V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
V
/2
/2
2 × V
2 × V
6 V
2 × V
CC
15 pF
15 pF
15 pF
15 pF
1 MΩ
1 MΩ
1 MΩ
1 MΩ
0.15 V
0.15 V
0.3 V
CC
CC
CC
CC
CC
CC
3 V
1.5 V
/2
V
CC
V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
su
h
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
V
0 V
t
t
t
t
t
PHL
PZL
PLZ
+ V
PLH
PHL
Output
Waveform 1
V
/2
OH
LOAD
V
V
V
M
Output
M
V
V
M
S1 at V
(see Note B)
V
LOAD
OL
∆
V
OL
V
OL
t
PLH
t
t
PZH
PHZ
− V
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
V
M
OH
∆
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
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SCES470A − AUGUST 2003 − REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
V
LOAD
Open
S1
R
L
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
PLH PHL
/t
C
L
t
V
R
PLZ PZL
LOAD
GND
L
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
C
R
L
V
LOAD
L
∆
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5 V 0.5 V
V
V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
V
/2
/2
2 × V
2 × V
6 V
2 × V
CC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
CC
CC
CC
3 V
1.5 V
/2
V
CC
V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
su
h
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
V
0 V
t
t
t
t
t
PHL
PZL
PLZ
+ V
PLH
PHL
Output
Waveform 1
V
/2
OH
LOAD
V
V
V
M
Output
M
V
V
M
S1 at V
(see Note B)
V
LOAD
OL
∆
V
OL
V
OL
t
PLH
t
t
PZH
PHZ
− V
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
V
M
OH
∆
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,13
0,65
8
5
0,15 NOM
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
0,25
1
4
0° – 8°
0,60
0,20
3,15
2,75
1,30 MAX
Seating Plane
0,10
0,10
0,00
4188781/C 09/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion
D. Falls within JEDEC MO-187 variation DA.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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