SN74LVC646APWR [TI]
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| 型号： | SN74LVC646APWR |
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TEXAS INSTRUMENTS |
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SN74LVC646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS302A – JANUARY 1993 – REVISED JULY 1995
DB, DW, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
1
24
23
22
21
20
19
18
17
16
15
14
13
= 3.3 V, T = 25°C
CC
A
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
2
Typical V
> 2 V at V
(Output V
Undershoot)
3
OHV
OH
= 3.3 V, T = 25°C
4
CC
A
5
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
6
7
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
8
9
10
11
12
description
B8
This octal bus transceiver and register is designed for 2.7-V to 3.6-V V
operation.
CC
The SN74LVC646 consists of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus
is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input.
Figure 1 illustrates the four fundamental bus-management functions that can be performed with the
SN74LVC646.
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver
mode, data present at the high-impedance port can be stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR
determines which bus receives data when OE is low. In the isolation mode (OE high), A data can be stored in
one register and B data can be stored in the other register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVC646 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
DATA I/Os
B1 – B8
OPERATION OR FUNCTION
OE
X
X
H
H
L
DIR
X
CLKAB
CLKBA
SAB
X
SBA
X
A1 – A8
Input
†
†
†
↑
X
Unspecified
Input
Store A, B unspecified
Store B, A unspecified
Store A and B data
†
X
X
↑
X
X
Unspecified
X
↑
H or L
X
↑
H or L
X
X
X
Input
Input
X
X
X
Input disabled
Output
Input disabled
Input
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
L
X
L
L
L
X
H or L
X
X
H
Output
Input
L
H
H
X
L
X
Input
Output
L
H or L
X
H
X
Input
Output
†
The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins is stored on every low-to-high transition of the clock inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS302A – JANUARY 1993 – REVISED JULY 1995
21
OE
L
3
1
23
2
22
SBA
21
OE
L
3
DIR
1
23
CLKAB CLKBA SAB
L
2
22
SBA
DIR CLKAB CLKBA SAB
L
X
X
X
L
H
X
X
X
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
21
3
1
23
2
22
21
OE
L
3
DIR
L
1
23
2
22
SBA
H
DIR CLKAB CLKBA SAB
SBA
X
CLKAB CLKBA SAB
OE
X
X
X
X
X
↑
X
X
X
↑
X
X
H or L
X
X
H
X
H
X
X
L
H
H or L
X
↑
↑
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS302A – JANUARY 1993 – REVISED JULY 1995
†
logic symbol
21
3
G3
OE
DIR
3 EN1 [BA]
3 EN2 [AB]
23
22
1
CLKBA
SBA
C4
G5
CLKAB
SAB
C6
2
G7
20
4D
B1
5
5
≥1
4
A1
1
1
6D
7
7
≥1
2
1
5
19
18
17
16
15
14
13
B2
B3
B4
B5
B6
B7
B8
A2
A3
A4
A5
A6
A7
A8
6
7
8
9
10
11
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS302A – JANUARY 1993 – REVISED JULY 1995
logic diagram (positive logic)
21
OE
3
DIR
23
CLKBA
22
SBA
1
CLKAB
2
SAB
One of Eight
Channels
1D
C1
4
A1
20
B1
1D
C1
To Seven Other Channels
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS302A – JANUARY 1993 – REVISED JULY 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V : Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
I
I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
CC
CC
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum power dissipation at T = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . 0.65 W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
A
DW package . . . . . . . . . . . . . . . . . 1.7 W
PW package . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation,refertothePackageThermalConsiderationsapplicationnoteinthe1994ABTAdvancedBiCMOSTechnology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 3)
MIN
2.7
2
MAX
UNIT
V
V
V
Supply voltage
3.6
V
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
V
V
= 2.7 V to 3.6 V
= 2.7 V to 3.6 V
CC
0.8
5.5
CC
Control inputs
Data inputs
0
0
0
V
V
Input voltage
V
V
I
V
V
CC
Output voltage
O
CC
V
CC
V
CC
V
CC
V
CC
= 2.7 V
= 3 V
–12
–24
12
I
High-level output current
mA
OH
= 2.7 V
= 3 V
I
Low-level output current
mA
OL
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
10
ns/V
T
A
–40
85
°C
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS302A – JANUARY 1993 – REVISED JULY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
†
PARAMETER
TEST CONDITIONS
MIN TYP
–0.2
MAX
UNIT
V
CC
I
I
= –100 µA
MIN to MAX
2.7 V
V
OH
CC
2.2
V
= – 12 mA
V
OH
OH
3 V
2.4
2
I
I
I
I
= – 24 mA
= 100 µA
= 12 mA
= 24 mA
3 V
OH
OL
OL
OL
MIN to MAX
2.7 V
0.2
0.4
V
V
OL
§
3 V
0.55
±5
I
I
I
V = 5.5 V or GND
3.6 V
µA
µA
µA
µA
I
I
V
= V
or GND
3.6 V
±10
20
OZ
CC
O
CC
or GND,
V = V
I = 0
O
3.6 V
I
CC
I
One input at V
– 0.6 V, Other inputs at V or GND
CC
3 V to 3.6 V
500
CC
CC
or GND
Control
inputs
C
C
V = V
3.3 V
3.3 V
4.6
7.2
pF
pF
i
I
CC
A or B
ports
V
= V
or GND
io
O
CC
†
‡
§
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
All typical values are measured at V = 3.3 V, T = 25°C.
CC
A
For I/O ports, the parameter I
includes the input leakage current.
OZ
timing characteristics over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 2)
V
= 3.3 V
CC
± 0.3 V
V
= 2.7 V
MAX
CC
UNIT
MIN
5
MAX
MIN
5
t
w
t
su
t
h
Pulse duration
ns
ns
ns
Setup time, data before CLK↑
Hold time, data after CLK↑
5
5
1
1
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 2)
V
= 3.3 V
CC
± 0.3 V
V
= 2.7 V
MAX
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
MIN
100
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
MIN
f
80
MHz
max
pd
A or B
CLK
B or A
A or B
A or B
A or B
A or B
A or B
A or B
8
9
9.2
11
t
ns
SBA or SAB
OE
9
11
t
t
t
t
8.5
8.5
9
9.5
9.5
10
10
ns
ns
ns
ns
en
dis
en
dis
OE
DIR
DIR
9
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS302A – JANUARY 1993 – REVISED JULY 1995
operating characteristics, V
= 3.3 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
TYP
38
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per transceiver
C
pF
pd
4.2
PARAMETER MEASUREMENT INFORMATION
6 V
TEST
S1
S1
500 Ω
Open
GND
t
Open
6 V
pd
/t
From Output
Under Test
t
PLZ PZL
/t
t
GND
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
2.7 V
0 V
LOAD CIRCUIT FOR OUTPUTS
1.5 V
Timing Input
Data Input
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
1.5 V
1.5 V
Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 6 V
V
V
3 V
OH
1.5 V
1.5 V
1.5 V
Output
1.5 V
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
OH
1.5 V
1.5 V
Output
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 2. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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