SN74LVC74AMDREP [TI]
DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET; 双上升沿触发D型触发器具有清零和预设
| 型号： | SN74LVC74AMDREP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET |
| 文件： | 总13页 (文件大小：550K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC74A-EP
DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
www.ti.com
SCAS751C–DECEMBER 2003–REVISED SEPTEMBER 2007
1
FEATURES
•
Controlled Baseline
•
•
•
Inputs Accept Voltages to 5.5 V
Max tpd of 5.2 ns at 3.3 V
–
One Assembly/Test Site, One Fabrication
Site
Typical VOLP (Output Ground Bounce) <0.8 V at
•
•
Extended Temperature Performance of –40°C
to 125°C and –55°C to 125°C
VCC = 3.3 V, TA = 25°C
•
Typical VOHV (Output VOH Undershoot) >2 V at
VCC = 3.3 V, TA = 25°C
Enhanced Diminishing Manufacturing Sources
(DMS) Support
D OR PW PACKAGE
(TOP VIEW)
•
•
•
Enhanced Product-Change Notification
(1)
Qualification Pedigree
1CLR
1D
14 VCC
Operates From 2 V to 3.6 V
1
2
3
4
5
6
7
13
12
11
10
9
2CLR
2D
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
1CLK
1PRE
1Q
2CLK
2PRE
2Q
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
1Q
8
GND
2Q
DESCRIPTION/ORDERING INFORMATION
The SN74LVC74A dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as a translator in
a mixed 3.3 V/5 V system environment.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
SN74LVC74AQDREP
TOP-SIDE MARKING
LVC74AE
SOIC – D
Reel of 2500
–40°C to 125°C
TSSOP – PW
SOIC – D
Reel of 2000
Reel of 2500
Reel of 2000
SN74LVC74AQPWREP
SN74LVC74AMDREP
LVC74AE
LVC74AM
LVC74AM
–55°C to 125°C
TSSOP – PW
SN74LVC74AMPWREP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC74A-EP
DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
www.ti.com
SCAS751C–DECEMBER 2003–REVISED SEPTEMBER 2007
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
L
CLR
H
CLK
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
X
H
H(1)
L
L
X
H(1)
H
H
↑
H
L
H
H
↑
L
H
H
H
L
X
Q0
Q 0
(1) This configuration is nonstable; that is, it does not persist when PRE
or CLR returns to its inactive (high) level.
LOGIC DIAGRAM, EACH FLIP-FLOP (POSITIVE LOGIC)
PRE
CLK
C
C
C
Q
TG
C
C
C
C
D
TG
TG
TG
Q
C
C
C
CLR
2
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Copyright © 2003–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC74A-EP
SN74LVC74A-EP
DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
www.ti.com
SCAS751C–DECEMBER 2003–REVISED SEPTEMBER 2007
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
6.5
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Output voltage range(2)(3)
6.5
V
VO
IIK
VCC + 0.5
–50
V
Input clamp current
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
–50
Continuous output current
Continuous current through VCC or GND
±50
±100
86
D package
θJA
Package thermal impedance(4)
Storage temperature range
°C/W
°C
PW package
113
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
2
MAX UNIT
Operating
3.6
V
VCC
Supply voltage
Data retention only
VCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
1.5
2
VIH
VIL
VI
High-level input voltage
Low-level input voltage
Input voltage
V
0.8
5.5
VCC
–12
–24
12
V
V
V
0
0
VO
Output voltage
VCC = 2.7 V
VCC = 3 V
VCC = 2.7 V
VCC = 3 V
IOH
High-level output current
mA
IOL
Low-level output current
mA
ns/V
°C
24
Δt/Δv
TA
Input transition rise or fall rate
Operating free-air temperature
10
M suffix
Q suffix
–55
–40
125
125
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 2003–2007, Texas Instruments Incorporated
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3
Product Folder Link(s): SN74LVC74A-EP
SN74LVC74A-EP
DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
www.ti.com
SCAS751C–DECEMBER 2003–REVISED SEPTEMBER 2007
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2.7 V to 3.6 V
2.7 V
MIN TYP(1) MAX
VCC – 0.2
UNIT
IOH = –100 μA
2.2
2.4
2.2
VOH
IOH = –12 mA
V
3 V
IOH = –24 mA
IOL = 100 μA
IOL = 12 mA
3 V
2.7 V to 3.6 V
2.7 V
0.2
0.4
0.55
±5
VOL
V
IOL = 24 mA
3 V
II
VI = 5.5 V or GND
3.6 V
μA
μA
μA
pF
ICC
ΔICC
Ci
VI = VCC or GND, IO = 0
3.6 V
10
One input at VCC – 0.6 V, Other inputs at VCC or GND
VI = VCC or GND
2.7 V to 3.6 V
3.3 V
500
5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
100
fclock
tw
Clock frequency
Pulse duration
83
MHz
ns
PRE or CLR low
CLK high or low
Data
3.3
3.3
3.4
2.2
1
3.3
3.3
3
tsu
th
Setup time before CLK↑
ns
ns
PRE or CLR inactive
2
Hold time, data after CLK↑
1
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
100
1
MAX
fmax
tpd
83
MHz
ns
CLK
6
5.2
5.4
Q or Q
PRE or CLR
6.4
1
Operating Characteristics
TA = 25°C
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
TEST
CONDITIONS
PARAMETER
UNIT
Cpd
Power dissipation capacitance per flip-flop
f = 10 MHz
47
51
pF
4
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Copyright © 2003–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC74A-EP
SN74LVC74A-EP
DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
www.ti.com
SCAS751C–DECEMBER 2003–REVISED SEPTEMBER 2007
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
V
LOAD
GND
R
L
PLZ PZL
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
2.7 V
2.7 V
2.7 V
≤2.5 ns
≤2.5 ns
1.5 V
1.5 V
6 V
6 V
50 pF
50 pF
500 Ω
500 Ω
0.3 V
0.3 V
3.3 V ± 0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
LOAD
V
+ V
∆
OL
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
- V
∆
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 2003–2007, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): SN74LVC74A-EP
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
SN74LVC74AMDREP
SN74LVC74AMPWREP
SN74LVC74AQDREP
SN74LVC74AQPWREP
V62/04669-01XE
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
14
14
14
14
14
14
14
14
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
SOIC
PW
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
SOIC
PW
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
V62/04669-01YE
TSSOP
SOIC
PW
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
V62/04669-02XE
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
V62/04669-02YE
TSSOP
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC74A-EP :
Catalog: SN74LVC74A
Automotive: SN74LVC74A-Q1
Military: SN54LVC74A
•
•
•
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Military - QML certified for Military and Defense Applications
•
•
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC74AMDREP
SOIC
D
PW
D
14
14
14
14
2500
2000
2500
2000
330.0
330.0
330.0
330.0
16.4
12.4
16.4
12.4
6.5
6.9
6.5
6.9
9.0
5.6
9.0
5.6
2.1
1.6
2.1
1.6
8.0
8.0
8.0
8.0
16.0
12.0
16.0
12.0
Q1
Q1
Q1
Q1
SN74LVC74AMPWREP TSSOP
SN74LVC74AQDREP SOIC
SN74LVC74AQPWREP TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVC74AMDREP
SN74LVC74AMPWREP
SN74LVC74AQDREP
SN74LVC74AQPWREP
SOIC
TSSOP
SOIC
D
PW
D
14
14
14
14
2500
2000
2500
2000
333.2
367.0
333.2
367.0
345.9
367.0
345.9
367.0
28.6
35.0
28.6
35.0
TSSOP
PW
Pack Materials-Page 2
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