SN74LVC74 [TI]
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET; 双上升沿触发的D型触发器具有清零和预设
| 型号： | SN74LVC74 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET |
| 文件： | 总6页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCAS287B – JANUARY 1993 – REVISED JULY 1995
D, DB, OR PW PACKAGE
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
(TOP VIEW)
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
1CLR
1D
1CLK
1PRE
1Q
V
CC
2CLR
1
2
3
4
5
6
7
14
13
12
11
10
9
2D
2CLK
2PRE
2Q
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
1Q
GND
Typical V
< 0.8 V at V
(Output Ground Bounce)
2Q
8
OLP
= 3.3 V, T = 25°C
CC
A
Typical V
> 2 V at V
(Output V
Undershoot)
OHV
CC
OH
= 3.3 V, T = 25°C
A
Inputs Accept Voltages to 5.5 V
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
description
This dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V V
operation.
CC
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input may be changed without affecting the levels at the outputs.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
The SN74LVC74 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
L
CLR
CLK
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
†
†
H
L
L
X
H
H
H
H
H
↑
H
L
L
H
↑
H
H
L
X
Q
Q
0
0
†
This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCAS287B – JANUARY 1993 – REVISED JULY 1995
†
logic symbol
4
5
6
9
8
S
1PRE
1CLK
1D
1Q
1Q
2Q
2Q
3
2
1
C1
1D
R
1CLR
10
11
12
13
2PRE
2CLK
2D
2CLR
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram, each flip-flop (positive logic)
PRE
C
TG
C
CLK
C
C
Q
C
TG
C
C
TG
C
C
TG
C
D
Q
CLR
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum power dissipation at T = 55°C (in still air) (see Note 3): D package . . . . . . . . . . . . . . . . . . 1.25 W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
A
DB or PW package . . . . . . . . . . . . 0.5 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation,refertothePackageThermalConsiderationsapplicationnoteinthe1994ABTAdvancedBiCMOSTechnology
Data Book, literature number SCBD002B.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCAS287B – JANUARY 1993 – REVISED JULY 1995
recommended operating conditions (see Note 4)
MIN
2
MAX
UNIT
Operating
3.6
V
Supply voltage
V
CC
Data retention only
1.5
2
V
V
V
V
High-level input voltage
Low-level input voltage
Input voltage
V
V
= 2.7 V to 3.6 V
= 2.7 V to 3.6 V
V
V
V
V
IH
IL
I
CC
0.8
5.5
CC
0
0
Output voltage
V
CC
O
V
CC
V
CC
V
CC
V
CC
= 2.7 V
= 3 V
–12
–24
12
I
High-level output current
Low-level output current
mA
mA
OH
OL
= 2.7 V
= 3 V
I
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
10
ns/V
T
A
–40
85
°C
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
†
PARAMETER
TEST CONDITIONS
MIN TYP
V –0.2
MAX
UNIT
V
CC
I
I
= –100 µA
MIN to MAX
2.7 V
OH
CC
2.2
V
= – 12 mA
V
OH
OL
OH
3 V
2.4
2.2
I
I
I
I
= – 24 mA
= 100 µA
= 12 mA
= 24 mA
3 V
OH
OL
OL
OL
MIN to MAX
2.7 V
0.2
0.4
V
V
3 V
0.55
±5
I
I
V = 5.5 V or GND
3.6 V
µA
µA
µA
pF
I
I
V = V
or GND,
I = 0
O
3.6 V
10
CC
I
CC
I
One input at V
– 0.6 V,
Other inputs at V
CC
or GND
2.7 V to 3.6 V
3.3 V
500
CC
CC
or GND
CC
C
V = V
5
i
I
†
‡
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
All typical values are at V = 3.3 V, T = 25°C.
CC
A
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
V = 3.3 V
CC
± 0.3 V
V
CC
= 2.7 V
UNIT
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency
Pulse duration
100
83
MHz
ns
clock
PRE or CLR low
CLK high or low
Data
4
5
w
5
6
3
4
t
t
ns
ns
Setup time before CLK↑
su
PRE or CLR inactive
2
3
Hold time, data after CLK↑
1
2
h
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCAS287B – JANUARY 1993 – REVISED JULY 1995
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
V
= 3.3 V
CC
± 0.3 V
V
= 2.7 V
MAX
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
MIN
100
1
MAX
MIN
f
t
83
MHz
ns
max
CLK
6.5
8
7
9
Q or Q
pd
PRE or CLR
1
†
t
1
ns
sk(o)
†
Skew between any two outputs of the same package switching in the same direction. This parameter is warranted but not production tested.
operating characteristics, V
= 3.3 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
TYP
UNIT
C
Power dissipation capacitance per flip-flop
C
27
pF
pd
L
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCAS287B – JANUARY 1993 – REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
6 V
TEST
S1
S1
500 Ω
Open
GND
t
Open
6 V
pd
/t
From Output
Under Test
t
PLZ PZL
/t
t
GND
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
t
w
LOAD CIRCUIT
2.7 V
0 V
1.5 V
1.5 V
Input
2.7 V
Timing
Input
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
2.7 V
0 V
Data
Input
2.7 V
0 V
1.5 V
1.5 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
t
PLZ
3 V
Output
Waveform 1
S1 at 6 V
2.7 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
OH
(see Note B)
t
PHZ
t
PLH
t
PHL
PZH
Output
Waveform 2
S1 at GND
V
V
OH
OH
1.5 V
Output
1.5 V
1.5 V
(see Note B)
0 V
V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 Ω, t
D. The outputs are measured one at a time with one transition per measurement.
2.5 ns, t
f
2.5 ns.
O
r
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
dis
are the same as t
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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