SN74LVC821ADGVR [TI]
10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS; 10位总线接口触发器具有三态输出
| 型号： | SN74LVC821ADGVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS |
| 文件： | 总16页 (文件大小：466K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC821A
10-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCAS304J–MARCH 1993–REVISED FEBRUARY 2005
FEATURES
DB, DGV, DW, NS, OR PW PACKAGE
(TOP VIEW)
•
•
•
•
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 7.3 ns at 3.3 V
OE
1D
2D
1
24
23
22
V
CC
2
1Q
2Q
Typical VOLP (Output Ground Bounce)
3
<0.8 V at VCC = 3.3 V, TA = 25°C
3D
4D
4
21 3Q
20 4Q
•
•
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
5
6
19
18
17
16
15
14
13
5D
6D
7D
8D
5Q
6Q
7Q
8Q
7
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With
8
3.3-V VCC
)
9
10
11
12
9D
10D
GND
9Q
10Q
CLK
•
•
•
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
DESCRIPTION/ORDERING INFORMATION
This 10-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC821A features 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. This device is particularly suitable for implementing wider buffer registers, I/O ports,
bidirectional bus drivers with parity, and working registers.
The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the
device provides true data at the Q outputs.
A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can
be entered while the outputs are in the high-impedance state.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74LVC821ADW
TOP-SIDE MARKING
Tube of 25
SOIC – DW
LVC821A
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 60
SN74LVC821ADWR
SN74LVC821ANSR
SN74LVC821ADBR
SN74LVC821APW
SOP – NS
LVC821A
LC821A
SSOP – DB
–40°C to 85°C
TSSOP – PW
TVSOP – DGV
Reel of 2000
Reel of 250
Reel of 2000
SN74LVC821APWR
SN74LVC821APWT
SN74LVC821ADGVR
LC821A
LC821A
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1993–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC821A
10-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCAS304J–MARCH 1993–REVISED FEBRUARY 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(EACH FLIP-FLOP)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
H
L
L
↑
H or L
X
L
X
X
Q0
Z
H
LOGIC DIAGRAM (POSITIVE LOGIC)
1
OE
13
CLK
C1
1D
23
1Q
2
1D
To Nine Other Channels
2
SN74LVC821A
10-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCAS304J–MARCH 1993–REVISED FEBRUARY 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
6.5
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
6.5
V
VO
VO
IIK
6.5
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–50
–50
±50
±100
63
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
DB package
DGV package
DW package
NS package
PW package
86
θJA
Package thermal impedance(4)
46
°C/W
°C
65
88
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
MAX UNIT
Operating
1.65
3.6
V
VCC
Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
1.5
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
0.35 × VCC
0.7
VIL
Low-level input voltage
V
0.8
5.5
VCC
5.5
–4
VI
Input voltage
0
0
0
V
V
High or low state
3-state
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
–8
IOH
High-level output current
Low-level output current
mA
mA
–12
–24
4
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
8
IOL
12
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10
ns/V
TA
–40
85
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
SN74LVC821A
10-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCAS304J–MARCH 1993–REVISED FEBRUARY 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V VCC – 0.2
MIN TYP(1)
MAX UNIT
IOH = –100 µA
IOH = –4 mA
IOH = –8 mA
1.65 V
2.3 V
2.7 V
3 V
1.2
1.7
2.2
2.4
2.2
VOH
V
IOH = –12 mA
IOH = –24 mA
IOL = 100 µA
3 V
1.65 V to 3.6 V
1.65 V
2.3 V
2.7 V
3 V
0.2
IOL = 4 mA
0.45
VOL
IOL = 8 mA
0.7
0.4
0.55
±5
V
IOL = 12 mA
IOL = 24 mA
II
VI = 0 to 5.5 V
VI or VO = 5.5 V
VO = 0 to 5.5 V
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V(2)
3.6 V
0
µA
µA
µA
Ioff
IOZ
±10
±10
10
3.6 V
ICC
∆ICC
Ci
IO = 0
3.6 V
2.7 V to 3.6 V
3.3 V
µA
µA
pF
pF
10
One input at VCC – 0.6 V, Other inputs at VCC or GND
500
Control inputs
Data inputs
5
4
7
VI = VCC or GND
Co
VO = VCC or GND
3.3 V
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This applies in the disabled state only.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
150
(1)
(1)
fclock
tw
Clock frequency
150
MHz
ns
(1)
(1)
(1)
(1)
(1)
(1)
Pulse duration, CLK high or low
Setup time, data before CLK
Hold time, data after CLK
3.3
1.9
1.5
3.3
1.9
1.5
tsu
th
ns
ns
(1) This information was not available at the time of publication.
4
SN74LVC821A
10-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCAS304J–MARCH 1993–REVISED FEBRUARY 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
150
2.2
MAX
(1)
(1)
fmax
tpd
150
MHz
ns
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
CLK
OE
Q
Q
Q
8.5
8.8
6.8
7.3
7.6
6.2
1
ten
1.3
ns
tdis
OE
1.6
ns
tsk(o)
ns
(1) This information was not available at the time of publication.
Operating Characteristics
TA = 25°C
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
TYP
TYP
65
(1)
(1)
Outputs enabled
Outputs disabled
Power dissipation capacitance
per flip-flop
Cpd
f = 10 MHz
pF
(1)
(1)
48
(1) This information was not available at the time of publication.
5
SN74LVC821A
10-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCAS304J–MARCH 1993–REVISED FEBRUARY 2005
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
V
R
L
PLZ PZL
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
V
V
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
/2
/2
2 × V
2 × V
6 V
6 V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
V
CC
CC
CC
1.5 V
1.5 V
3.3 V ± 0.3 V
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
LOAD
V
OL
+ V
∆
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
− V
∆
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SSOP
SSOP
Drawing
SN74LVC821ADBLE
SN74LVC821ADBR
OBSOLETE
ACTIVE
DB
24
24
TBD
Call TI
Call TI
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC821ADBRE4
SN74LVC821ADBRG4
SN74LVC821ADGVR
SN74LVC821ADGVRE4
SN74LVC821ADGVRG4
SN74LVC821ADW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
TVSOP
TVSOP
TVSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SO
DB
DB
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGV
DGV
DGV
DW
DW
DW
DW
DW
DW
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC821ADWE4
SN74LVC821ADWG4
SN74LVC821ADWR
SN74LVC821ADWRE4
SN74LVC821ADWRG4
SN74LVC821ANSR
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC821ANSRE4
SN74LVC821ANSRG4
SN74LVC821APW
SO
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
PW
PW
PW
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC821APWE4
SN74LVC821APWG4
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC821APWLE
SN74LVC821APWR
OBSOLETE TSSOP
PW
PW
24
24
TBD
Call TI
Call TI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC821APWRE4
SN74LVC821APWRG4
SN74LVC821APWT
PW
PW
PW
PW
PW
24
24
24
24
24
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC821APWTE4
SN74LVC821APWTG4
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
Orderable Device
Status (1)
Package Package
Type Drawing
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN74LVC821ADBR
SN74LVC821ADGVR
SN74LVC821ADWR
SN74LVC821ANSR
SN74LVC821APWR
SSOP
TVSOP
SOIC
DB
DGV
DW
NS
24
24
24
24
24
2000
2000
2000
2000
2000
330.0
330.0
330.0
330.0
330.0
16.4
12.4
24.4
24.4
16.4
8.2
7.0
8.8
5.6
2.5
1.6
2.7
2.5
1.6
12.0
8.0
16.0
12.0
24.0
24.0
16.0
Q1
Q1
Q1
Q1
Q1
10.75
8.2
15.7
15.4
8.3
12.0
12.0
8.0
SO
TSSOP
PW
6.95
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVC821ADBR
SN74LVC821ADGVR
SN74LVC821ADWR
SN74LVC821ANSR
SN74LVC821APWR
SSOP
TVSOP
SOIC
DB
DGV
DW
NS
24
24
24
24
24
2000
2000
2000
2000
2000
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
33.0
29.0
41.0
41.0
33.0
SO
TSSOP
PW
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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