SN74LVCC4245ADW [TI]
OCTAL DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS; 具有可配置的输出电压和三态输出的八路双电源总线收发器
| 型号： | SN74LVCC4245ADW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS |
| 文件： | 总10页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVCC4245A
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS584F – NOVEMBER 1996 – REVISED AUGUST 1998
DB, DW, OR PW PACKAGE
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
(TOP VIEW)
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
V
1
2
3
4
5
6
7
8
9
24
V
CCB
CCA
DIR
23 NC
22 OE
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 B7
14 B8
13 GND
Latch-Up Performance Exceeds 250 mA Per
JESD 17
A1
A2
A3
A4
A5
A6
A7
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
description
A8 10
GND 11
GND 12
This 8-bit (octal) noninverting bus transceiver
uses two separate power-supply rails. The A port,
V
, is dedicated to accept a 5-V supply level,
CCA
NC – No internal connection
and the configurable B port, which is designed to
track V , accepts voltages from 3 V to 5 V. This
CCB
allows for translation from a 3.3-V to a 5-V
environment and vice versa.
The SN74LVCC4245A is designed for asynchronous communication between data buses. The device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated.
The SN74LVCC4245A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OPERATION
OE
L
DIR
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCC4245A
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS584F – NOVEMBER 1996 – REVISED AUGUST 1998
logic diagram (positive logic)
2
DIR
22
OE
3
A1
21
B1
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
and V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
CCB
CCA
Input voltage range, V (see Note 1): I/O ports (A port) . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
I
CCA
CCB
CCA
CCA
CCB
I/O ports (B port) . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Except I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Output voltage range, V (see Note 1): (A port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
(B port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W
O
, V
, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CCA CCB
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. This value is limited to 6 V maximum.
2. The package thermal impedance is calculated in accordance with JESD 51.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCC4245A
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS584F – NOVEMBER 1996 – REVISED AUGUST 1998
recommended operating conditions (see Note 3)
V
V
MIN NOM
MAX
5.5
UNIT
V
CCA
CCB
V
V
Supply voltage
Supply voltage
4.5
2.7
2
5
CCA
3.3
5.5
V
CCB
2.7 V
3.6 V
5.5 V
2.7 V
3.6 V
5.5 V
2.7 V
3.6 V
5.5 V
2.7 V
3.6 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
V
IHA
V
IHB
V
ILA
V
ILB
High-level input voltage
High-level input voltage
Low-level input voltage
Low-level input voltage
V
OB
V
OA
V
OB
V
OA
≤ 0.1 V,
≤ 0.1 V,
≤ 0.1 V,
≤ 0.1 V,
V
OB
V
OA
V
OB
V
OA
≥ V
≥ V
≥ V
≥ V
– 0.1 V
– 0.1 V
– 0.1 V
– 0.1 V
2
V
V
V
V
CCB
CCA
CCB
CCA
2
2
2
3.85
0.8
0.8
0.8
0.8
0.8
1.65
V
V
V
V
Input voltage
0
0
0
0
V
V
V
IA
CCA
CCB
CCA
Input voltage
V
V
V
IB
Output voltage
V
OA
Output voltage
V
OB
CCB
–24
I
I
I
I
High-level output current
High-level output current
Low-level output current
Low-level output current
Operating free-air temperature
4.5 V
3 V
mA
mA
mA
mA
°C
OHA
OHB
OLA
OLB
4.5 V 2.7 V to 4.5 V
4.5 V 3 V
4.5 V 2.7 V to 4.5 V
–24
24
24
T
A
–40
85
NOTE 3: AllunusedinputsofthedevicemustbeheldattheassociatedV
orGNDtoensureproperdeviceoperation. RefertotheTIapplication
CC
report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCC4245A
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS584F – NOVEMBER 1996 – REVISED AUGUST 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
4.4
TYP
4.49
4.25
2.99
2.5
MAX
UNIT
V
V
CCB
CCA
I
I
I
= –100 µA
= –24 mA
= –100 µA
4.5 V
4.5 V
4.5 V
3 V
OH
OH
OH
V
V
OHA
3 V
3 V
3.76
2.9
2.7 V
3 V
2.2
I
= –12 mA
4.5 V
OH
2.46
2.1
2.85
2.3
V
V
OHB
2.7 V
3 V
I
= –24 mA
4.5 V
2.25
3.76
2.65
4.25
OH
4.5 V
3 V
I
I
I
I
= 100 µA
= 24 mA
= 100 µA
= 12 mA
4.5 V
4.5 V
4.5 V
4.5 V
0.1
0.44
0.1
0.44
0.5
0.44
0.44
±1
OL
OL
OL
OL
V
V
V
V
OLA
3 V
0.21
3 V
2.7 V
2.7 V
3 V
0.11
0.22
0.21
0.18
±0.1
±0.1
±0.5
8
OLB
I
= 24 mA
4.5 V
OL
4.5 V
3.6 V
5.5 V
3.6 V
Open
3.6 V
5.5 V
3.6 V
5.5 V
I
I
Control inputs V = V or GND
CCA
5.5 V
µA
µA
I
I
±1
†
V
A
= V
or GND,
CCA/B
or GND
V = V or V
5.5 V
5.5 V
±5
A or B ports
B to A
O
I
IL
IH
OZ
= V
80
n
CC
I
8
80
µA
µA
CCA
I
= 0,
B
n
= V or GND
CCB
5.5 V
5.5 V
O(A port)
8
80
5
50
I
A to B
A port
A
= V
or GND,
I
= 0
CCB
n
CCA
O (B port)
8
80
V = V
– 2.1 V, Other inputs at V
or GND,
or GND,
or GND,
or GND,
I
CCA
CCA
CCA
CCA
CCB
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
3.6 V
3.6 V
1.35
1
1.5
1.5
1.5
0.5
OE at GND and DIR at V
CCA
V = V
DIR at V
– 2.1 V, Other inputs at V
I
CCA
‡
‡
mA
mA
∆I
∆I
OE
CCA
or GND
CCA
– 2.1 V, Other inputs at V
or GND
CCA
– 0.6 V, Other inputs at V
V = V
OE at V
I
CCA
DIR
1
V = V
I
CCB
B port
0.35
CCB
OE at GND and DIR at GND
C
C
Control inputs V = V
or GND
Open
5 V
Open
3.3 V
5
pF
pF
i
I
CCA
= V
A or B ports
V
O
or GND
11
io
CCA/B
†
‡
For I/O ports, the parameter I
includes the input leakage current.
OZ
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or the associated V
.
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCC4245A
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS584F – NOVEMBER 1996 – REVISED AUGUST 1998
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figures 1 through 4)
V
V
= 5 V
V
= 5 V
CCA
± 0.5 V,
CCA
± 0.5 V,
V = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
= 5 V
± 0.5 V
CCB
CCB
TO 3.6 V
PARAMETER
UNIT
MIN
1
MAX
7.1
6
MIN
1
MAX
7
t
t
t
t
t
t
t
t
t
t
t
t
PHL
PLH
PHL
PLH
PZL
PZH
PZL
PZH
PLZ
PHZ
PLZ
PHZ
A
B
A
A
B
A
B
ns
ns
ns
ns
ns
ns
1
1
7
1
6.8
6.1
9
1
6.2
5.3
9
B
1
1
1
1
OE
OE
OE
OE
1
8.3
8.2
8.1
4.7
4.9
5.4
6.3
1
8
1
1
10
10.2
5.2
5.2
5.4
7.4
1
1
1
1
1
1
1
1
1
1
operating characteristics, V
= 5 V, V
= 3.3 V, T = 25°C
CCA
CCB
A
PARAMETER
TEST CONDITIONS
= 0, f = 10 MHz
TYP
20
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per transceiver
C
pF
pd
L
6.5
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCC4245A
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS584F – NOVEMBER 1996 – REVISED AUGUST 1998
PARAMETER MEASUREMENT INFORMATION FOR A TO B
V
= 4.5 V TO 5.5 V AND V
= 2.7 V TO 3.6 V
CCA
CCB
6 V
S1
Open
GND
500 Ω
From Output
Under Test
TEST
S1
C
= 50 pF
L
t
/t
Open
6 V
PLH PHL
500 Ω
(see Note A)
t
/t
PLZ PZL
t
/t
GND
PHZ PZH
LOAD CIRCUIT
t
w
3 V
0 V
1.5 V
1.5 V
Input
3 V
0 V
Output
Control
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
t
PLZ
Output
Waveform 1
S1 at 6 V
3 V
3 V
1.5 V
V
V
+ 0.3 V
– 0.3 V
OL
1.5 V
1.5 V
Input
V
OL
(see Note B)
0 V
V
t
PHZ
t
t
PZH
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
OH
OH
1.5 V
Output
1.5 V
1.5 V
0 V
(see Note B)
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCC4245A
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS584F – NOVEMBER 1996 – REVISED AUGUST 1998
PARAMETER MEASUREMENT INFORMATION FOR A TO B
V
= 4.5 V TO 5.5 V AND V
= 3.6 V TO 5.5 V
CCA
CCB
7 V
S1
Open
GND
500 Ω
From Output
Under Test
TEST
S1
C
= 50 pF
L
t
/t
Open
7 V
PLH PHL
500 Ω
(see Note A)
t
/t
PLZ PZL
t
/t
GND
PHZ PZH
LOAD CIRCUIT
t
w
3 V
0 V
1.5 V
1.5 V
Input
3 V
0 V
Output
Control
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
3 V
1.5 V
V
V
+ 0.3 V
– 0.3 V
OL
1.5 V
1.5 V
Input
V
OL
(see Note B)
0 V
V
t
PHZ
t
t
PZH
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
OH
OH
1.5 V
Output
1.5 V
1.5 V
0 V
(see Note B)
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCC4245A
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS584F – NOVEMBER 1996 – REVISED AUGUST 1998
PARAMETER MEASUREMENT INFORMATION FOR B TO A
V
= 4.5 V TO 5.5 V AND V
= 2.7 V TO 3.6 V
CCA
CCB
2 × V
CCA
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
/t
PLH PHL
Open
C
= 50 pF
L
500 Ω
t
/t
2 × V
CCA
GND
(see Note A)
PLZ PZL
t /t
PHZ PZH
LOAD CIRCUIT
t
w
3 V
0 V
1.5 V
1.5 V
Input
3 V
0 V
Output
Control
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
t
PLZ
Output
Waveform 1
V
V
CCA
3 V
1.5 V
PHZ
V
V
+ 0.3 V
– 0.3 V
S1 at 2 × V
OL
1.5 V
1.5 V
CCA
Input
OL
(see Note B)
0 V
V
t
t
t
PZH
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
OH
OH
1.5 V
Output
1.5 V
1.5 V
0 V
(see Note B)
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 3. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCC4245A
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS584F – NOVEMBER 1996 – REVISED AUGUST 1998
PARAMETER MEASUREMENT INFORMATION FOR B TO A
V
= 4.5 V TO 5.5 V AND V
= 3.6 V TO 5.5 V
CCA
CCB
2 × V
CCA
Open
S1
500 Ω
From Output
Under Test
GND
TEST
S1
C
= 50 pF
L
t
/t
Open
PLH PHL
500 Ω
(see Note A)
t
/t
2 × V
CCA
GND
PLZ PZL
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CCB
Input
V
/2
V
CCB
/2
CCB
3 V
0 V
0 V
Output
Control
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
t
PLZ
Output
Waveform 1
V
V
CCA
V
CCB
1.5 V
PHZ
V
V
+ 0.3 V
– 0.3 V
S1 at 2 × V
OL
V
CCB
/2
V
CCB
/2
CCA
Input
OL
(see Note B)
0 V
V
t
t
t
PZH
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
OH
OH
1.5 V
Output
1.5 V
1.5 V
0 V
(see Note B)
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 4. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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Copyright 1998, Texas Instruments Incorporated
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