SN74LVCH16245AZQLR [TI]
16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS; 具有三态输出的16位总线收发器
| 型号： | SN74LVCH16245AZQLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS |
| 文件： | 总17页 (文件大小：464K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVCH16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES495B–OCTOBER 2003–REVISED AUGUST 2006
FEATURES
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
•
Member of the Texas Instruments Widebus™
Family
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
•
•
•
•
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4 ns at 3.3 V
2
3
4
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
5
6
•
•
Typical VOHV (Output VOH Undershoot) >2 V at
VCC = 3.3 V, TA = 25°C
7
V
CC
V
CC
8
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
9
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
3.3-V VCC
)
•
•
•
•
Ioff Supports Partial-Power-Down Mode
Operation
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
V
CC
V
CC
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
2B5
2B6
GND
2B7
2B8
2DIR
2A5
2A6
GND
2A7
2A8
2OE
DESCRIPTION/ORDERING
INFORMATION
This 16-bit (dual-octal) noninverting bus transceiver
is designed for 1.65-V to 3.6-V VCC operation.
This device can be used as two 8-bit transceivers or one 16-bit transceiver.
The SN74LVCH16245A is designed for asynchronous communication between data buses. The logic levels of
the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port
outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to
the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are
activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level
applied to prevent excess ICC and ICCZ
.
Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input circuit and is
not disabled by OE or DIR.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVCH16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES495B–OCTOBER 2003–REVISED AUGUST 2006
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
FBGA – GRD
SN74LVCH16245AGRDR
SN74LVCH16245AZRDR
SN74LVCH16245ADL
Tape and reel
Tube
LDH245A
FBGA – ZRD (Pb-free)
SSOP – DL
SN74LVCH16245ADLR
74LVCH16245ADLRG4
SN74LVCH16245ADGGR
74LVCH16245ADGGRG4
SN74LVCH16245ADGVR
74LVCH16245ADGVRE4
SN74LVCH16245AGQLR
SN74LVCH16245AZQLR
LVCH16245A
Tape and reel
–40°C to 85°C
TSSOP – DGG
TVSOP – DGV
Tape and reel
Tape and reel
Tape and reel
LVCH16245A
LDH245A
VFBGA – GQL
LDH245A
VFBGA – ZQL (Pb-free)
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
GQL OR ZQL PACKAGE
TERMINAL ASSIGNMENTS(1)
(56-Ball GQL/ZQL Package)
(TOP VIEW)
1
2 3 4 5 6
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
A
B
C
D
E
F
1DIR
1B2
1B4
1B6
1B8
2B1
2B3
2B5
2B7
2DIR
NC
NC
NC
NC
1OE
1A2
1A4
1A6
1A8
2A1
2A3
2A5
2A7
2OE
1B1
1B3
1B5
1B7
2B2
2B4
2B6
2B8
NC
GND
VCC
GND
GND
VCC
GND
1A1
1A3
1A5
1A7
2A2
2A4
2A6
2A8
NC
G
H
J
GND
VCC
GND
NC
GND
VCC
GND
NC
K
K
abc
abc
(1) NC – No internal connection
GRD OR ZRD PACKAGE
(TOP VIEW)
TERMINAL ASSIGNMENTS(1)
(54-Ball GRD/ZRD Package)
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1B1
1B3
1B5
1B7
2B1
2B3
2B5
2B7
2B8
NC
1DIR
NC
1OE
NC
NC
1A1
1A3
1A5
1A7
2A1
2A3
2A5
2A7
2A8
A
B
C
D
1B2
1B4
1B6
1B8
2B2
2B4
2B6
NC
1A2
1A4
1A6
1A8
2A2
2A4
2A6
NC
VCC
GND
GND
GND
VCC
NC
VCC
GND
GND
GND
VCC
NC
E
F
G
H
J
G
H
J
2DIR
2OE
(1) NC – No internal connection
2
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SN74LVCH16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES495B–OCTOBER 2003–REVISED AUGUST 2006
FUNCTION TABLE(1)
(EACH 8-BIT SECTION)
CONTROL INPUTS
OUTPUT CIRCUITS
OPERATION
OE
L
DIR
L
A PORT
Enabled
Hi-Z
B PORT
Hi-Z
B data to A bus
A data to B bus
Isolation
L
H
Enabled
Hi-Z
H
X
Hi-Z
(1) Input circuits of the data I/Os always are active.
LOGIC DIAGRAM (POSITIVE LOGIC)
24
1
2DIR
1DIR
48
25
13
1OE
2OE
2B1
36
47
1A1
2A1
2
1B1
To Seven Other Channels
To Seven Other Channels
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
6.5
6.5
6.5
V
VO
VO
IIK
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–50
–50
±50
±100
70
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through each VCC or GND
DGG package
DGV package
58
θJA
Package thermal impedance(4)
DL package
63
°C/W
GQL/ZQL package
GRD/ZRD package
42
36
Tstg
Storage temperature range
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
3
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SN74LVCH16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES495B–OCTOBER 2003–REVISED AUGUST 2006
Recommended Operating Conditions(1)
MIN
MAX UNIT
Operating
1.65
3.6
V
VCC
Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
1.5
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
0.35 × VCC
0.7
VIL
Low-level input voltage
V
0.8
5.5
VCC
5.5
–4
–8
–12
–24
4
VI
Input voltage
0
0
0
V
V
High or low state
3-state
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
IOH
High-level output current
Low-level output current
mA
mA
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
8
IOL
12
24
5
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
TA
–40
85
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SN74LVCH16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES495B–OCTOBER 2003–REVISED AUGUST 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
1.65 V
2.3 V
MIN TYP(1)
VCC – 0.2
MAX UNIT
IOH = –100 µA
IOH = –4 mA
IOH = –8 mA
1.2
1.7
2.2
2.4
2.2
VOH
V
2.7 V
IOH = –12 mA
3 V
IOH = –24 mA
IOL = 100 µA
IOL = 4 mA
3 V
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
VOL
IOL = 8 mA
0.7
0.4
V
IOL = 12 mA
IOL = 24 mA
2.7 V
3 V
0.55
±5
II
Control inputs VI = 0 to 5.5 V
VI = 0.58 V
3.6 V
µA
15
–15
45
1.65 V
2.3 V
3 V
VI = 1.07 V
VI = 0.7 V
II(hold) A or B port
VI = 1.7 V
–45
75
µA
VI = 0.8 V
VI = 2 V
–75
VI = 0 to 3.6 V(2)
3.6 V
0
±500
±10
±5
Ioff
VI or VO = 5.5 V
µA
µA
(3)
IOZ
VO = 0 V or (VCC to 5.5 V)
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V(4)
2.3 V to 3.6 V
20
ICC
IO = 0
3.6 V
µA
20
∆ICC
One input at VCC – 0.6 V, Other inputs at VCC or GND
2.7 V to 3.6 V
3.3 V
500
µA
pF
pF
Ci
Control inputs VI = VCC or GND
5
Cio
A or B port
VO = VCC or GND
3.3 V
7.5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This is the bus-hold maximum dynamic current required to switch the input from one state to another.
(3) For the total leakage current in an I/O port, consult the II(hold) specification for the input voltage condition 0 V < VI < VCC, and the IOZ
specification for the input voltage conditions VI = 0 V or VI = VCC to 5.5 V. The bus-hold current, at input voltage greater than VCC, is
negligible.
(4) This applies in the disabled state only.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.5
1.5
1.5
MAX
MIN
1
MAX
MIN
1
MAX
MIN
1
MAX
tpd
ten
A or B
OE
B or A
A or B
A or B
7.1
8.9
4.5
5.6
6.8
4.7
6.7
7.1
4
5.5
6.6
1
ns
ns
ns
ns
1
1.5
1.5
1.5
1.5
tdis
OE
11.9
1
tsk(o)
5
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SN74LVCH16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES495B–OCTOBER 2003–REVISED AUGUST 2006
Operating Characteristics
TA = 25°C
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
36
3
TYP
36
3
TYP
40
4
Outputs enabled
Outputs disabled
Power dissipation capacitance
per transceiver
Cpd
f = 10 MHz
pF
6
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SN74LVCH16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES495B–OCTOBER 2003–REVISED AUGUST 2006
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
V
R
L
PLZ PZL
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
V
V
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
/2
/2
2 × V
2 × V
6 V
6 V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
V
CC
CC
CC
1.5 V
1.5 V
3.3 V ± 0.3 V
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
V
M
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
LOAD
V
OL
+ V
∆
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
− V
∆
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
74LVCH16245ADGGRG4
74LVCH16245ADGVRE4
74LVCH16245ADLRG4
SN74LVCH16245ADGGR
SN74LVCH16245ADGVR
SN74LVCH16245ADL
TSSOP
DGG
48
48
48
48
48
48
48
48
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
SSOP
TSSOP
TVSOP
SSOP
SSOP
SSOP
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGG
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVCH16245ADLG4
SN74LVCH16245ADLR
SN74LVCH16245AGQLR
DL
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
GQL
1000
TBD
SNPB
Level-1-240C-UNLIM
Level-1-240C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
SN74LVCH16245AGRDR
SN74LVCH16245AZQLR
SN74LVCH16245AZRDR
ACTIVE
ACTIVE
ACTIVE
BGA MI
CROSTA
R JUNI
OR
GRD
ZQL
ZRD
54
56
54
1000
TBD
SNPB
BGA MI
CROSTA
R JUNI
OR
1000 Green (RoHS &
no Sb/Br)
SNAGCU
SNAGCU
BGA MI
CROSTA
R JUNI
OR
1000 Green (RoHS &
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
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Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
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Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Low Power Wireless www.ti.com/lpw
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2006, Texas Instruments Incorporated
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