SN74LVCH16646A_V01 [TI]
16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS;
| 型号： | SN74LVCH16646A_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS 输出元件 |
| 文件： | 总17页 (文件大小：1088K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS318K–NOVEMBER 1993–REVISED MARCH 2005
FEATURES
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
•
Member of the Texas Instruments Widebus™
Family
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1DIR
1CLKAB
1SAB
GND
1OE
•
•
•
•
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 5.7 ns at 3.3 V
2
1CLKBA
1SBA
GND
1B1
3
4
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
5
1A1
1A2
6
1B2
•
•
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
7
V
CC
V
CC
8
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
9
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
With 3.3-V VCC
)
•
•
•
•
Ioff Supports Partial-Power-Down Mode
Operation
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
V
CC
V
CC
– 1000-V Charged-Device Model (C101)
2A7
2A8
2B7
2B8
DESCRIPTION/ORDERING INFORMATION
GND
GND
2SBA
2CLKBA
2OE
This 16-bit bus transceiver and register is designed
for 1.65-V to 3.6-V VCC operation.
2SAB
2CLKAB
2DIR
The SN74LVCH16646A can be used as two 8-bit
transceivers or one 16-bit transceiver. The device
consists of bus transceiver circuits, D-type flip-flops,
and control circuitry arranged for multiplexed
transmission of data directly from the input bus or
from the internal registers.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74LVCH16646ADL
TOP-SIDE MARKING
Tube
SSOP – DL
LVCH16646A
Tape and reel
Tape and reel
Tape and reel
SN74LVCH16646ADLR
SN74LVCH16646ADGGR
SN74LVCH16646ADGVR
–40°C to 85°C
TSSOP – DGG
TVSOP – DGV
LVCH16646A
LDH646A
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1993–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS318K–NOVEMBER 1993–REVISED MARCH 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB
or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with
the SN74LVCH16646A.
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode,
data present at the high-impedance port can be stored in either register or in both. The select-control (SAB and
SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control
eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and
real-time data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high), A data
can be stored in one register and/or B data can be stored in the other register.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
When an output function is disabled, the input function still is enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
FUNCTION TABLE
INPUTS
DATA I/O(1)
OPERATION OR FUNCTION
OE
X
X
H
H
L
DIR
X
CLKAB
CLKBA
SAB
X
SBA
X
A1–A8
Input
B1–B8
↑
X
Unspecified
Input
Store A, B unspecified(1)
Store B, A unspecified(1)
Store A and B data
X
X
↑
X
X
Unspecified
Input
X
↑
H or L
X
↑
H or L
X
X
X
Input
X
X
X
Input
Input
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B Bus
Stored A data to bus
L
X
L
Output
Output
Input
Input
L
L
X
H or L
X
X
H
Input
L
H
H
X
L
X
Output
Output
L
H or L
X
H
X
Input
(1) The data-output functions can be enabled or disabled by various signals at OE or DIR. Data-input functions always are enabled, i.e.,
data at the bus terminals is stored on every low-to-high transition of the clock inputs.
2
SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS318K–NOVEMBER 1993–REVISED MARCH 2005
DIR CLKAB CLKBA SAB
SBA
L
DIR
H
CLKAB CLKBA SAB
SBA
X
OE
L
OE
L
L
X
X
X
X
X
L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
DIR CLKAB CLKBA SAB
SBA
X
DIR
L
CLKAB CLKBA SAB
SBA
H
OE
X
OE
L
X
H or L
X
X
H
X
X
X
X
↑
X
X
X
↑
X
L
H
H or L
X
X
X
H
X
↑
↑
TRANSFER STORED DATA
TO A AND/OR B
STORAGE FROM
A, B, OR A AND B
Figure 1. Bus-Management Functions
3
SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS318K–NOVEMBER 1993–REVISED MARCH 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
56
1OE
1
1DIR
1CLKBA
1SBA
55
54
2
1CLKAB
3
1SAB
One of Eight Channels
1D
C1
5
1A1
52
1B1
1D
C1
To Seven Other Channels
29
2OE
28
30
31
27
2DIR
2CLKBA
2SBA
2CLKAB
26
2SAB
One of Eight Channels
1D
C1
15
2A1
42
2B1
1D
C1
To Seven Other Channels
4
SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS318K–NOVEMBER 1993–REVISED MARCH 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
MAX
6.5
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
6.5
V
VO
VO
IIK
6.5
V
VCC + 0.5
–50
V
Input clamp current
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
–50
Continuous output current
Continuous current througheach VCC or GND
±50
±100
64
DGG package
DGV package
DL package
θJA
Package thermal impedance(4)
48
°C/W
°C
56
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
MAX UNIT
Operating
1.65
3.6
V
VCC
Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
1.5
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
0.35 × VCC
0.7
VIL
Low-level input voltage
V
0.8
5.5
VCC
5.5
–4
VI
Input voltage
0
0
0
V
V
High or low state
3-state
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
–8
IOH
High-level output current
Low-level output current
mA
mA
–12
–24
4
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
8
IOL
12
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10
ns/V
TA
–40
85
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS318K–NOVEMBER 1993–REVISED MARCH 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
1.65 V
2.3 V
MIN TYP(1) MAX
VCC – 0.2
UNIT
IOH = –100 µA
IOH = –4 mA
IOH = –8 mA
1.2
1.7
2.2
2.4
2.2
VOH
V
2.7 V
IOH = –12 mA
3 V
IOH = –24 mA
IOL = 100 µA
IOL = 4 mA
3 V
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.7
VOL
IOL = 8 mA
V
IOL = 12 mA
IOL = 24 mA
2.7 V
0.4
3 V
0.55
±5
II
Control inputs VI = 0 to 5.5 V
VI = 0.58 V
3.6 V
µA
(2)
(2)
1.65 V
2.3 V
3 V
VI = 1.07 V
VI = 0.7 V
45
–45
75
II(hold)
A or B ports
VI = 1.7 V
µA
VI = 0.8 V
VI = 2 V
–75
VI = 0 to 3.6 V(3)
VI or VO = 5.5 V
VO = 0 to 5.5 V
VI = VCC or GND
3..6 V
0
±500
±10
±10
20
Ioff
µA
µA
(4)
IOZ
3.6 V
ICC
IO = 0
3.6 V
µA
3.6 V ≤ VI ≤ 5.5 V(5)
One input at VCC – 0.6 V, Other inputs at VCC or GND
Control inputs VI = VCC or GND
A or B ports VO = VCC or GND
20
∆ICC
Ci
2.7 V to 3.6 V
3.3 V
500
µA
pF
pF
5
Cio
3.3 V
8.5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This information was not available at the time of publication.
(3) This is the bus-hold maximum dynamic current required to switch the input from one state to another.
(4) For I/O ports, the parameter IOZ includes the input leakage current, but not II(hold)
.
(5) This applies in the disabled state only.
Timing Requirements
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
150
MIN
MAX
150
(1)
(1)
fclock
tw
Clock frequency
MHz
ns
(1)
(1)
(1)
(1)
(1)
(1)
Pulse duration, CLK high or low
Setup time, A or B before CLKAB↑ or CLKBA↑
Hold time, A or B after CLKAB↑ or CLKBA↑
3.3
3.2
0
3.3
2.9
0.3
tsu
th
ns
ns
(1) This information was not available at the time of publication.
6
SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS318K–NOVEMBER 1993–REVISED MARCH 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
150
1.3
1.8
1.7
1.3
2.1
1.4
2
MAX
(1)
(1)
fmax
150
MHz
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
A or B
B or A
A or B
6.8
7.9
9.2
8.5
7.7
8.5
7.8
5.7
6.7
7.7
6.9
6.9
7.2
7
tpd
CLKAB or CLKBA
SAB or SBA
ns
ten
tdis
ten
tdis
OE
A or B
A or B
ns
ns
DIR
(1) This information was not available at the time of publication.
Operating Characteristics
TA = 25°C
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
TYP
TYP
60
(1)
(1)
Outputs enabled
Outputs disabled
Power dissipation capacitance
per transceiver
Cpd
f = 10 MHz
pF
(1)
(1)
12
(1) This information was not available at the time of publication.
7
SN74LVCH16646A
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS318K–NOVEMBER 1993–REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
V
R
L
PLZ PZL
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
V
V
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
/2
/2
2 × V
2 × V
6 V
6 V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
V
CC
CC
CC
1.5 V
1.5 V
3.3 V ± 0.3 V
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
V
M
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
LOAD
V
OL
+ V
∆
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
− V
∆
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
8
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74LVCH16646ADGGR
SN74LVCH16646ADL
SN74LVCH16646ADLR
ACTIVE
ACTIVE
ACTIVE
TSSOP
SSOP
SSOP
DGG
DL
56
56
56
2000 RoHS & Green
20 RoHS & Green
1000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
LVCH16646A
NIPDAU
NIPDAU
LVCH16646A
LVCH16646A
DL
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVCH16646ADGGR TSSOP
SN74LVCH16646ADLR SSOP
DGG
DL
56
56
2000
1000
330.0
330.0
24.4
32.4
8.6
15.6
1.8
3.1
12.0
16.0
24.0
32.0
Q1
Q1
11.35 18.67
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2017
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVCH16646ADGGR
SN74LVCH16646ADLR
TSSOP
SSOP
DGG
DL
56
56
2000
1000
367.0
367.0
367.0
367.0
45.0
55.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGG0056A
TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
2
0
0
SMALL OUTLINE PACKAGE
C
8.3
7.9
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
54X 0.5
56
1
14.1
13.9
NOTE 3
2X
13.5
28
B
29
0.27
0.17
6.2
6.0
56X
1.2 MAX
0.08
C A
B
(0.15) TYP
0.25
GAGE PLANE
0 - 8
SEE DETAIL A
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4222167/A 07/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05)
TYP
SYMM
28
29
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222167/A 07/2015
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05) TYP
SYMM
28
29
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4222167/A 07/2015
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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