SN74LVCH244ADWE4 [TI]
OCTAL BUFFERS/DRIVERS OCTAL BUFFERS/DRIVERS; 八路缓冲器/驱动八路缓冲器/驱动器
| 型号： | SN74LVCH244ADWE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL BUFFERS/DRIVERS OCTAL BUFFERS/DRIVERS |
| 文件： | 总23页 (文件大小：665K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LVCH244A, SN74LVCH244A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCES009O–JULY 1995–REVISED FEBRUARY 2007
FEATURES
•
•
•
•
Operate From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 5.9 ns at 3.3 V
•
•
•
•
Ioff Supports Partial-Power-Down Mode
Operation
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Latch-Up Performance Exceeds 250 mA Per
JESD 17
•
•
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
ESD Protection Exceeds JESD 22
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
Support Mixed-Mode Signal Operation on All
Ports
(5-V Input/Output Voltage With 3.3-V VCC
)
1000-V Charged-Device Model (C101)
SN54LVCH244A . . . J OR W PACKAGE
SN74LVCH244A . . . DB, DBQ, DGV, DW,
NS, OR PW PACKAGE
SN74LVCH244A . . . RGY PACKAGE
(TOP VIEW)
SN54LVCH244A . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
1
20
3
9
2
1
20 19
18
1Y1
2A4
1Y2
2A3
1Y3
1A2
2Y3
1A3
2Y2
1A4
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
4
5
6
7
8
19
18
17
16
15
14
13
12
2
3
4
5
6
7
8
9
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
17
16
15
14
10 11 12 13
10
11
DESCRIPTION/ORDERING INFORMATION
The SN54LVCH244A octal buffer/line driver is designed for 2.7-V to 3.6-V VCC operation, and the
SN74LVCH244A octal buffer/line driver is designed for 1.65-V to 3.6-V VCC operation.
These devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low,
these devices pass data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN54LVCH244A, SN74LVCH244A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCES009O–JULY 1995–REVISED FEBRUARY 2007
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
QFN – RGY
SOIC – DW
Reel of 1000
Tube of 25
SN74LVCH244ARGYR
SN74LVCH244ADW
SN74LVCH244ADWR
SN74LVCH244ANSR
SN74LVCH244ADBR
SN74LVCH244ADBQR
SN74LVCH244APW
SN74LVCH244APWR
SN74LVCH244APWT
SN74LVCH244ADGVR
SNJ54LVCH244AJ
LCH244A
LVCH244A
Reel of 2000
Reel of 2000
Reel of 2000
Reel of 2500
Tube of 70
SOP – NS
LVCH244A
LCH244A
SSOP – DB
–40°C to 85°C
SSOP (QSOP) – DBQ
LVCH244A
TSSOP – PW
Reel of 2000
Reel of 250
Reel of 2000
Tube of 20
LCH244A
TVSOP – DGV
CDIP – J
LCH244A
SNJ54LVCH244AJ
SNJ54LVCH244AW
SNJ54LVCH244AFK
–55°C to 125°C
CFP – W
Tube of 85
SNJ54LVCH244AW
SNJ54LVCH244AFK
LCCC – FK
Tube of 55
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(EACH BUFFER)
INPUTS
OUTPUT
Y
OE
L
A
H
L
H
L
L
H
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
1
2
19
1OE
1A1
2OE
18
16
14
12
11
13
15
17
9
7
5
3
1Y1
1Y2
1Y3
1Y4
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
4
6
8
1A2
1A3
1A4
2
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SN54LVCH244A, SN74LVCH244A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCES009O–JULY 1995–REVISED FEBRUARY 2007
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
6.5
6.5
6.5
V
V
VO
VO
IIK
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–50
–50
±50
±100
70
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
DB package(4)
DBQ package(4)
DGV package(4)
DW package(4)
NS package(4)
PW package(4)
RGY package(5)
68
92
θJA
Package thermal impedance
58 °C/W
60
83
37
Tstg
Storage temperature range
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) The package thermal impedance is calculated in accordance with JESD 51-5.
3
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SN54LVCH244A, SN74LVCH244A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCES009O–JULY 1995–REVISED FEBRUARY 2007
Recommended Operating Conditions(1)
SN54LVCH244A
SN74LVCH244A
UNIT
MIN
2
MAX
MIN
MAX
Operating
3.6
1.65
3.6
VCC
Supply voltage
V
V
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
1.5
1.5
0.65 × VCC
VIH
High-level input voltage
1.7
2
2
0.35 × VCC
0.7
0.8
5.5
VCC
5.5
–4
VIL
Low-level input voltage
V
0.8
5.5
VI
Input voltage
0
0
0
0
0
0
V
V
High or low state
3-state
VCC
5.5
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
–8
IOH
High-level output current
Low-level output current
mA
mA
–12
–24
–12
–24
4
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
8
IOL
12
24
12
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10
10
ns/V
TA
–55
125
–40
85
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SN54LVCH244A, SN74LVCH244A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCES009O–JULY 1995–REVISED FEBRUARY 2007
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
SN54LVCH244A
MIN TYP(1) MAX
SN74LVCH244A
MIN TYP(1) MAX
PARAMETER
TEST CONDITIONS
VCC
UNIT
1.65 V to 3.6 V
2.7 V to 3.6 V
1.65 V
VCC – 0.2
IOH = –100 µA
VCC – 0.2
IOH = –4 mA
IOH = –8 mA
1.2
1.7
2.2
2.4
2.2
VOH
2.3 V
V
2.7 V
2.2
2.4
2.2
IOH = –12 mA
IOH = –24 mA
IOL = 100 µA
3 V
3 V
1.65 V to 3.6 V
2.7 V to 3.6 V
1.65 V
0.2
0.2
IOL = 4 mA
0.45
0.7
VOL
V
IOL = 8 mA
2.3 V
IOL = 12 mA
2.7 V
0.4
0.55
±5
0.4
IOL = 24 mA
3 V
0.55
±5
II
VI = 0 to 5.5 V
VI or VO = 5.5 V
VI = 0.58 V
3.6 V
µA
µA
Ioff
0
±10
(2)
(2)
1.65 V
2.3 V
3 V
VI = 1.07 V
VI = 0.7 V
45
–45
75
II(hold)
VI = 1.7 V
µA
VI = 0.8 V
75
VI = 2 V
–75
–75
VI = 0 to 3.6 V(3)
VO = 0 to 5.5 V
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V(4)
One input at VCC – 0.6 V,
3..6 V
3.6 V
±500
±15
10
±500
±10
10
IOZ
ICC
µA
µA
IO = 0
3.6 V
10
10
∆ICC
2.7 V to 3.6 V
500
500
µA
Other inputs at VCC or GND
Ci
VI = VCC or GND
3.3 V
3.3 V
4
12
12
4
pF
pF
Co
VO = VCC or GND
5.5
5.5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This information was not available at the time of publication.
(3) This is the bus-hold maximum dynamic current required to switch the input from one state to another.
(4) This applies in the disabled state only.
5
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SN54LVCH244A, SN74LVCH244A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCES009O–JULY 1995–REVISED FEBRUARY 2007
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN54LVCH244A
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
PARAMETER
VCC = 2.7 V
UNIT
MIN MAX
MIN MAX
tpd
ten
tdis
A
Y
Y
Y
7.5
9
1
1
1
6.5
8
ns
ns
ns
OE
OE
8
7
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVCH244A
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
PARAMETER
VCC = 2.7 V
UNIT
MIN MAX
MIN
MAX
MIN MAX MIN
MAX
5.9
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
tpd
ten
tdis
A
Y
Y
Y
6.9
8.6
6.8
1.5
1
ns
ns
ns
(1)
(1)
OE
OE
7.6
1.5
5.8
(1) This information was not available at the time of publication.
Operating Characteristics
TA = 25°C
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
TYP
TYP
47
2
(1)
(1)
Outputs enabled
Outputs disabled
Power dissipation capacitance
per buffer/driver
Cpd
f = 10 MHz
pF
(1)
(1)
(1) This information was not available at the time of publication.
6
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SN54LVCH244A, SN74LVCH244A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCES009O–JULY 1995–REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
V
R
L
PLZ PZL
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
V
V
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
/2
/2
2 × V
2 × V
6 V
6 V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
V
CC
CC
CC
1.5 V
1.5 V
3.3 V ± 0.3 V
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
LOAD
V
OL
+ V
∆
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
− V
∆
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
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PACKAGE OPTION ADDENDUM
www.ti.com
26-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-9754201Q2A
5962-9754201QRA
5962-9754201QSA
5962-9754201V2A
5962-9754201VRA
5962-9754201VSA
SN74LVCH244ADBLE
SN74LVCH244ADBQR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
ACTIVE
FK
J
20
20
20
20
20
20
20
20
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
W
LCCC
CDIP
CFP
FK
J
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
Call TI
W
SSOP
DB
DBQ
Call TI
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SN74LVCH244ADBQRE4
SN74LVCH244ADBQRG4
SN74LVCH244ADBR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP/
QSOP
DBQ
DBQ
DB
20
20
20
20
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVCH244ADBRE4
SSOP
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVCH244ADBRG4
SN74LVCH244ADGVR
ACTIVE
ACTIVE
SSOP
DB
20
20
2000
TBD
Call TI
Call TI
TVSOP
DGV
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVCH244ADGVRE4
SN74LVCH244ADGVRG4
SN74LVCH244ADW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TVSOP
TVSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SO
DGV
DGV
DW
DW
DW
DW
DW
DW
NS
20
20
20
20
20
20
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVCH244ADWE4
SN74LVCH244ADWG4
SN74LVCH244ADWR
SN74LVCH244ADWRE4
SN74LVCH244ADWRG4
SN74LVCH244ANSR
SN74LVCH244ANSRE4
SN74LVCH244APW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
PW
PW
PW
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVCH244APWE4
SN74LVCH244APWG4
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVCH244APWLE
SN74LVCH244APWR
OBSOLETE TSSOP
ACTIVE TSSOP
PW
PW
20
20
TBD
Call TI
Call TI
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-May-2007
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
no Sb/Br)
SN74LVCH244APWRE4
SN74LVCH244APWRG4
SN74LVCH244APWT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
QFN
PW
PW
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVCH244APWTE4
SN74LVCH244APWTG4
SN74LVCH244ARGYR
SN74LVCH244ARGYRG4
PW
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGY
RGY
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SNJ54LVCH244AFK
SNJ54LVCH244AJ
SNJ54LVCH244AW
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
20
20
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
330
330
180
(mm)
16
SN74LVCH244ADBQR
SN74LVCH244ADBR
SN74LVCH244ADGVR
SN74LVCH244ADWR
SN74LVCH244ANSR
SN74LVCH244APWR
SN74LVCH244ARGYR
DBQ
DB
20
20
20
20
20
20
20
MLA
MLA
MLA
MLA
MLA
MLA
MLA
6.5
8.2
9.0
7.5
2.1
2.5
1.6
2.7
2.5
1.6
1.6
8
12
8
16
16
12
24
24
16
12
Q1
Q1
Q1
Q1
Q1
Q1
Q1
16
DGV
DW
NS
12
7.0
5.6
24
10.8
8.2
13.0
13.0
7.1
12
12
8
24
PW
16
6.95
3.8
RGY
12
4.8
8
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74LVCH244ADBQR
SN74LVCH244ADBR
SN74LVCH244ADGVR
SN74LVCH244ADWR
SN74LVCH244ANSR
SN74LVCH244APWR
SN74LVCH244ARGYR
DBQ
DB
20
20
20
20
20
20
20
MLA
MLA
MLA
MLA
MLA
MLA
MLA
0.0
0.0
0.0
342.9
338.1
333.2
333.2
342.9
190.0
336.6
340.5
333.2
333.2
336.6
212.7
28.58
20.64
31.75
31.75
28.58
31.75
DGV
DW
NS
PW
RGY
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2007
Pack Materials-Page 3
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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