SN74LVCH32373ANMJR [TI]
具有三态输出的 32 位透明 D 型锁存器 | NMJ | 96 | -40 to 85;
| 型号： | SN74LVCH32373ANMJR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有三态输出的 32 位透明 D 型锁存器 | NMJ | 96 | -40 to 85 驱动 锁存器 总线驱动器 总线收发器 |
| 文件： | 总9页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVCH32373A
32-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS618A – OCTOBER 1998 – REVISED JUNE 1999
Member of the Texas Instruments
Widebus Family
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 3.3 V, T = 25°C
CC
A
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Typical V
> 2 V at V
(Output V
Undershoot)
OHV
CC
OH
= 3.3 V, T = 25°C
A
Packaged in Plastic Fine-Pitch Ball Grid
Array Package
Power Off Disables Outputs, Permitting
Live Insertion
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V
)
CC
description
This 32-bit transparent D-type latch is designed for 1.65-V to 3.6-V V
operation.
CC
The SN74LVCH32373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. It can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When
the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs
are latched at the levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVCH32373A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus trademarks of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH32373A
32-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS618A – OCTOBER 1998 – REVISED JUNE 1999
terminal assignments
GKE PACKAGE
(TOP VIEW)
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
6
5
4
3
2
1
1D2
1D1
1LE
1OE
1Q1
1Q2
A
1D4
1D3
GND
GND
1Q3
1Q4
B
1D6
1D5
1D8
1D7
2D2
2D1
2D4
2D3
2D6
2D5
GND
GND
2Q5
2Q6
G
2D7
2D8
2LE
2OE
2Q8
2Q7
H
3D2
3D1
3LE
3D4
3D3
GND
GND
3Q3
3Q4
K
3D6
3D5
3D8
3D7
4D2
4D1
4D4
4D3
4D6
4D5
GND
GND
4Q5
4Q6
R
4D7
4D8
4LE
4OE
4Q8
4Q7
T
V
V
GND GND
GND GND
V
V
V
V
GND GND
GND GND
V
V
CC
CC
CC
CC
3OE
3Q1
3Q2
J
CC
CC
CC
CC
1Q5
1Q6
C
1Q7
1Q8
D
2Q1
2Q2
E
2Q3
2Q4
F
3Q5
3Q6
L
3Q7
3Q8
M
4Q1
4Q2
N
4Q3
4Q4
P
logic diagram (positive logic)
A3
H3
H4
1OE
2OE
2LE
A4
1LE
C1
1D
C1
1D
A2
E2
1Q1
2Q1
A5
E5
1D1
2D1
To Seven Other Channels
To Seven Other Channels
J3
J4
T3
T4
3OE
3LE
4OE
4LE
C1
1D
C1
1D
J2
N2
3Q1
4Q1
J5
N5
3D1
4D1
To Seven Other Channels
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH32373A
32-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS618A – OCTOBER 1998 – REVISED JUNE 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θ (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
IK
I
Output clamp current, I
OK
O
O
Continuous current through each V
CC
JA
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN
1.65
1.5
MAX
UNIT
Operating
3.6
V
Supply voltage
V
CC
IH
Data retention only
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
0.65 × V
1.7
CC
V
High-level input voltage
V
V
2
0.35 × V
0.7
CC
V
IL
Low-level input voltage
0.8
V
V
Input voltage
0
0
0
5.5
V
V
I
High or low state
3 state
V
CC
Output voltage
O
5.5
–4
–8
–12
–24
4
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
I
High-level output current
Low-level output current
mA
mA
OH
OL
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
8
I
12
24
10
85
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
ns/V
T
A
–40
°C
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH32373A
32-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS618A – OCTOBER 1998 – REVISED JUNE 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
–0.2
MAX
UNIT
V
CC
I
I
I
= –100 µA
= –4 mA
= –8 mA
1.65 V to 3.6 V
1.65 V
2.3 V
V
CC
1.2
OH
OH
OH
1.7
2.2
2.4
2.2
V
V
OH
OL
2.7 V
I
= –12 mA
OH
3 V
I
I
I
I
I
I
= –24 mA
= 100 µA
= 4 mA
3 V
OH
OL
OL
OL
OL
OL
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.7
V
= 8 mA
V
= 12 mA
= 24 mA
2.7 V
0.4
3 V
0.55
±5
I
I
V = 0 to 5.5 V
3.6 V
µA
I
I
V = 0.58 V
25
–25
45
I
1.65 V
2.3 V
3 V
V = 1.07 V
I
V = 0.7 V
I
V = 1.7 V
–45
75
µA
I(hold)
I
V = 0.8 V
I
V = 2 V
–75
I
‡
V = 0 to 3.6 V
3.6 V
0
±500
±10
±10
20
I
I
I
V or V = 5.5 V
µA
µA
off
I
O
V
O
= 0 to 5.5 V
3.6 V
OZ
V = V
I
or GND
CC
I
I
O
= 0
3.6 V
µA
CC
§
3.6 V ≤ V ≤ 5.5 V
20
I
∆I
CC
One input at V
– 0.6 V,
Other inputs at V
CC
or GND
2.7 V to 3.6 V
3.3 V
500
µA
pF
pF
CC
or GND
C
C
V = V
5
i
I
CC
= V
V
or GND
3.3 V
6.5
o
O
CC
†
‡
§
All typical values are at V
= 3.3 V, T = 25°C.
CC
A
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This applies in the disabled state only.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
± 0.15 V
CC
± 0.2 V
CC
± 0.3 V
V
= 2.7 V
MAX
CC
UNIT
MIN
MAX
MIN
MAX
MIN
3.3
1.7
1.2
MIN
3.3
1.7
1.2
MAX
¶
¶
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
¶
¶
¶
¶
¶
This information was not available at the time of publication.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH32373A
32-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS618A – OCTOBER 1998 – REVISED JUNE 1999
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
± 0.15 V
CC
± 0.2 V
CC
± 0.3 V
V
= 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
4.9
MIN
1.6
2.1
1.3
2.5
MAX
4.2
†
†
†
†
D
t
pd
Q
ns
†
†
†
†
†
†
†
†
†
†
†
†
LE
OE
OE
5.3
4.6
t
t
Q
Q
5.7
4.7
ns
ns
en
6.3
5.9
dis
†
This information was not available at the time of publication.
operating characteristics, T = 25°C
A
V
= 1.8 V
CC
TYP
V
= 2.5 V
CC
TYP
V = 3.3 V
CC
TEST
CONDITIONS
PARAMETER
UNIT
TYP
†
†
†
†
Outputs enabled
Outputs disabled
39
6
Power dissipation capacitance
per latch
C
f = 10 MHz
pF
pd
†
This information was not available at the time of publication.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH32373A
32-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS618A – OCTOBER 1998 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
= 1.8 V ± 0.15 V
V
CC
2 × V
CC
Open
S1
1 kΩ
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
1 kΩ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH32373A
32-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS618A – OCTOBER 1998 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 2. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCH32373A
32-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS618A – OCTOBER 1998 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
V
= 2.7 V AND 3.3 V ± 0.3 V
CC
6 V
TEST
S1
S1
500 Ω
Open
From Output
Under Test
t
pd
Open
6 V
GND
t
/t
PLZ PZL
/t
t
GND
C
= 50 pF
PHZ PZH
L
500 Ω
(see Note A)
t
w
LOAD CIRCUIT
2.7 V
0 V
1.5 V
1.5 V
Input
2.7 V
Timing
Input
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
2.7 V
Data
Input
Output
Control
(low-level
enabling)
2.7 V
0 V
1.5 V
1.5 V
0 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
3 V
2.7 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
+ 0.3 V
– 0.3 V
OL
V
OL
(see Note B)
t
t
PHZ
PZH
t
t
PHL
PLH
V
OH
Output
Waveform 2
S1 at GND
V
OH
V
OH
1.5 V
Output
1.5 V
1.5 V
0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 3. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
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