SN74LVCR16245ADGGR [TI]
16 BIT BUS TRANSCEIVER WITH 3 STATE OUTPUTS; 具有三态输出16位总线收发器
| 型号： | SN74LVCR16245ADGGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16 BIT BUS TRANSCEIVER WITH 3 STATE OUTPUTS |
| 文件： | 总12页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅꢆꢇ ꢈꢉ ꢊꢃ ꢋꢌ
ꢈ ꢉ ꢍꢎꢏ ꢐ ꢎꢑꢀ ꢐ ꢇꢌꢁ ꢀꢆ ꢒ ꢏꢅ ꢒ ꢇ
ꢓ ꢏꢐ ꢔ ꢕ ꢍꢀꢐꢌꢐ ꢒ ꢖ ꢑꢐ ꢗꢑ ꢐꢀ
SCES427A − FEBRUARY 2003 − REVISED NOVEMBER 2004
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
D
Member of the Texas Instruments
Widebus Family
D
D
D
D
D
D
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
2
Max t of 4.8 ns at 3.3 V
pd
3
4
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
5
= 3.3 V, T = 25°C
A
6
Typical V
(Output V
Undershoot)
OHV
OH
7
V
V
CC
CC
>2 V at V
= 3.3 V, T = 25°C
CC
A
8
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
3.3-V V
)
CC
D
All Inputs and Outputs Have Equivalent
26-Ω Series Resistors, So No External
Resistors Are Required
D
D
D
I
Supports Partial-Power-Down Mode
off
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
V
V
CC
CC
2B5
2B6
GND
2B7
2B8
2A5
2A6
GND
2A7
2A8
2OE
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
description/ordering information
2DIR
This 16-bit (dual-octal) noninverting bus
transceiver is designed for 1.65-V to 3.6-V V
operation.
CC
The SN74LVCR16245A is designed for asynchronous communication between data buses. The
control-function implementation minimizes external-timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the
A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE) input can disable the device so that the buses are effectively isolated.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74LVCR16245ADL
SSOP − DL
LVCR16245A
Tape and reel SN74LVCR16245ADLR
Tape and reel SN74LVCR16245ADGGR
Tape and reel SN74LVCR16245ADGVR
TSSOP − DGG
LVCR16245A
LDR245A
−40°C to 85°C
TVSOP − DGV
VFBGA − GQL
SN74LVCR16245AGQLR
Tape and reel
LDR245A
VFBGA − ZQL (Pb-free)
SN74LVCR16245AZQLR
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
ꢗꢇ ꢖ ꢘꢑ ꢆ ꢐꢏ ꢖ ꢁ ꢘ ꢌꢐꢌ ꢙꢚ ꢛ ꢜꢝ ꢞ ꢟꢠ ꢙꢜꢚ ꢙꢡ ꢢꢣ ꢝ ꢝ ꢤꢚꢠ ꢟꢡ ꢜꢛ ꢥꢣꢦ ꢧꢙꢢ ꢟꢠ ꢙꢜꢚ ꢨꢟ ꢠꢤ ꢩ
ꢗꢝ ꢜ ꢨꢣꢢ ꢠ ꢡ ꢢ ꢜꢚ ꢛꢜ ꢝ ꢞ ꢠ ꢜ ꢡ ꢥꢤ ꢢ ꢙꢛ ꢙꢢꢟ ꢠꢙ ꢜꢚꢡ ꢥꢤ ꢝ ꢠꢪ ꢤ ꢠꢤ ꢝ ꢞꢡ ꢜꢛ ꢐꢤꢫ ꢟꢡ ꢏꢚꢡ ꢠꢝ ꢣꢞ ꢤꢚꢠ ꢡ
ꢡ ꢠ ꢟ ꢚꢨ ꢟ ꢝꢨ ꢬ ꢟ ꢝꢝ ꢟ ꢚ ꢠꢭꢩ ꢗꢝ ꢜ ꢨꢣꢢ ꢠꢙꢜꢚ ꢥꢝ ꢜꢢ ꢤꢡ ꢡꢙ ꢚꢮ ꢨꢜꢤ ꢡ ꢚꢜꢠ ꢚꢤ ꢢꢤ ꢡꢡ ꢟꢝ ꢙꢧ ꢭ ꢙꢚꢢ ꢧꢣꢨ ꢤ
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ
Copyright 2004, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢃꢋ ꢌ
ꢈꢉ ꢍꢎꢏ ꢐ ꢎ ꢑꢀ ꢐ ꢇ ꢌꢁ ꢀꢆ ꢒꢏ ꢅ ꢒꢇ
ꢓꢏ ꢐ ꢔ ꢕ ꢍꢀꢐꢌꢐ ꢒ ꢖꢑꢐ ꢗ ꢑꢐꢀ
SCES427A − FEBRUARY 2003 − REVISED NOVEMBER 2004
description/ordering information (continued)
All outputs, which are designed to sink up to 12 mA, include equivalent 26-W series resistors to reduce
overshoot and undershoot.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator
in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
GQL OR ZQL PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1DIR
1B2
1B4
1B6
1B8
2B1
2B3
2B5
2B7
2DIR
NC
NC
NC
NC
1OE
1A2
1A4
1A6
1A8
2A1
2A3
2A5
2A7
2OE
A
B
C
D
1B1
1B3
1B5
1B7
2B2
2B4
2B6
2B8
NC
GND
GND
1A1
1A3
1A5
1A7
2A2
2A4
2A6
2A8
NC
V
CC
V
CC
GND
GND
E
F
G
H
J
GND
GND
G
H
J
V
CC
V
CC
GND
NC
GND
NC
K
K
NC − No internal connection
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
OE
L
DIR
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
2
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ꢓ ꢏꢐ ꢔ ꢕ ꢍꢀꢐꢌꢐ ꢒ ꢖ ꢑꢐ ꢗꢑ ꢐꢀ
SCES427A − FEBRUARY 2003 − REVISED NOVEMBER 2004
logic diagram (positive logic)
1
24
36
1DIR
2DIR
2A1
48
25
1OE
1B1
2OE
47
1A1
2
13
2B1
To Seven Other Channels
Pin numbers shown are for the DGG, DGV, and DL packages.
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
IK
I
Output clamp current, I
OK
O
O
Continuous current through each V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
GQL/ZQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51-7.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢃꢋ ꢌ
ꢈꢉ ꢍꢎꢏ ꢐ ꢎ ꢑꢀ ꢐ ꢇ ꢌꢁ ꢀꢆ ꢒꢏ ꢅ ꢒꢇ
ꢓꢏ ꢐ ꢔ ꢕ ꢍꢀꢐꢌꢐ ꢒ ꢖꢑꢐ ꢗ ꢑꢐꢀ
SCES427A − FEBRUARY 2003 − REVISED NOVEMBER 2004
recommended operating conditions (see Note 4)
MIN
1.65
1.5
MAX
UNIT
Operating
3.6
V
Supply voltage
V
CC
IH
Data retention only
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
0.65 × V
1.7
CC
V
High-level input voltage
V
V
2
0.35 × V
0.7
CC
V
IL
Low-level input voltage
0.8
V
V
Input voltage
0
0
0
5.5
V
V
I
High or low state
3-state
V
CC
5.5
Output voltage
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
−2
−4
−8
I
High-level output current
Low-level output current
mA
mA
OH
OL
−12
2
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
4
I
8
12
10
85
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
−40
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅꢆꢇ ꢈꢉ ꢊꢃ ꢋꢌ
ꢈ ꢉ ꢍꢎꢏ ꢐ ꢎꢑꢀ ꢐ ꢇꢌꢁ ꢀꢆ ꢒ ꢏꢅ ꢒ ꢇ
ꢓ ꢏꢐ ꢔ ꢕ ꢍꢀꢐꢌꢐ ꢒ ꢖ ꢑꢐ ꢗꢑ ꢐꢀ
SCES427A − FEBRUARY 2003 − REVISED NOVEMBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
MIN TYP
− 0.2
MAX
UNIT
V
CC
I
I
= −100 µA
1.65 V to 3.6 V
1.65 V
2.3 V
V
OH
CC
1.2
= −2 mA
OH
1.7
2.2
2.4
2
I
= −4 mA
OH
2.7 V
V
OH
V
I
I
I
I
I
= −6 mA
= −8 mA
= −12 mA
= 100 µA
= 2 mA
3 V
OH
OH
OH
OL
OL
2.7 V
3 V
2
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.7
0.4
0.55
0.6
0.8
5
I
= 4 mA
OL
2.7 V
V
OL
V
I
I
I
= 6 mA
= 8 mA
= 12 mA
3 V
OL
OL
OL
2.7 V
3 V
I
I
Control inputs V = 0 to 5.5 V
3.6 V
µA
µA
µA
I
I
V or V = 5.5 V
0
10
off
I
O
‡
V
= 0 to 5.5 V
3.6 V
5
I
O
OZ
V = V
CC
or GND,
20
I
I
I
O
= 0
3.6 V
µA
CC
§
3.6 V ≤ V ≤ 5.5 V
20
I
∆I
CC
One input at V
CC
− 0.6 V, Other inputs at V
CC
or GND
2.7 V to 3.6 V
3.3 V
500
µA
pF
pF
C
C
Control inputs V = V
or GND
or GND
= 3.3 V, T = 25°C.
3
i
I
CC
A or B ports
V = V
O CC
3.3 V
12
io
†
‡
§
All typical values are at V
For I/O ports, the parameter I includes the input leakage current.
This applies in the disabled state only.
CC
A
OZ
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
0.15 V
CC
0.2 V
CC
0.3 V
V
= 2.7 V
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
t
t
A or B
OE
B or A
A or B
A or B
1
1.5
1.5
7.8
10
1
1
1
5.8
1.5
5.7
1.5
1.5
2.2
4.8
ns
ns
ns
pd
8
1.5
1.5
7.9
8.3
6.3
7.4
en
11.9
8.4
OE
dis
operating characteristics, T = 25°C
A
V
= 1.8 V
CC
TYP
V
= 2.5 V
CC
TYP
V = 3.3 V
CC
TEST
CONDITIONS
PARAMETER
UNIT
TYP
Outputs enabled
Outputs disabled
35
3
38
3
43
4
Power dissipation capacitance
per transceiver
C
f = 10 MHz
pF
pd
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢃꢋ ꢌ
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ꢓꢏ ꢐ ꢔ ꢕ ꢍꢀꢐꢌꢐ ꢒ ꢖꢑꢐ ꢗ ꢑꢐꢀ
SCES427A − FEBRUARY 2003 − REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
V
LOAD
Open
S1
R
L
From Output
Under Test
TEST
S1
GND
t
/t
Open
PLH PHL
/t
C
L
t
V
R
PLZ PZL
LOAD
GND
L
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
INPUT
V
CC
V
M
V
C
R
V
LOAD
L
L
∆
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
2.7 V
V
V
V
/2
V
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
30 pF
30 pF
50 pF
50 pF
CC
CC
CC
V
CC
/2
V
CC
CC
2.7 V
2.7 V
1.5 V
1.5 V
6 V
3.3 V 0.3 V
6 V
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
su
h
V
I
V
I
V
M
V
M
Input
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
I
I
Output
Control
V
M
V
M
V
M
V
M
Input
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
+ V
PLH
PHL
Output
Waveform 1
V
V
/2
LOAD
V
V
OH
V
V
V
V
V
M
S1 at V
(see Note B)
M
Output
M
LOAD
V
V
OL
∆
OL
OL
t
t
t
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
− V
OH
∆
V
M
M
M
Output
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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