SN74LVT16245BDLR [TI]
3.3-V ABT 16 BIT BUS TRANSCEIVERS WITH 3 STATE OUTPUTS; 3.3 -V ABT 16位总线与3态输出收发器
| 型号： | SN74LVT16245BDLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT 16 BIT BUS TRANSCEIVERS WITH 3 STATE OUTPUTS |
| 文件： | 总16页 (文件大小：503K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉ ꢃ ꢂ ꢊꢋ ꢀꢁꢌ ꢃ ꢄꢅ ꢆꢇꢈ ꢉꢃ ꢂꢊ
ꢍ ꢎꢍ ꢏꢅ ꢐꢊꢆ ꢇ ꢈ ꢏꢊꢑ ꢆ ꢊꢒꢀ ꢆ ꢓꢐꢁꢀꢔ ꢕ ꢑꢅ ꢕ ꢓꢀ
ꢖ ꢑꢆ ꢗ ꢍ ꢏꢀꢆꢐꢆ ꢕ ꢘ ꢒꢆ ꢙ ꢒꢆꢀ
SCBS715C − FEBRUARY 2000 − REVISED SEPTEMBER 2003
SN54LVT16245B . . . WD PACKAGE
SN74LVT16245B . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
D
D
Members of the Texas Instruments
Widebus Family
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
1
48
47
46
45
44
43
42
41
40
39
38
37
2
3
D
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
4
5
3.3-V V
)
6
CC
V
V
7
D
D
D
D
D
D
D
Support Unregulated Battery Operation
Down to 2.7 V
CC
CC
1B5
1B6
1A5
1A6
GND
1A7
1A8
8
9
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
GND
1B7
10
11
12
= 3.3 V, T = 25°C
A
I
and Power-Up 3-State Support Hot
off
1B8
Insertion
2B1 13
2B2 14
36 2A1
35 2A2
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
CC
15
16
17
18
19
20
21
22
23
24
34
33
32
31
30
29
28
27
26
25
GND
2B3
2B4
GND
2A3
2A4
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
V
V
CC
CC
2B5
2B6
2A5
2A6
GND
2A7
2A8
2OE
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
GND
2B7
2B8
− 1000-V Charged-Device Model (C101)
2DIR
description/ordering information
The ’LVT16245B devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for low-voltage
(3.3-V) V
operation, but with the capability to provide a TTL interface to a 5-V system environment.
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74LVT16245BDL
SSOP − DL
LVT16245B
Tape and reel
Tape and reel
Tape and reel
SN74LVT16245BDLR
SN74LVT16245BDGGR
SN74LVT16245BDGVR
SN74LVT16245BGQLR
SN74LVT16245BZQLR
SNJ54LVT16245BWD
TSSOP − DGG
TVSOP − DGV
VFBGA − GQL
LVT16245B
VD245B
−40°C to 85°C
−55°C to 125°C
Tape and reel
Tube
VD245B
VFBGA − ZQL (Pb-free)
CFP − WD
SNJ54LVT16245BWD
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2003, Texas Instruments Incorporated
ꢒ ꢁ ꢄꢕꢀꢀ ꢘ ꢆꢗ ꢕꢓꢖ ꢑꢀ ꢕ ꢁ ꢘꢆꢕꢚ ꢛꢜ ꢝꢞ ꢟꢠꢡ ꢢꢣꢤ ꢥꢛ ꢡꢠ ꢥꢛꢦ ꢝꢥꢞ ꢙꢓ ꢘ ꢚ ꢒ ꢔꢆ ꢑꢘ ꢁ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉꢃ ꢂ ꢊꢋ ꢀ ꢁꢌ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢃꢂ ꢊ
ꢍꢎ ꢍꢏꢅ ꢐ ꢊ ꢆ ꢇ ꢈꢏ ꢊꢑ ꢆ ꢊꢒ ꢀ ꢆꢓ ꢐꢁ ꢀꢔ ꢕꢑ ꢅ ꢕ ꢓꢀ
ꢖꢑ ꢆ ꢗ ꢍ ꢏꢀꢆꢐꢆ ꢕ ꢘꢒꢆ ꢙꢒ ꢆꢀ
SCBS715C − FEBRUARY 2000 − REVISED SEPTEMBER 2003
description/ordering information (continued)
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission
from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control
(DIR) input. The output-enable (OE) input can be used to disable the devices so that the buses are
effectively isolated.
When V
is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
GQL OR ZQL PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1DIR
1B2
1B4
1B6
1B8
2B1
2B3
2B5
2B7
2DIR
NC
NC
NC
NC
1OE
1A2
1A4
1A6
1A8
2A1
2A3
2A5
2A7
2OE
A
B
C
D
E
F
1B1
1B3
1B5
1B7
2B2
2B4
2B6
2B8
NC
GND
GND
1A1
1A3
1A5
1A7
2A2
2A4
2A6
2A8
NC
V
CC
V
CC
GND
GND
G
H
J
GND
GND
G
H
J
V
CC
V
CC
GND
NC
GND
NC
K
K
NC − No internal connection
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
OE
L
DIR
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉ ꢃ ꢂ ꢊꢋ ꢀꢁꢌ ꢃ ꢄꢅ ꢆꢇꢈ ꢉꢃ ꢂꢊ
ꢍ ꢎꢍ ꢏꢅ ꢐꢊꢆ ꢇ ꢈ ꢏꢊꢑ ꢆ ꢊꢒꢀ ꢆ ꢓꢐꢁꢀꢔ ꢕ ꢑꢅ ꢕ ꢓꢀ
ꢖ ꢑꢆ ꢗ ꢍ ꢏꢀꢆꢐꢆ ꢕ ꢘ ꢒꢆ ꢙ ꢒꢆꢀ
SCBS715C − FEBRUARY 2000 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
24
36
1
2DIR
2A1
1DIR
48
25
13
1OE
1B1
2OE
2B1
47
1A1
2
To Seven Other Channels
To Seven Other Channels
Pin numbers shown are for the DGG, DGV, DL, and WD packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I : SN54LVT16245B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74LVT16245B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, I (see Note 2): SN54LVT16245B . . . . . . . . . . . . . . . . . . . . . 48 mA
O
SN74LVT16245B . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
GQL/ZQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51-7.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉꢃ ꢂ ꢊꢋ ꢀ ꢁꢌ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢃꢂ ꢊ
ꢍꢎ ꢍꢏꢅ ꢐ ꢊ ꢆ ꢇ ꢈꢏ ꢊꢑ ꢆ ꢊꢒ ꢀ ꢆꢓ ꢐꢁ ꢀꢔ ꢕꢑ ꢅ ꢕ ꢓꢀ
ꢖꢑ ꢆ ꢗ ꢍ ꢏꢀꢆꢐꢆ ꢕ ꢘꢒꢆ ꢙꢒ ꢆꢀ
SCBS715C − FEBRUARY 2000 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 4)
SN54LVT16245B SN74LVT16245B
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
5.5
−24
48
0.8
5.5
−32
64
V
IL
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
−55
200
−40
CC
T
A
Operating free-air temperature
125
85
NOTE 4: All unused inputs of the device must at V
or GND to ensure proper device operation. Refer to the TI application report, Implications
of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
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4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉ ꢃ ꢂ ꢊꢋ ꢀꢁꢌ ꢃ ꢄꢅ ꢆꢇꢈ ꢉꢃ ꢂꢊ
ꢍ ꢎꢍ ꢏꢅ ꢐꢊꢆ ꢇ ꢈ ꢏꢊꢑ ꢆ ꢊꢒꢀ ꢆ ꢓꢐꢁꢀꢔ ꢕ ꢑꢅ ꢕ ꢓꢀ
ꢖ ꢑꢆ ꢗ ꢍ ꢏꢀꢆꢐꢆ ꢕ ꢘ ꢒꢆ ꢙ ꢒꢆꢀ
SCBS715C − FEBRUARY 2000 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVT16245B
SN74LVT16245B
PARAMETER
TEST CONDITIONS
UNIT
†
TYP
†
TYP
MIN
MAX
MIN
MAX
V
V
V
V
V
= 2.7 V,
I = −18 mA
−1.2
−1.2
V
IK
CC
CC
CC
I
= 2.7 V to 3.6 V,
= 2.7 V,
I
I
I
I
I
I
I
I
I
I
= −100 µA
= −8 mA
= −24 mA
= −32 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 48 mA
= 64 mA
V
−0.2
V
CC
−0.2
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
CC
2.4
2
2.4
2
V
V
OH
V
= 3 V
CC
CC
0.2
0.5
0.2
0.5
0.4
0.5
V
= 2.7 V
0.4
V
OL
0.5
V
CC
= 3 V
0.55
0.55
1
V
V
= 3.6 V,
V = V
I CC
or GND
1
10
20
5
CC
Control inputs
= 0 or 3.6 V,
V = 5.5 V
I
10
20
1
CC
V = 5.5 V
I
I
I
µA
‡
V = V
V
CC
= 3.6 V
= 0,
A or B ports
I
CC
V = 0
I
−5
−5
100
I
I
V
V
V or V = 0 to 4.5 V
µA
µA
off
CC
I
O
= 0 to 1.5 V, V = 0.5 V to 3 V,
CC
O
100*
100*
100
100
OZPU
OZPD
OE = don’t care
V
= 1.5 V to 0, V = 0.5 V to 3 V,
CC
OE = don’t care
O
µA
I
I
Outputs high
Outputs low
0.19
5
0.19
5
V
I
= 3.6 V,
CC
= 0,
mA
mA
O
CC
V = V
I
or GND
CC
Outputs disabled
0.19
0.19
V
= 3 V to 3.6, One input at V − 0.6 V,
CC
CC
Other inputs at V
§
0.2
0.2
∆I
CC
or GND
CC
C
C
V = 3 V or 0
4
4
pF
pF
i
I
V
O
= 3 V or 0
10
10
io
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
All typical values are at V
Unused pins at V
CC
= 3.3 V, T = 25°C.
A
CC
or GND.
‡
§
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
or GND.
CC
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ꢢ
ꢟꢤ ꢞ ꢝ ꢯꢥ ꢩꢜ ꢦ ꢞ ꢤ ꢠꢧ ꢟꢤ ꢰ ꢤ ꢫꢠ ꢩꢣꢤ ꢥꢛꢎ ꢔ ꢜꢦ ꢨꢦ ꢡꢛ ꢤꢨ ꢝꢞ ꢛꢝ ꢡ ꢟꢦ ꢛꢦ ꢦꢥ ꢟ ꢠꢛ ꢜꢤꢨ
ꢡ
ꢛ
ꢞ
ꢝ
ꢥ
ꢛ
ꢜ
ꢤ
ꢧ
ꢠ
ꢨ
ꢣ
ꢦ
ꢛ
ꢝ
ꢰ
ꢤ
ꢠ
ꢨ
ꢞ
ꢩ
ꢤ
ꢡ
ꢝ
ꢧ
ꢝ
ꢡ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢞ
ꢦ
ꢨ
ꢤ
ꢟ
ꢤ
ꢞ
ꢝ
ꢯ
ꢥ
ꢯ
ꢠ
ꢦ
ꢫ
ꢞ
ꢎ
ꢆ
ꢤ
ꢬ
ꢦ
ꢞ
ꢑ
ꢥ
ꢞ
ꢛ
ꢨ
ꢢ
ꢣ
ꢤ
ꢥ
ꢡ ꢜꢦ ꢥ ꢯꢤ ꢠꢨ ꢟꢝ ꢞ ꢡ ꢠꢥ ꢛꢝ ꢥꢢꢤ ꢛ ꢜꢤ ꢞ ꢤ ꢩꢨ ꢠꢟ ꢢꢡꢛ ꢞ ꢭ ꢝꢛꢜ ꢠꢢꢛ ꢥꢠꢛ ꢝꢡꢤ ꢎ
ꢛ
ꢞ
ꢨ
ꢤ
ꢞ
ꢤ
ꢨ
ꢰ
ꢤ
ꢞ
ꢛ
ꢜ
ꢤ
ꢨ
ꢝ
ꢯ
ꢜ
ꢛ
ꢛ
ꢠ
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉꢃ ꢂ ꢊꢋ ꢀ ꢁꢌ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢃꢂ ꢊ
ꢍꢎ ꢍꢏꢅ ꢐ ꢊ ꢆ ꢇ ꢈꢏ ꢊꢑ ꢆ ꢊꢒ ꢀ ꢆꢓ ꢐꢁ ꢀꢔ ꢕꢑ ꢅ ꢕ ꢓꢀ
ꢖꢑ ꢆ ꢗ ꢍ ꢏꢀꢆꢐꢆ ꢕ ꢘꢒꢆ ꢙꢒ ꢆꢀ
SCBS715C − FEBRUARY 2000 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN54LVT16245B
= 3.3 V
SN74LVT16245B
V
V
= 3.3 V
V
FROM
(INPUT)
TO
(OUTPUT)
CC
CC
V
CC
= 2.7 V
= 2.7 V
PARAMETER
UNIT
CC
MIN
0.3 V
0.3 V
†
MIN
0.5
0.5
0.5
0.5
1
MAX
4.5
4.4
6.5
5.4
6.8
6.2
MIN
MAX
4.6
3.9
6.6
6.2
7
MIN TYP
MAX
3.3
3.3
4.5
4.6
5.1
5.1
0.5
MAX
3.7
3.5
5.3
5.2
5.5
5.4
t
t
t
t
t
t
t
1.5
1.3
1.5
1.6
2.3
2.2
2.3
2.1
2.8
2.9
3.7
3.5
PLH
PHL
PZH
PZL
PHZ
PLZ
sk(o)
A or B
OE
B or A
A or B
A or B
ns
ns
OE
ns
ns
1
6.3
†
All typical values are at V
CC
= 3.3 V, T = 25°C.
A
ꢙ
ꢓ
ꢘ
ꢚ
ꢒ
ꢔ
ꢆ
ꢙ
ꢓ
ꢕ
ꢅ
ꢑ
ꢕ
ꢖ
ꢝ
ꢥ
ꢧ
ꢠ
ꢨ
ꢣ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢡ
ꢠ
ꢥ
ꢡ
ꢤ
ꢨ
ꢥ
ꢞ
ꢩ
ꢨ
ꢠ
ꢟ
ꢢ
ꢡ
ꢟ ꢤ ꢞ ꢝ ꢯ ꢥ ꢩꢜ ꢦ ꢞ ꢤ ꢠꢧ ꢟꢤ ꢰ ꢤ ꢫ ꢠꢩ ꢣꢤ ꢥ ꢛꢎ ꢔ ꢜꢦ ꢨꢦ ꢡꢛ ꢤꢨ ꢝꢞ ꢛꢝ ꢡ ꢟꢦ ꢛꢦ ꢦꢥ ꢟ ꢠꢛ ꢜꢤꢨ
ꢛ
ꢞ
ꢝ
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ꢛ
ꢜ
ꢤ
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ꢡ ꢜ ꢦ ꢥ ꢯꢤ ꢠꢨ ꢟꢝ ꢞ ꢡ ꢠꢥ ꢛꢝ ꢥꢢ ꢤ ꢛ ꢜꢤ ꢞ ꢤ ꢩꢨ ꢠ ꢟꢢꢡ ꢛꢞ ꢭ ꢝꢛꢜ ꢠꢢꢛ ꢥꢠꢛ ꢝꢡꢤ ꢎ
ꢛ
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ꢨ
ꢤ
ꢞ
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ꢰ
ꢤ
ꢞ
ꢛ
ꢜ
ꢤ
ꢨ
ꢝ
ꢯ
ꢜ
ꢛ
ꢛ
ꢠ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉ ꢃ ꢂ ꢊꢋ ꢀꢁꢌ ꢃ ꢄꢅ ꢆꢇꢈ ꢉꢃ ꢂꢊ
ꢍ ꢎꢍ ꢏꢅ ꢐꢊꢆ ꢇ ꢈ ꢏꢊꢑ ꢆ ꢊꢒꢀ ꢆ ꢓꢐꢁꢀꢔ ꢕ ꢑꢅ ꢕ ꢓꢀ
ꢖ ꢑꢆ ꢗ ꢍ ꢏꢀꢆꢐꢆ ꢕ ꢘ ꢒꢆ ꢙ ꢒꢆꢀ
SCBS715C − FEBRUARY 2000 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
6 V
TEST
S1
S1
Open
GND
500 Ω
From Output
Under Test
t
/t
Open
6 V
PLH PHL
/t
t
PLZ PZL
/t
C
= 50 pF
L
t
GND
PHZ PZH
500 Ω
(see Note A)
2.7 V
0 V
LOAD CIRCUIT
1.5 V
Timing Input
Data Input
t
w
t
t
h
su
2.7 V
2.7 V
0 V
1.5 V
1.5 V
Input
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
Input
1.5 V
1.5 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
S1 at 6 V
V
V
3 V
OH
1.5 V
Output
Output
1.5 V
1.5 V
1.5 V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
V
− 0.3 V
OH
1.5 V
1.5 V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
PACKAGING INFORMATION
Orderable Device
74LVT16245BDGGRE4
74LVT16245BDGVRE4
74LVT16245BDLRG4
SN74LVT16245BDGGR
SN74LVT16245BDGVR
SN74LVT16245BDL
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
48
48
48
48
48
48
48
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
TVSOP
SSOP
TSSOP
TVSOP
SSOP
SSOP
SSOP
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGG
DGV
DL
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVT16245BDLG4
SN74LVT16245BDLR
DL
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVT16245BGQLR
SN74LVT16245BGRDR
SN74LVT16245BZQLR
ACTIVE
ACTIVE
ACTIVE
VFBGA
LFBGA
VFBGA
GQL
GRD
ZQL
56
54
56
1000
1000
1000
TBD
TBD
SNPB
SNPB
Level-1-240C-UNLIM
Level-1-240C-UNLIM
Level-1-260C-UNLIM
Pb-Free
(RoHS)
SNAGCU
SN74LVT16245BZRDR
ACTIVE
LFBGA
ZRD
54
1000
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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