SN74LVT32244ZKER [TI]
3.3-V ABT 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS; 3.3 -V ABT 32位缓冲器/驱动器，具有三态输出
| 型号： | SN74LVT32244ZKER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS |
| 文件： | 总11页 (文件大小：245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVT32244
3.3-V ABT 32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCBS748C–OCTOBER 2000–REVISED NOVEMBER 2006
FEATURES
•
Member of Texas Instruments Widebus+™
Family
Input and Output Voltages With 3.3-V VCC)
•
•
•
Supports Unregulated Battery Operation
Down to 2.7 V
•
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V Operation
and Low Static-Power Dissipation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
•
•
•
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
ESD Protection Exceeds JESD 22
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
Ioff and Power-Up 3-State Support Hot
Insertion
1000-V Charged-Device Model (C101)
Supports Mixed-Mode Signal Operation (5-V
GKE OR ZKE PACKAGE
(TOP VIEW)
TERMINAL ASSIGNMENTS
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1Y2
1Y4
2Y2
2Y4
3Y2
3Y4
4Y2
4Y3
5Y2
5Y4
6Y2
6Y4
7Y2
7Y4
8Y2
8Y3
1Y1
1Y3
2Y1
2Y3
3Y1
3Y3
4Y1
4Y4
5Y1
5Y3
6Y1
6Y3
7Y1
7Y3
8Y1
8Y4
1OE
GND
1VCC
GND
GND
1VCC
GND
4OE
5OE
GND
2VCC
GND
GND
2VCC
GND
8OE
2OE
GND
1VCC
GND
GND
1VCC
GND
3OE
6OE
GND
2VCC
GND
GND
2VCC
GND
7OE
1A1
1A3
2A1
2A3
3A1
3A3
4A1
4A4
5A1
5A3
6A1
6A3
7A1
7A3
8A1
8A4
1A2
1A4
2A2
2A4
3A2
3A4
4A2
4A3
5A2
5A4
6A2
6A4
7A2
7A4
8A2
8A3
A
B
C
D
E
F
G
H
J
G
H
J
K
L
M
N
P
R
T
K
L
M
N
P
R
T
DESCRIPTION/ORDERING INFORMATION
The SN74LVT32244 is a 32-bit buffer and line driver designed for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74LVT32244GKER
TOP-SIDE MARKING
VJ244
BGA – GKE
BGA – ZKE (Pb-free)
–40°C to 85°C
Reel of 1000
SN74LVT32244ZKER
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVT32244
3.3-V ABT 32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCBS748C–OCTOBER 2000–REVISED NOVEMBER 2006
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device can be used as eight 4-bit buffers, four 8-bit buffers, two 16-bit buffers, or one 32-bit buffer. The
device provides true outputs and has symmetrical active-output-enable (OE) inputs. It is designed specifically to
improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented
receivers and transmitters.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
FUNCTION TABLE
(each 4-bit buffer/driver)
INPUTS
OUTPUT
Y
OE
L
A
H
L
H
L
L
H
X
Z
2
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SN74LVT32244
3.3-V ABT 32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCBS748C–OCTOBER 2000–REVISED NOVEMBER 2006
LOGIC DIAGRAM (POSITIVE LOGIC)
A3
A5
A6
H4
E5
E6
1OE
1A1
1A2
1A3
1A4
3OE
3A1
3A2
3A3
3A4
A2
A1
B2
B1
E2
E1
F2
F1
1Y1
1Y2
1Y3
1Y4
3Y1
3Y2
3Y3
3Y4
B5
B6
F5
F6
A4
C5
H3
G5
2OE
2A1
4OE
4A1
C2
C1
D2
D1
G2
G1
H1
H2
2Y1
2Y2
2Y3
2Y4
4Y1
4Y2
4Y3
4Y4
C6
D5
D6
G6
H6
H5
2A2
2A3
2A4
4A2
4A3
4A4
J3
J5
T4
N5
5OE
5A1
7OE
7A1
J2
J1
N2
N1
P2
P1
5Y1
5Y2
5Y3
5Y4
7Y1
7Y2
7Y3
7Y4
J6
K5
K6
N6
P5
P6
5A2
5A3
5A4
7A2
7A3
7A4
K2
K1
J4
L5
T3
R5
6OE
6A1
6A2
6A3
6A4
8OE
8A1
8A2
8A3
8A4
L2
L1
R2
R1
T1
T2
6Y1
6Y2
6Y3
6Y4
8Y1
8Y2
8Y3
8Y4
L6
R6
T6
T5
M5
M6
M2
M1
3
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SN74LVT32244
3.3-V ABT 32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCBS748C–OCTOBER 2000–REVISED NOVEMBER 2006
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
4.6
UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high state(2)
Current into any output in the low state
V
7
7
V
V
VO
VO
IO
–0.5 VCC + 0.5
V
128
64
mA
mA
mA
mA
°C/W
°C
IO
Current into any output in the high state(3)
IIK
Input clamp current
VI < 0
–50
–50
40
IOK
θJA
Tstg
Output clamp current
Package thermal impedance(4)
VO < 0
GKE/ZKE package
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This current flows only when the output is in the high state and VO > VCC
.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
2.7
2
MAX
UNIT
V
VCC
VIH
Supply voltage
3.6
High-level input voltage
Low-level input voltage
Input voltage
V
VIL
0.8
5.5
–32
64
V
VI
V
IOH
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
IOL
∆t/∆v
∆t/∆VCC
TA
Outputs enabled
10
200
–40
Operating free-air temperature
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SN74LVT32244
3.3-V ABT 32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCBS748C–OCTOBER 2000–REVISED NOVEMBER 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
VIK
VCC = 2.7 V,
II = –18 mA
IOH = –100 µA
IOH = –8 mA
IOH = –32 mA
IOL = 100 µA
IOL = 24 mA
IOL = 16 mA
IOL = 32 mA
IOL = 64 mA
VI = 5.5 V
–1.2
V
VCC = 2.7 V to 3.6 V,
VCC = 2.7 V,
VCC – 0.2
VOH
2.4
2
V
V
VCC = 3 V,
0.2
0.5
0.4
0.5
0.55
10
VCC = 2.7 V
VOL
VCC = 3 V
VCC = 0 or 3.6 V,
VCC = 3.6 V,
Control inputs
Data inputs
VI = VCC or GND
VI = VCC
±1
II
µA
1
VCC = 3.6 V
VI = 0
–5
Ioff
VCC = 0,
VI or VO = 0 to 4.5 V
VO = 3 V
±100
5
µA
µA
µA
µA
µA
IOZH
IOZL
IOZPU
IOZPD
VCC = 3.6 V,
VCC = 3.6 V,
VO = 0.5 V
–5
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care
VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don't care
Outputs high
VCC = 3.6 V, IO = 0,
VI = VCC or GND
±100
±100
0.38
10
ICC
Outputs low
mA
Outputs disabled
0.38
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
(2)
∆ICC
0.2
mA
Ci
VI = 3 V or 0
VO = 3 V or 0
4
9
pF
pF
Co
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
5
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SN74LVT32244
3.3-V ABT 32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCBS748C–OCTOBER 2000–REVISED NOVEMBER 2006
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.2
1.2
1.2
1.2
2.2
2
TYP(1)
MAX
3.2
3.2
4
MIN
MAX
3.7
3.7
5
tPLH
tPHL
2.3
2
A
Y
Y
Y
ns
ns
ns
ns
tPZH
2.6
2.7
3.3
3.1
OE
OE
tPZL
4
5
tPHZ
4.5
4.2
0.5
0.5
5
tPLZ
4.4
tsk(LH)
tsk(HL)
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
6
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SN74LVT32244
3.3-V ABT 32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCBS748C–OCTOBER 2000–REVISED NOVEMBER 2006
PARAMETER MEASUREMENT INFORMATION
6 V
Open
S1
500 Ω
TEST
/t
S1
From Output
Under Test
GND
t
Open
6 V
GND
PLH PHL
t
t
/t
PLZ PZL
C = 50 pF
L
500 Ω
/t
PHZ PZH
(see Note A)
2.7 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
2.7 V
0 V
2.7 V
0 V
Output
Control
Input
1.5 V
1.5 V
1.5 V
1.5 V
t
t
PZL
PLZ
t
t
t
PHL
PLH
Output
Waveform 1
S1 at 6 V
V
V
3 V
OH
Output
1.5 V
1.5 V
1.5 V
1.5 V
V
+ 0.3 V
OL
V
OL
(see Note B)
OL
t
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
V
− 0.3 V
OH
1.5 V
VOLTAGE WAVEFORMS
Output
1.5 V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Sep-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74LVT32244GKER
SN74LVT32244ZKER
NRND
LFBGA
LFBGA
GKE
96
96
1000
TBD
SNPB
Level-3-220C-168 HR
Level-3-260C-168 HR
ACTIVE
ZKE
1000 Green (RoHS &
no Sb/Br)
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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