SN74LVT573DBR [TI]
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS; 3.3 -V ABT八路透明D类锁存器具有三态输出
| 型号： | SN74LVT573DBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| 文件： | 总15页 (文件大小：467K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LVT573, SN74LVT573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS138D – MAY 1992 – REVISED JULY 1995
SN54LVT573 . . . J OR W PACKAGE
SN74LVT573 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static Power
Dissipation
OE
1D
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
1Q
2Q
3Q
4Q
5Q
6Q
)
CC
2D
3D
Support Unregulated Battery Operation
Down to 2.7 V
4D
5D
6D
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 3.3 V, T = 25°C
CC
A
7D
8D
13 7Q
12 8Q
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
11
GND
LE
SN54LVT573 . . . FK PACKAGE
(TOP VIEW)
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
Support Live Insertion
3
2
1
20 19
18
4
5
6
7
8
3D
4D
5D
6D
7D
2Q
3Q
4Q
5Q
6Q
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Packages, and Ceramic
(J) DIPs
17
16
15
14
9 10 11 12 13
description
These octal latches are designed specifically for low-voltage (3.3-V) V
provide a TTL interface to a 5-V system environment.
operation, but with the capability to
CC
The eight latches of the ’LVT573 are transparent D-type latches. While the latch-enable (LE) input is high, the
Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up
at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components. OE does not affect the internal operations of the latches.
Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVT573 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LVT573 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LVT573 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT573, SN74LVT573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS138D – MAY 1992 – REVISED JULY 1995
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
†
logic symbol
logic diagram (positive logic)
1
OE
1
EN
C1
OE
11
LE
11
LE
2
1D
3
19
18
17
16
15
14
13
12
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
C1
19
2D
4
1Q
2
1D
1D
3D
5
4D
6
5D
7
6D
8
7D
9
To Seven Other Channels
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high state or power-off state, V (see Note 1) . . . . –0.5 V to 7 V
O
Current into any output in the low state, I : SN54LVT573 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74LVT573 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, I (see Note 2): SN54LVT573 . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
SN74LVT573 . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Maximum power dissipation at T = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . 0.6 W
A
DW package . . . . . . . . . . . . . . . . . . . 1.6 W
PW package . . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation,refertothePackageThermalConsiderationsapplicationnoteinthe1994ABTAdvancedBiCMOSTechnology
Data Book, literature number SCBD002B.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT573, SN74LVT573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS138D – MAY 1992 – REVISED JULY 1995
recommended operating conditions (see Note 4)
SN54LVT573 SN74LVT573
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
5.5
–24
48
0.8
5.5
–32
64
V
IL
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
mA
mA
ns/V
°C
OH
OL
∆t/∆v
Outputs enabled
10
10
T
A
–55
125
–40
85
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT573, SN74LVT573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS138D – MAY 1992 – REVISED JULY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVT573
SN74LVT573
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 2.7 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
CC
CC
I
‡
= MIN to MAX ,
= 2.7 V,
I
I
I
I
I
I
I
I
I
I
= –100 µA
= – 8 mA
= – 24 mA
= –32 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 48 mA
= 64 mA
V
–0.2
V
–0.2
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
CC
2.4
CC
2.4
V
OH
V
V
2
V
= 3 V
CC
CC
2
0.2
0.5
0.2
0.5
0.4
0.5
V
= 2.7 V
0.4
V
OL
0.5
V
CC
V
CC
V
CC
= 3 V
0.55
0.55
10
‡
= 0 or MAX ,
V = 5.5 V
I
50
Control
inputs
V = V
or GND
±1
±1
I
CC
CC
I
I
µA
= 3.6 V
V = V
I
1
1
–5
Data inputs
V = 0
I
–5
I
I
V
V
= 0,
V or V = 0 to 4.5 V
±100
µA
µA
off
CC
I
O
V = 0.8 V
I
75
75
= 3 V
Data inputs
I(hold)
CC
V = 2 V
I
–75
–75
I
I
V
V
= 3.6 V,
= 3.6 V,
V
= 3 V
1
–1
1
–1
µA
µA
OZH
CC
O
O
V
= 0.5 V
OZL
CC
Outputs high
Outputs low
0.13
8.6
0.39
14
0.13
8.6
0.19
12
V
= 3.6 V,
or GND
CC
I
= 0,
CC
O
I
mA
CC
V = V
I
Outputs
disabled
0.13
0.39
0.3
0.13
0.19
0.2
V
= 3 V to 3.6 V,
One input at V
or GND
– 0.6 V,
CC
CC
Other inputs at V
§
∆I
mA
CC
CC
C
C
V = 3 V or 0
4
8
4
8
pF
pF
i
I
V
O
= 3 V or 0
o
†
‡
§
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVT573
= 3.3 V
SN74LVT573
= 3.3 V
V
V
CC
± 0.3 V
CC
± 0.3 V
V
CC
= 2.7 V
MAX
V
CC
= 2.7 V
MAX
UNIT
MIN
3.3
1
MAX
MIN
3.3
0.9
2
MIN
3.3
0.7
1.6
MAX
MIN
3.3
0.6
1.8
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
1.8
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT573, SN74LVT573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS138D – MAY 1992 – REVISED JULY 1995
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN54LVT573
= 3.3 V
SN74LVT573
= 3.3 V
FROM
(INPUT)
TO
(OUTPUT)
V
V
CC
± 0.3 V
CC
± 0.3 V
V
CC
= 2.7 V
V
CC
= 2.7 V
PARAMETER
UNIT
†
MIN
0.5
0.5
1
MAX
4.7
4.9
6
MIN
MAX
4.9
5.4
6.9
7.6
6.4
7.2
6.9
5.5
MIN TYP
MAX
4.2
4.3
5.6
6.5
5.1
5.5
5.7
4.6
MIN
MAX
4.7
5.2
6.3
7.2
6.2
6.6
6.7
5.1
t
t
t
t
t
t
t
t
1
1
2.5
2.7
3.5
4.3
2.8
3.3
3.7
3
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
Q
Q
Q
ns
ns
ns
ns
1.6
2.5
1
LE
1.4
0.5
0.7
1.2
1
6.9
5.3
5.7
5.9
5.4
OE
OE
1.3
2
1.5
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT573, SN74LVT573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS138D – MAY 1992 – REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
6 V
Open
TEST
S1
S1
t
/t
Open
6 V
500 Ω
PLH PHL
From Output
Under Test
t
/t
PLZ PZL
GND
t
/t
PHZ PZH
GND
C
= 50 pF
L
500 Ω
(see Note A)
2.7 V
0 V
LOAD CIRCUIT FOR OUTPUTS
1.5 V
Timing Input
Data Input
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
t
1.5 V
1.5 V
Input
t
PZL
t
t
PHL
PLH
PLZ
1.5 V
Output
Waveform 1
S1 at 6 V
V
V
3 V
OH
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
t
PZH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
OH
1.5 V
1.5 V
Output
(see Note B)
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SSOP
SSOP
Drawing
SN74LVT573DBLE
SN74LVT573DBR
OBSOLETE
ACTIVE
DB
20
20
TBD
Call TI
Call TI
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVT573DBRE4
SN74LVT573DW
ACTIVE
ACTIVE
SSOP
SOIC
DB
20
20
TBD
Call TI
Call TI
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVT573DWE4
SN74LVT573DWR
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
20
20
TBD
Call TI
Call TI
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVT573DWRE4
SN74LVT573NSR
SN74LVT573PWLE
SN74LVT573PWR
ACTIVE
SOIC
SO
DW
NS
20
20
20
20
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
OBSOLETE
OBSOLETE TSSOP
PW
PW
ACTIVE
TSSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVT573PWRE4
SNJ54LVT573FK
SNJ54LVT573J
ACTIVE
TSSOP
LCCC
CDIP
CFP
PW
FK
J
20
20
20
20
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
OBSOLETE
OBSOLETE
OBSOLETE
SNJ54LVT573W
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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Following are URLs where you can obtain information on other Texas Instruments products and application
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Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
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www.ti.com/automotive
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dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
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Microcontrollers
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Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
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