SN74LVTH162240DGGR [TI]
3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS; 3.3 -V ABT 16位缓冲器/驱动器，具有三态输出
| 型号： | SN74LVTH162240DGGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总11页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LVTH162240, SN74LVTH162240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS685E – MARCH 1997 – REVISED APRIL 1999
SN54LVTH162240 . . . WD PACKAGE
SN74LVTH162240 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
1OE
1Y1
1Y2
GND
1Y3
1Y4
2OE
1A1
1A2
GND
1A3
1A4
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
40
Output Ports Have Equivalent 22-Ω Series
Resistors, So No External Resistors Are
Required
V
V
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
CC
CC
)
2Y1
2Y2
2A1
2A2
CC
Support Unregulated Battery Operation
Down to 2.7 V
GND 10
39 GND
2Y3
2Y4
2A3
2A4
11
12
38
37
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 3.3 V, T = 25°C
CC
A
3Y1 13
3Y2 14
GND 15
3Y3 16
3Y4 17
36 3A1
35 3A2
34 GND
33 3A3
32 3A4
I
and Power-Up 3-State Support Hot
off
Insertion
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
V
18
31
V
CC
CC
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
4Y1 19
4Y2 20
GND 21
4Y3 22
4Y4 23
4OE 24
30 4A1
29 4A2
28 GND
27 4A3
26 4A4
25 3OE
CC
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’LVTH162240devices are 16-bit buffers/drivers designed specifically for low-voltage (3.3-V) V operation
CC
and to improve both the performance and density of 3-state memory address drivers, clock drivers, and
bus-oriented receivers and transmitters. They have the capability to provide a TTL interface to a 5-V system
environment.
These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer and provide inverting
outputs and symmetrical active-low output-enable (OE) inputs.
The outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors to
reduce overshoot and undershoot.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH162240, SN74LVTH162240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS685E – MARCH 1997 – REVISED APRIL 1999
description (continued)
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
through a pullup resistor;
CC
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
TheSN54LVTH162240ischaracterizedforoperationoverthefullmilitarytemperaturerangeof–55°Cto125°C.
The SN74LVTH162240 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
L
H
Z
H
X
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH162240, SN74LVTH162240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS685E – MARCH 1997 – REVISED APRIL 1999
†
logic symbol
1
1OE
2OE
3OE
EN1
EN2
EN3
EN4
48
25
24
4OE
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
1
1
1
1
2
3
1Y1
3
1Y2
5
1Y3
6
1Y4
8
2Y1
9
2Y2
11
2Y3
12
2Y4
13
3Y1
14
3Y2
16
3Y3
17
3Y4
19
1
4
4Y1
20
4Y2
22
4Y3
23
4Y4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH162240, SN74LVTH162240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS685E – MARCH 1997 – REVISED APRIL 1999
logic diagram (positive logic)
1
25
36
1OE
3OE
3A1
47
46
44
43
2
13
14
16
17
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
3Y1
3Y2
3Y3
3Y4
3
5
6
35
33
32
3A2
3A3
3A4
48
41
24
30
2OE
2A1
4OE
4A1
8
9
19
20
22
23
2Y1
2Y2
2Y3
2Y4
4Y1
4Y2
4Y3
4Y4
40
38
37
29
27
26
2A2
2A3
2A4
4A2
4A3
4A4
11
12
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I
Current into any output in the high state, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
O
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH162240, SN74LVTH162240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS685E – MARCH 1997 – REVISED APRIL 1999
recommended operating conditions (see Note 4)
SN54LVTH162240 SN74LVTH162240
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
5.5
–12
12
0.8
5.5
–12
12
V
IL
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
–55
200
–40
CC
T
A
Operating free-air temperature
125
85
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH162240
SN74LVTH162240
PARAMETER
TEST CONDITIONS
I = –18 mA
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
V
V
V
= 2.7 V,
= 3 V,
–1.2
–1.2
V
V
V
IK
CC
CC
CC
CC
CC
I
I
I
= –12 mA
= 12 mA
2
2
OH
OL
OH
OL
= 3 V,
0.8
10
±1
1
0.8
10
= 0 or 3.6 V,
= 3.6 V,
V = 5.5 V
I
Control inputs
V = V
or GND
±1
I
CC
CC
I
I
I
µA
µA
µA
I
V = V
1
I
V
CC
V
CC
V
CC
= 3.6 V
= 0,
Data inputs
V = 0
I
–5
–5
V or V = 0 to 4.5 V
±100
off
I
O
V = 0.8 V
I
75
75
= 3 V
V = 2 V
I
–75
–75
Data inputs
I(hold)
500
–750
‡
V
CC
= 3.6 V ,
V = 0 to 3.6 V
I
I
I
V
V
V
= 3.6 V,
= 3.6 V,
V
V
= 3 V
5
5
µA
µA
OZH
CC
CC
CC
O
= 0.5 V
–5
–5
OZL
O
= 0 to 1.5 V, V = 0.5 V to 3 V,
O
±100*
±100*
±100
±100
µA
µA
I
OZPU
OZPD
OE = don’t care
V
= 1.5 V to 0, V = 0.5 V to 3 V,
CC
OE = don’t care
O
I
Outputs high
Outputs low
0.19
5
0.19
5
V
I
= 3.6 V,
CC
= 0,
I
mA
CC
O
V = V
I
or GND
CC
Outputs disabled
0.19
0.19
V
= 3 V to 3.6 V, One input at V – 0.6 V,
CC
CC
Other inputs at V
§
0.2
0.2
mA
∆I
CC
or GND
CC
C
C
V = 3 V or 0
4
9
4
9
pF
pF
i
I
V
O
= 3 V or 0
o
On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
‡
§
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH162240, SN74LVTH162240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS685E – MARCH 1997 – REVISED APRIL 1999
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN54LVTH162240
= 3.3 V
SN74LVTH162240
FROM
(INPUT)
TO
(OUTPUT)
V
V
= 3.3 V
V
CC
CC
V
CC
= 2.7 V
= 2.7 V
PARAMETER
UNIT
CC
MIN
± 0.3 V
± 0.3 V
†
MIN
1
MAX
4.2
4.2
5
MIN
MAX
5
MIN TYP
MAX
4
MAX
4.6
4.6
5.7
4.9
5.2
4.5
0.5
t
t
t
t
t
t
t
1
1
1
1
2
2
2.5
2.9
2.8
2.8
3.5
3.4
PLH
PHL
PZH
PZL
PHZ
PLZ
sk(o)
A
Y
Y
Y
ns
ns
1
5
4
1
5.5
5.1
5.4
4.8
4.8
4.7
4.7
4.5
0.5
OE
OE
1
4.9
4.9
4.7
1.9
1.9
ns
ns
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH162240, SN74LVTH162240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS685E – MARCH 1997 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
6 V
Open
GND
S1
TEST
S1
500 Ω
From Output
Under Test
t
/t
Open
6 V
PLH PHL
t
/t
PLZ PZL
C
= 50 pF
L
t
/t
GND
500 Ω
PHZ PZH
(see Note A)
2.7 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
0 V
V
t
t
t
PHL
t
t
PLZ
PLH
PZL
Output
Waveform 1
S1 at 6 V
3 V
OH
1.5 V
1.5 V
1.5 V
t
Output
1.5 V
V
OL
+ 0.3 V
V
OL
V
OL
(see Note B)
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
– 0.3 V
1.5 V
OH
1.5 V
Output
≈ 0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
PACKAGING INFORMATION
Orderable Device
74LVTH162240DGGRE4
SN74LVTH162240DGGR
SN74LVTH162240DL
SN74LVTH162240DLR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
48
48
48
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
SSOP
SSOP
DGG
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
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amplifier.ti.com
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dataconverter.ti.com
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www.ti.com/digitalcontrol
www.ti.com/military
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interface.ti.com
logic.ti.com
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power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
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www.ti.com/video
microcontroller.ti.com
Telephony
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