SN74LVTH16373DLR [TI]
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS; 3.3 -V ABT 16位透明D类锁存器三态输出
| 型号： | SN74LVTH16373DLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| 文件： | 总16页 (文件大小：469K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LVTH16373, SN74LVTH16373
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
www.ti.com
SCBS144O–MAY 1992–REVISED OCTOBER 2005
FEATURES
SN54LVTH16373 . . . WD PACKAGE
SN74LVTH16373 . . . DGG OR DL PACKAGE
(TOP VIEW)
•
Members of the Texas Instruments Widebus™
Family
•
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V Operation
and Low Static-Power Dissipation
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
1LE
1D1
1D2
GND
1D3
1D4
2
3
•
•
•
•
•
•
•
•
•
Support Mixed-Mode Signal Operation (5-V
4
Input and Output Voltages With 3.3-V VCC
)
5
Support Unregulated Battery Operation Down
to 2.7 V
6
7
V
CC
V
CC
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
8
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
9
Ioff and Power-Up 3-State Support Hot
Insertion
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
V
CC
V
CC
Latch-Up Performance Exceeds 500 mA Per
JESD 17
2Q5
2Q6
GND
2Q7
2Q8
2OE
2D5
2D6
GND
2D7
2D8
2LE
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
DESCRIPTION/ORDERING INFORMATION
The 'LVTH16373 devices are 16-bit transparent D-type latches with 3-state outputs designed for low-voltage
(3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These
devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working
registers.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74LVTH16373GRDR
SN74LVTH16373ZRDR
SN74LVTH16373DL
TOP-SIDE MARKING
LL373
FBGA – GRD
Tape and reel
FBGA – ZRD (Pb-free)
Tube
SSOP – DL
LVTH16373
LVTH16373
LL373
–40°C to 85°C
–55°C to 125°C
Tape and reel
Tape and reel
SN74LVTH16373DLR
TSSOP – DGG
VFBGA – GQL
VFBGA – ZQL (Pb-free)
CFP – WD
SN74LVTH16373DGGR
SN74LVTH16373GQLR
SN74LVTH16373ZQLR
SNJ54LVTH16373WD
Tape and reel
Tube
SNJ54LVTH16373WD
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1992–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
On products compliant to MIL-PRF-38535, all parameters are
Instruments standard warranty. Production processing does not
tested unless otherwise noted. On all other products, production
necessarily include testing of all parameters.
processing does not necessarily include testing of all parameters.
SN54LVTH16373, SN74LVTH16373
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
www.ti.com
SCBS144O–MAY 1992–REVISED OCTOBER 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the
Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the
D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
TERMINAL ASSIGNMENTS(1)
(56-Ball GQL/ZQL Package)
GQL OR ZQL PACKAGE
(TOP VIEW)
1
2 3 4 5 6
1
2
3
4
5
6
A
B
C
D
E
F
1OE
1Q2
1Q4
1Q6
1Q8
2Q1
2Q3
2Q5
2Q7
2OE
NC
NC
NC
NC
1CLK
1D2
1D4
1D6
1D8
2D1
2D3
2D5
2D7
2CLK
A
B
C
D
E
F
G
H
J
1Q1
1Q3
1Q5
1Q7
2Q2
2Q4
2Q6
2Q8
NC
GND
VCC
GND
GND
VCC
GND
1D1
1D3
1D5
1D7
2D2
2D4
2D6
2D8
NC
G
H
J
GND
VCC
GND
NC
GND
VCC
GND
NC
K
K
(1) NC – No internal connection
2
SN54LVTH16373, SN74LVTH16373
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
www.ti.com
SCBS144O–MAY 1992–REVISED OCTOBER 2005
GRD OR ZRD PACKAGE
(TOP VIEW)
TERMINAL ASSIGNMENTS(1)
(54-Ball GRD/ZRD Package)
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1Q1
1Q3
1Q5
1Q7
2Q1
2Q3
2Q5
2Q7
2Q8
NC
1OE
NC
1LE
NC
NC
1D1
1D3
1D5
1D7
2D1
2D3
2D5
2D7
2D8
A
B
C
D
1Q2
1Q4
1Q6
1Q8
2Q2
2Q4
2Q6
NC
1D2
1D4
1D6
1D8
2D2
2D4
2D6
NC
VCC
GND
GND
GND
VCC
NC
VCC
GND
GND
GND
VCC
NC
E
F
G
H
J
G
H
J
2OE
2LE
(1) NC – No internal connection
FUNCTION TABLE
(8-BIT SECTION)
INPUTS
OUTPUT
Q
OE
L
CLK
H
D
H
L
H
L
L
H
L
L
X
X
Q0
Z
H
X
LOGIC DIAGRAM (POSITIVE LOGIC)
1
24
2OE
1OE
25
48
2LE
1LE
C1
1D
C1
1D
2
13
2Q1
1Q1
47
36
2D1
1D1
To Seven Other Channels
Pin numbers shown are for the DGG, DL, and WD packages.
To Seven Other Channels
3
SN54LVTH16373, SN74LVTH16373
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
www.ti.com
SCBS144O–MAY 1992–REVISED OCTOBER 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
4.6
UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high state(2)
V
7
7
V
V
V
VO
VO
–0.5 VCC + 0.5
SN54LVTH16373
Current into any output in the low state
96
128
48
IO
mA
mA
SN74LVTH16373
SN54LVTH16373
Current into any output in the high state(3)
SN74LVTH16373
IO
64
IIK
Input clamp current
Output clamp current
VI < 0
–50
–50
70
mA
mA
IOK
VO < 0
DGG package
DL package
GQL/ZQL package
GRD/ZRD package
63
θJA
Package thermal impedance(4)
°C
°C
42
36
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This current flows only when the output is in the high state and VO > VCC
.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
SN54LVTH16373
SN74LVTH16373
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
VCC
VIH
Supply voltage
3.6
3.6
V
V
High-level input voltage
Low-level input voltage
Input voltage
VIL
0.8
5.5
–24
48
0.8
5.5
–32
64
V
VI
V
IOH
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
IOL
∆t/∆v
∆t/∆VCC
TA
Outpts enabled
10
10 ns/V
200
–55
200
–40
µs/V
Operating free-air temperature
125
85
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
SN54LVTH16373, SN74LVTH16373
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
www.ti.com
SCBS144O–MAY 1992–REVISED OCTOBER 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
SN54LVTH16373
MIN TYP(1)
SN74LVTH16373
MIN TYP(1) MAX
–1.2
PARAMETER
VIK
TEST CONDITIONS
UNIT
MAX
VCC = 2.7 V,
II = –18 mA
–1.2
V
VCC = 2.7 V to 3.6 V,
VCC = 2.7 V,
IOH = –100 µA
IOH = –8 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 µA
IOL = 24 mA
IOL = 16 mA
IOL = 32 mA
IOL = 48 mA
IOL = 64 mA
VI = 5.5 V
VCC – 0.2
VCC – 0.2
2.4
2
2.4
VOH
V
V
VCC = 3 V
2
0.2
0.5
0.2
0.5
0.4
0.5
VCC = 2.7 V
0.4
VOL
0.5
VCC = 3 V
0.55
0.55
10
VCC = 0 or 3.6 V,
VCC = 3.6 V,
10
Control
inputs
VI = VCC or GND
±1
±1
II
µA
VI = VCC
1
1
–5
Data
inputs
VCC = 3.6 V
VCC = 0,
VI = 0
–5
Ioff
VI or VO = 0 to 4.5 V
VI = 0.8 V
VI = 2 V
±100
µA
µA
75
75
VCC = 3 V
Data
inputs
II(hold)
–75
–75
VCC = 3.6 V,(2)
VCC = 3.6 V,
VCC = 3.6 V,
VI = 0 to 3.6 V
VO = 3 V
±500
5
IOZH
IOZL
5
µA
µA
VO = 0.5 V
–5
–5
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = don't care
IOZPU
IOZPD
±100(3)
±100(3)
±100
±100
µA
µA
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE = don't care
Outputs high
VCC = 3.6 V,
0.19
5
0.19
5
ICC
IO = 0,
Outputs low
mA
mA
VI = VCC or GND
Outputs disabled
0.19
0.19
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
(4)
∆ICC
0.2
0.2
Ci
VI = 3 V or 0
VO = 3 V or 0
3
9
3
9
pF
pF
Co
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
(3) On products compliant to MIL-PRF-38535, this parameter is not production tested.
(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
5
SN54LVTH16373, SN74LVTH16373
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
www.ti.com
SCBS144O–MAY 1992–REVISED OCTOBER 2005
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN54LVTH16373
VCC = 3.3 V
± 0.3 V
MIN MAX MIN
SN74LVTH16373
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
VCC = 2.7 V
UNIT
MAX
MIN
3
MAX
MIN
3
MAX
tw
tsu
th
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
3
2
3
3
2
ns
ns
ns
1
0.6
1.1
3.3
1
Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54LVTH16373
VCC = 3.3 V
± 0.3 V
SN74LVTH16373
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
PARAMETER
VCC = 2.7 V
VCC = 2.7 V
UNIT
± 0.3 V
MIN MAX MIN MAX MIN TYP(1) MAX MIN MAX
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsk(o)
1.4
1.4
1.8
1.8
1.4
1.4
2
4.5
4.4
5.5
5.2
5.7
5.5
6
5.2
4.8
5.8
5.6
6.7
6
1.5
1.5
2.1
2.1
1.5
1.5
2.4
2
2.7
2.5
3
3.8
3.6
4.3
4
4.2
4
D
Q
Q
Q
Q
ns
ns
ns
4.8
4
LE
OE
OE
2.9
2.8
2.8
3.5
3.2
4.3
4.3
5
5.1
4.7
5.4
4.8
6.2
5.6
ns
ns
1.4
5.2
4.7
0.5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
6
SN54LVTH16373, SN74LVTH16373
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
www.ti.com
SCBS144O–MAY 1992–REVISED OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION
6 V
Open
GND
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
6 V
PLH PHL
t
/t
PLZ PZL
C = 50 pF
(see Note A)
t
/t
GND
L
PHZ PZH
500 Ω
2.7 V
0 V
Timing Input
Data Input
1.5 V
LOAD CIRCUIT
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
t
PHL
t
t
PLH
PZL
PLZ
Output
Waveform 1
S1 at 6 V
V
V
3 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
t
Output
V
+ 0.3 V
OL
V
OL
(see Note B)
OL
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
V
− 0.3 V
OH
1.5 V
1.5 V
Output
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com
4-Oct-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
5962-9681001QXA
ACTIVE
ACTIVE
CFP
WD
48
48
1
TBD
Call TI
Level-NC-NC-NC
74LVTH16373DGGRG4
TSSOP
DGG
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVTH16373DGGR
SN74LVTH16373DL
SN74LVTH16373DLR
ACTIVE
ACTIVE
ACTIVE
TSSOP
SSOP
SSOP
DGG
DL
48
48
48
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVTH16373GQLR
SN74LVTH16373GRDR
SN74LVTH16373ZQLR
ACTIVE
ACTIVE
ACTIVE
VFBGA
LFBGA
VFBGA
GQL
GRD
ZQL
56
54
56
1000
1000
TBD
TBD
SNPB
SNPB
Level-1-240C-UNLIM
Level-1-240C-UNLIM
Level-1-260C-UNLIM
1000 Green (RoHS &
no Sb/Br)
SNAGCU
SN74LVTH16373ZRDR
SNJ54LVTH16373WD
ACTIVE
ACTIVE
LFBGA
CFP
ZRD
WD
54
48
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Call TI
Level-1-260C-UNLIM
Level-NC-NC-NC
1
TBD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997
WD (R-GDFP-F**)
CERAMIC DUAL FLATPACK
48 LEADS SHOWN
0.120 (3,05)
0.075 (1,91)
0.009 (0,23)
0.004 (0,10)
1.130 (28,70)
0.870 (22,10)
0.370 (9,40)
0.250 (6,35)
0.390 (9,91)
0.370 (9,40)
0.370 (9,40)
0.250 (6,35)
1
48
0.025 (0,635)
A
0.014 (0,36)
0.008 (0,20)
24
25
NO. OF
LEADS**
48
56
0.740
0.640
(16,26) (18,80)
A MAX
A MIN
0.610 0.710
(15,49) (18,03)
4040176/D 10/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only
E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA
GDFP1-F56 and JEDEC MO-146AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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