SN74LVTH16500-EP [TI]
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS; ?? 3.3 -V ABT 18位通用总线三态输出收发器
| 型号： | SN74LVTH16500-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS |
| 文件： | 总10页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCBS783 − NOVEMBER 2003
D
D
D
D
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
Enhanced Diminishing Manufacturing
Sources (DMS) Support
DGG PACKAGE
(TOP VIEW)
Enhanced Product-Change Notification
†
Qualification Pedigree
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEAB
LEAB
A1
GND
A2
GND
CLKAB
B1
GND
B2
Member of the Texas Instruments
Widebus Family
UBT Transceivers Combine D-Type
Latches and D-Type Flip-Flops for
Operation in Transparent, Latched, or
Clocked Mode
2
3
D
4
5
6
A3
B3
7
V
V
CC
A4
CC
D
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
8
B4
B5
B6
GND
B7
9
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
3.3-V V
)
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
D
D
D
D
Supports Unregulated Battery Operation
Down To 2.7 V
Typical V
<0.8 V at V
(Output Ground Bounce)
= 3.3 V, T = 25°C
B8
B9
OLP
CC
A
B10
B11
B12
GND
B13
B14
B15
I
and Power-Up 3-State Support Hot
off
Insertion
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
D
D
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
CC
V
V
CC
CC
Flow-Through Architecture Optimizes PCB
Layout
A16
A17
GND
A18
OEBA
LEBA
B16
B17
GND
B18
CLKBA
GND
Latch-Up Performance Exceeds 500 mA Per
JESD 17
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
description/ordering information
The SN74LVTH16500 is an 18-bit universal bus transceiver designed for low-voltage (3.3-V) V
but with the capability to provide a TTL interface to a 5-V system environment.
operation,
CC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and UBT are trademarks of Texas Instruments.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢋꢌ ꢍꢎ
ꢏꢐ ꢏꢌꢅ ꢑ ꢒ ꢆ ꢈ ꢓꢌ ꢒꢔ ꢆ ꢕꢁ ꢔ ꢅꢍ ꢖꢀ ꢑꢄ ꢒꢕ ꢀ ꢆꢖ ꢑ ꢁꢀꢗꢍ ꢔꢅꢍ ꢖ
ꢘꢔ ꢆ ꢇ ꢏ ꢌꢀꢆꢑꢆ ꢍ ꢙꢕꢆ ꢎ ꢕꢆꢀ
SCBS783 − NOVEMBER 2003
description/ordering information (continued)
ORDERING INFORMATION
ORDERABLE
PART NUMBER
†
T
A
PACKAGE
TOP-SIDE MARKING
−40°C to 85°C
TSSOP − DGG
Tape and reel
CLVTH16500IDGGREP
LH16500EP
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is
low, the A data is stored in the latch/flip-flop on the high-to-low transition of CLKAB. OEAB is active high. When
OEAB is high, the B-port outputs are active. When OEAB is low, the B-port outputs are in the high-impedance
state.
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
When V
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
through a pullup resistor
CC
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.
This device is fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
†
FUNCTION TABLE
INPUTS
OUTPUT
B
OEAB
LEAB
CLKAB
A
X
L
L
X
H
H
L
X
X
X
↓
↓
H
L
Z
L
H
H
H
H
H
H
H
L
H
L
L
H
X
X
H
‡
B
0
§
B
0
L
L
†
‡
§
A-to-B data flow is shown: B-to-A flow is similar, but
uses OEBA, LEBA, and CLKBA.
Output level before the indicated steady-state input
conditions were established
Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was low before LEAB went low
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCBS783 − NOVEMBER 2003
logic diagram (positive logic)
1
OEAB
55
CLKAB
2
LEAB
28
LEBA
30
CLKBA
27
OEBA
3
A1
1D
C1
CLK
54
B1
1D
C1
CLK
To 17 Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I
Current into any output in the high state, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
O
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Package thermal impedance, θ (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
JA
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51-7.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢋꢌ ꢍꢎ
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ꢘꢔ ꢆ ꢇ ꢏ ꢌꢀꢆꢑꢆ ꢍ ꢙꢕꢆ ꢎ ꢕꢆꢀ
SCBS783 − NOVEMBER 2003
recommended operating conditions (see Note 4)
MIN
2.7
2
MAX
UNIT
V
V
V
V
V
Supply voltage
3.6
CC
High-level input voltage
Low-level input voltage
Input voltage
V
IH
0.8
5.5
−32
64
V
IL
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
200
−40
CC
T
A
Operating free-air temperature
85
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
= 2.7 V,
I = −18 mA
−1.2
V
IK
CC
CC
CC
CC
I
= 2.7 V to 3.6 V,
= 2.7 V,
I
I
I
I
I
I
I
I
= −100 µA
= −8 mA
= −32 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 64 mA
V
−0.2
OH
OH
OH
OL
OL
OL
OL
OL
CC
2.4
V
OH
V
V
= 3 V,
2
0.2
0.5
0.4
0.5
0.55
1
V
= 2.7 V
CC
CC
V
OL
V
= 3 V
V
V
= 3.6 V,
V = V or GND
I CC
CC
Control inputs
= 0 or 3.6 V,
V = 5.5 V
I
10
CC
V = 5.5 V
I
20
I
I
µA
‡
V = V
1
V
CC
= 3.6 V
A or B ports
I
CC
V = 0
I
−5
I
I
V
V
= 0,
V or V = 0 to 4.5 V
100
µA
µA
off
CC
I
O
V = 0.8 V
I
75
= 3 V
CC
V = 2 V
I
−75
A or B ports
I(hold)
§
V
V
V
= 3.6 V ,
V = 0 to 3.6 V
500
100
CC
CC
CC
I
= 0 to 1.5 V, V = 0.5 V to 3 V, OE/OE = don’t care
O
µA
µA
I
I
OZPU
= 1.5 V to 0, V = 0.5 V to 3 V, OE/OE = don’t care
O
100
0.19
5
OZPD
Outputs high
Outputs low
I
V
= 3.6 V, I = 0, V = V
CC
or GND
mA
CC
CC
CC
O
I
Outputs disabled
0.19
0.2
¶
V
= 3 V to 3.6 V, One input at V
CC
− 0.6 V, Other inputs at V
or GND
mA
pF
pF
∆I
CC
CC
C
C
V = 3 V or 0
4
i
I
V
O
= 3 V or 0
10
io
†
‡
§
¶
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
Unused pins at V
or GND
CC
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
or GND.
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢊꢋ ꢋꢌ ꢍꢎ
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ꢘ ꢔꢆ ꢇ ꢏ ꢌꢀꢆꢑꢆ ꢍ ꢙ ꢕꢆ ꢎꢕ ꢆꢀ
SCBS783 − NOVEMBER 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V = 3.3 V
CC
0.3 V
V
CC
= 2.7 V
UNIT
MIN MAX
150
MIN
MAX
f
t
Clock frequency
Pulse duration
150
MHz
ns
clock
LE high
3.3
3.3
2.9
2.9
1.4
2.9
0.4
1.6
3.3
3.3
2.9
2.9
0.5
2.3
0.4
1.6
w
CLK high or low
A before CLKAB↓
B before CLKBA↓
t
t
Setup time
Hold time
ns
ns
su
CLK high
CLK low
A or B before LE↓
A or B after CLK↓
A or B after LE↓
h
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
V
= 3.3 V
CC
0.3 V
V
= 2.7 V
MAX
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
†
MIN TYP
MAX
MIN
f
t
t
t
t
t
t
t
t
t
t
150
150
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
1.3
1.3
1.5
1.5
1.3
1.3
1.3
1.3
1.7
1.7
2.8
2.6
3.8
3.8
3.6
3.5
3.6
3.6
4.5
4.1
3.7
3.7
5.1
5.1
5
4
4
B or A
A or B
A or B
A or B
A or B
A or B
5.7
5.7
5.9
5.9
5.5
5.5
6.3
6.3
LEBA or LEAB
ns
ns
ns
ns
CLKBA or CLKAB
OEBA or OEAB
OEBA or OEAB
5
4.8
4.8
5.8
5.8
†
All typical values are at V
CC
= 3.3 V, T = 25°C.
A
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢋꢌ ꢍꢎ
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ꢘꢔ ꢆ ꢇ ꢏ ꢌꢀꢆꢑꢆ ꢍ ꢙꢕꢆ ꢎ ꢕꢆꢀ
SCBS783 − NOVEMBER 2003
PARAMETER MEASUREMENT INFORMATION
6 V
TEST
S1
S1
Open
500 Ω
From Output
Under Test
t
/t
PHL PLH
Open
6 V
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
GND
L
PHZ PZH
500 Ω
(see Note A)
2.7 V
0 V
Timing Input
Data Input
1.5 V
LOAD CIRCUIT
t
w
t
t
su
h
2.7 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
t
PHL
t
t
PLZ
PLH
PHL
PZL
Output
Waveform 1
S1 at 6 V
V
3 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
+ 0.3 V
OL
V
OL
(see Note B)
V
OL
t
t
t
PZH
PHZ
PLH
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
− 0.3 V
OH
1.5 V
1.5 V
Output
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
CLVTH16500IDGGREP
V62/04713-01XE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
DGG
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVTH16500-EP :
Catalog: SN74LVTH16500
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
CLVTH16500IDGGREP TSSOP
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DGG 56
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 41.0
CLVTH16500IDGGREP
2000
Pack Materials-Page 2
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相关型号：
SN74LVTH16500DLG4
LVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, SSOP-56
TI
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