SN74LVTH16646 [TI]
3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS; 3.3 -V ABT 16位总线，三态输出收发器
| 型号： | SN74LVTH16646 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总10页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LVTH16646, SN74LVTH16646
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS698E – JULY 1997 – REVISED APRIL 1999
SN54LVTH16646 . . . WD PACKAGE
SN74LVTH16646 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1DIR
1CLKAB
1SAB
GND
1OE
2
1CLKBA
1SBA
GND
1B1
3
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
4
5
1A1
3.3-V V
)
6
1A2
1B2
CC
7
V
V
Support Unregulated Battery Operation
Down to 2.7 V
CC
CC
8
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
9
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
= 3.3 V, T = 25°C
CC
A
I
and Power-Up 3-State Support Hot
off
Insertion
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 500 mA Per
JESD 17
V
V
CC
CC
2A7
2A8
GND
2B7
2B8
GND
2SBA
2CLKBA
2OE
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
2SAB
2CLKAB
2DIR
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’LVTH16646 devices are 16-bit bus transceivers designed for low-voltage (3.3-V) V
the capability to provide a TTL interface to a 5-V system environment.
operation, but with
CC
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked
into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1
illustrates the four fundamental bus-management functions that can be performed with the ’LVTH16646
devices.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH16646, SN74LVTH16646
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS698E – JULY 1997 – REVISED APRIL 1999
description (continued)
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The
select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry
used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition
between stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation
mode (OE high), A data can be stored in one register and/or B data can be stored in the other register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
through a pullup resistor;
CC
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54LVTH16646 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH16646 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR FUNCTION
OE
X
X
H
H
L
DIR
X
CLKAB
CLKBA
SAB
X
SBA
X
A1–A8
Input
B1–B8
†
†
†
↑
X
Unspecified
Store A, B unspecified
Store B, A unspecified
Store A and B data
†
X
X
↑
X
X
Unspecified
Input
X
↑
H or L
X
↑
H or L
X
X
X
Input
Input
X
X
X
Input disabled
Output
Input disabled
Input
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B Bus
Stored A data to bus
L
X
L
L
L
X
H or L
X
X
H
Output
Input
L
H
H
X
L
X
Input
Output
L
H or L
X
H
X
Input
Output
†
The data-output functions may be enabled or disabled by various signals at OE or DIR. Data-input functions always are enabled, i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH16646, SN74LVTH16646
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS698E – JULY 1997 – REVISED APRIL 1999
DIR CLKAB CLKBA SAB
SBA
L
DIR
H
CLKAB CLKBA SAB
SBA
X
OE
L
OE
L
L
X
X
X
X
X
L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
DIR CLKAB CLKBA SAB
SBA
X
DIR
L
CLKAB CLKBA SAB
SBA
H
OE
X
OE
L
X
L
L
X
H
X
X
X
X
↑
X
X
X
↑
X
L
H
X
X
X
X
H
X
↑
↑
TRANSFER STORED DATA
TO A AND/OR B
STORAGE FROM
A, B, OR A AND B
Figure 1. Bus-Management Functions
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH16646, SN74LVTH16646
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS698E – JULY 1997 – REVISED APRIL 1999
†
logic symbol
56
1OE
G3
1
1DIR
3 EN1 [BA]
3 EN2 [AB]
55
1CLKBA
54
C4
G5
1SBA
2
1CLKAB
3
C6
1SAB
29
G7
G10
2OE
28
2DIR
10 EN8 [BA]
10 EN9 [AB]
30
2CLKBA
31
C11
G12
2SBA
27
2CLKAB
26
C13
2SAB
G14
52
4D
2
1B1
≥1
5
5
1A1
1
5 1
≥1
6D
7
7
1
6
1A2
8
51
49
48
47
45
44
43
42
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
1A3
9
1A4
10
1A5
12
1A6
13
1A7
14
1A8
≥1
8
12 11D
12 1
15
2A1
13D 14
1 14
≥1
9
16
2A2
17
41
40
38
37
36
34
33
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2A3
19
2A4
20
2A5
21
2A6
23
2A7
24
2A8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH16646, SN74LVTH16646
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS698E – JULY 1997 – REVISED APRIL 1999
logic diagram (positive logic)
56
1OE
1
1DIR
55
1CLKBA
54
1SBA
2
1CLKAB
3
1SAB
One of Eight Channels
1D
C1
5
1A1
52
1B1
1D
C1
To Seven Other Channels
29
2OE
28
2DIR
30
2CLKBA
31
2SBA
27
2CLKAB
26
2SAB
One of Eight Channels
1D
C1
15
2A1
42
2B1
1D
C1
To Seven Other Channels
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH16646, SN74LVTH16646
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS698E – JULY 1997 – REVISED APRIL 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I : SN54LVTH16646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74LVTH16646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, I (see Note 2): SN54LVTH16646 . . . . . . . . . . . . . . . . . . . . . 48 mA
O
SN74LVTH16646 . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVTH16646 SN74LVTH16646
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
5.5
–24
48
0.8
5.5
–32
64
V
IL
V
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
I
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
–55
200
–40
CC
T
A
Operating free-air temperature
125
85
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH16646, SN74LVTH16646
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS698E – JULY 1997 – REVISED APRIL 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH16646
SN74LVTH16646
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
= 2.7 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
CC
CC
I
= 2.7 V to 3.6 V,
= 2.7 V,
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –8 mA
= –24 mA
= –32 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 48 mA
= 64 mA
V
–0.2
V
–0.2
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
CC
2.4
CC
2.4
V
V
OH
2
V
= 3 V
CC
CC
2
0.2
0.5
0.2
0.5
0.4
0.5
V
= 2.7 V
0.4
V
OL
0.5
V
CC
= 3 V
0.55
0.55
±1
V
V
= 3.6 V,
V = V
I
or GND
±1
10
20
1
CC
CC
Control inputs
= 0 or 3.6 V,
V = 5.5 V
I
10
CC
I
I
V = 5.5 V
I
20
µA
‡
V
CC
= 3.6 V
V = V
I CC
1
A or B ports
A or B ports
V = 0
I
–5
–5
I
I
V
V
= 0,
V or V = 0 to 4.5 V
±100
µA
µA
off
CC
I
O
V = 0.8 V
I
75
75
= 3 V
CC
V = 2 V
I
–75
–75
I(hold)
§
V
V
= 3.6 V ,
V = 0 to 3.6 V
±500
±100
CC
I
= 0 to 1.5 V, V = 0.5 V to 3 V,
OE = don’t care
CC
O
±100*
±100*
µA
µA
I
I
OZPU
V
= 1.5 V to 0, V = 0.5 V to 3 V,
CC
OE = don’t care
O
±100
OZPD
Outputs high
Outputs low
0.19
5
0.19
5
V
= 3.6 V, I = 0,
O
CC
V = V
I
mA
CC
or GND
CC
I
Outputs disabled
0.19
0.19
V
= 3 V to 3.6 V, One input at V – 0.6 V,
CC
CC
Other inputs at V
¶
0.2
0.2
mA
∆I
CC
or GND
CC
C
C
V = 3 V or 0
4
4
pF
pF
i
I
V
O
= 3 V or 0
10
10
io
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
‡
§
¶
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
or GND
Unused pins at V
CC
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH16646, SN74LVTH16646
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS698E – JULY 1997 – REVISED APRIL 1999
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 2)
SN54LVTH16646
= 3.3 V
SN74LVTH16646
= 3.3 V
V
CC
V
CC
V
= 2.7 V
V
= 2.7 V
UNIT
CC
CC
± 0.3 V
± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
f
t
Clock frequency
150
150
150
150
MHz
ns
clock
Pulse duration, CLK high or low
3.3
1.2
2
3.3
1.5
2.8
0
3.3
1.2
2
3.3
1.5
2.8
0
w
Data high
Data low
Data high
Data low
Setup time,
A or B before CLKAB↑ or CLKBA↑
t
ns
ns
su
h
0.5
0.5
0.5
0.5
Hold time,
A or B after CLKAB↑ or CLKBA↑
t
0.5
0.5
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 2)
SN54LVTH16646
= 3.3 V
SN74LVTH16646
FROM
(INPUT)
TO
(OUTPUT)
V
V
= 3.3 V
V
CC
CC
V
CC
= 2.7 V
= 2.7 V
MAX
PARAMETER
UNIT
CC
± 0.3 V
± 0.3 V
†
MIN
150
1.3
1.3
1
MAX
MIN
MAX
MIN TYP
MAX
MIN
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
150
150
150
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
4.5
4.5
3.6
3.6
4.7
4.7
4.5
4.5
5.8
5.6
4.6
4.6
6
5
5
1.3
1.3
1
2.8
2.8
2.4
2.1
2.8
3
4.2
4.2
3.4
3.4
4.5
4.5
4.3
4.3
5.6
5.4
4.4
4.4
5.7
5.2
4.7
4.7
3.9
3.9
5.4
5.4
5.2
5.2
6.1
6.1
5.3
5.3
6.8
5.7
CLKBA or
CLKAB
A or B
B or A
A or B
A or B
A or B
A or B
A or B
4.1
4.1
5.6
5.6
5.4
5.4
6.3
6.3
5.5
5.5
7.1
6
A or B
ns
ns
ns
ns
ns
ns
1
1
1
1
‡
SBA or SAB
1
1
1
1
2.5
2.6
4
OE
OE
DIR
1
1
2
2
2
2
3.6
3
1
1
1
1
3
1.5
1.5
1.5
1.5
3.9
3.6
DIR
5.5
†
‡
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH16646, SN74LVTH16646
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS698E – JULY 1997 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
6 V
Open
GND
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
6 V
PLH PHL
t
/t
PLZ PZL
C
= 50 pF
t
/t
GND
L
PHZ PZH
500 Ω
(see Note A)
2.7 V
0 V
Timing Input
Data Input
1.5 V
LOAD CIRCUIT
t
w
t
t
h
su
2.7 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
t
PHL
t
t
PLZ
PLH
PZL
Output
Waveform 1
S1 at 6 V
V
3 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
+ 0.3 V
OL
V
OL
(see Note B)
V
OL
t
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
9
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