SN74LVTH574IPWREP [TI]
3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS;
| 型号： | SN74LVTH574IPWREP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS 驱动 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总9页 (文件大小：434K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCBS774 − NOVEMBER 2003
D
D
D
D
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Enhanced Diminishing Manufacturing
Sources (DMS) Support
D
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
Enhanced Product-Change Notification
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
†
Qualification Pedigree
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With 3.3-V
PW PACKAGE
(TOP VIEW)
V
)
CC
D
D
D
Supports Unregulated Battery Operation
Down To 2.7 V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
A
I
and Power-Up 3-State Support Hot
off
Insertion
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
GND
description/ordering information
This octal flip-flop is designed specifically for low-voltage (3.3-V) V
a TTL interface to a 5-V system environment.
operation, but with the capability to provide
CC
The eight flip-flops of the SN74LVTH574 are edge-triggered D-type flip-flops. On the positive transition of the
clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
T
A
PACKAGE
−40°C to 85°C
TSSOP − PW Tape and reel
SN74LVTH574IPWREP
LH574EP
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢂ ꢃꢉꢊꢋ
ꢌꢍ ꢌꢉꢅ ꢎ ꢏ ꢆ ꢐꢑ ꢆꢎꢄ ꢊ ꢒꢓ ꢊꢉꢆ ꢔꢕ ꢓꢓ ꢊꢔ ꢊꢒ ꢒ ꢉꢆꢖ ꢋꢊ ꢗ ꢄꢕ ꢋꢉꢗ ꢄ ꢐ ꢋ
ꢘꢕ ꢆ ꢇ ꢌ ꢉꢀꢆꢎꢆ ꢊ ꢐꢙꢆ ꢋꢙ ꢆꢀ
SCBS774 − NOVEMBER 2003
description/ordering information (continued)
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup
or pulldown resistors with the bus-hold circuitry is not recommended.
This device is fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
↑
H
L
L
L
H or L
X
X
X
Q
0
H
Z
logic diagram (positive logic)
1
OE
11
CLK
C1
19
1Q
2
1D
1D
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I
Current into any output in the high state, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
O
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Package thermal impedance, θ (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
JA
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCBS774 − NOVEMBER 2003
recommended operating conditions (see Note 4)
MIN
2.7
2
MAX
UNIT
V
V
V
V
V
Supply voltage
3.6
CC
High-level input voltage
Low-level input voltage
Input voltage
V
IH
0.8
5.5
−32
64
V
IL
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
200
−40
CC
T
A
Operating free-air temperature
85
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
= 2.7 V,
I = −18 mA
−1.2
V
IK
CC
CC
CC
CC
I
= 2.7 V to 3.6 V,
= 2.7 V,
I
I
I
I
I
I
I
I
= −100 µA
= −8 mA
= −32 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 64 mA
V
−0.2
OH
OH
OH
OL
OL
OL
OL
OL
CC
2.4
V
OH
V
V
= 3 V,
2
0.2
0.5
0.4
0.5
0.55
10
V
= 2.7 V
CC
CC
V
OL
V
= 3 V
V
V
= 0 or 3.6 V,
= 3.6 V,
V = 5.5 V
I
CC
Control inputs
V = V
or GND
1
CC
I
CC
I
I
µA
V = V
1
I
CC
Data inputs
V
V
= 3.6 V
= 0,
CC
V = 0
I
−5
I
I
V or V = 0 to 4.5 V
100
µA
µA
off
CC
I
O
V = 0.8 V
I
75
V
CC
= 3 V
V = 2 V
I
−75
Data inputs
I(hold)
‡
V
CC
V
CC
V
CC
V
CC
= 3.6 V ,
V = 0 to 3.6 V
500
5
I
I
I
I
= 3.6 V,
= 3.6 V,
V
= 3 V
µA
µA
µA
OZH
O
O
V
= 0.5 V
−5
OZL
= 0 to 1.5 V, V = 0.5 V to 3 V, OE = don’t care
O
100
OZPU
V
= 1.5 V to 0, V = 0.5 V to 3 V, OE = don’t care
O
100
0.19
5
µA
I
CC
OZPD
Outputs high
Outputs low
I
V
= 3.6 V, I = 0, V = V
CC
or GND
mA
CC
§
CC
CC
O
I
Outputs disabled
0.19
0.2
V
= 3 V to 3.6 V, One input at V
CC
− 0.6 V, Other inputs at V
or GND
mA
pF
pF
∆I
CC
CC
C
C
V = 3 V or 0
I
3
7
i
V
O
= 3 V or 0
o
†
‡
§
All typical values are at V
CC
= 3.3 V, T = 25°C.
A
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
or GND.
CC
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢂ ꢃꢉꢊꢋ
ꢌꢍ ꢌꢉꢅ ꢎ ꢏ ꢆ ꢐꢑ ꢆꢎꢄ ꢊ ꢒꢓ ꢊꢉꢆ ꢔꢕ ꢓꢓ ꢊꢔ ꢊꢒ ꢒ ꢉꢆꢖ ꢋꢊ ꢗ ꢄꢕ ꢋꢉꢗ ꢄ ꢐ ꢋ
ꢘꢕ ꢆ ꢇ ꢌ ꢉꢀꢆꢎꢆ ꢊ ꢐꢙꢆ ꢋꢙ ꢆꢀ
SCBS774 − NOVEMBER 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V = 3.3 V
CC
0.3 V
V
CC
= 2.7 V
UNIT
MIN MAX
150
MIN
MAX
f
t
t
t
Clock frequency
150
MHz
ns
clock
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
3.3
2
3.3
2.4
0
w
ns
su
h
0.3
ns
switching characteristics over recommended free-air temperature, C = 50 pF (unless otherwise
L
noted) (see Figure 1)
V
= 3.3 V
CC
0.3 V
V
= 2.7 V
MAX
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
†
MIN TYP
MAX
MIN
f
t
t
t
t
t
t
150
150
MHz
ns
max
PLH
PHL
PZH
PZL
PHZ
PLZ
1.8
3
3
4.5
4.5
4.8
4.8
4.8
4.4
5.3
5.3
5.9
5.9
5.1
4.4
CLK
OE
Q
Q
Q
1.8
1.5
1.5
2
3.2
3.5
3.5
3.2
ns
ns
OE
2
†
All typical values are at V
CC
= 3.3 V, T = 25°C.
A
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCBS774 − NOVEMBER 2003
PARAMETER MEASUREMENT INFORMATION
6 V
TEST
S1
S1
Open
GND
500 Ω
From Output
Under Test
t
/t
PLH PHL
Open
6 V
t
/t
PLZ PZL
C
= 50 pF
t
/t
GND
L
PHZ PZH
500 Ω
(see Note A)
2.7 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
PLZ
PZL
t
t
t
PHL
PLH
PHL
Output
Waveform 1
S1 at 6 V
3 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
t
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
t
PZH
PHZ
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
− 0.3 V
OH
1.5 V
1.5 V
Output
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
SN74LVTH574IPWREP
V62/04679-01XE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
PW
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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OTHER QUALIFIED VERSIONS OF SN74LVTH574-EP :
Catalog: SN74LVTH574
Military: SN54LVTH574
•
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Military - QML certified for Military and Defense Applications
•
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVTH574IPWREP TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 20
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
SN74LVTH574IPWREP
2000
Pack Materials-Page 2
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