SN74LVTH646DBRG4 [TI]

LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SSOP-24;


型号：	SN74LVTH646DBRG4
厂家：	TEXAS INSTRUMENTS
描述：	LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SSOP-24 信息通信管理光电二极管输出元件逻辑集成电路触发器
文件：	总22页 (文件大小：1000K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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ꢋ ꢌꢋ ꢍꢅ ꢎꢏꢆ ꢐ ꢑꢆꢎꢄ ꢏꢒꢀ ꢆ ꢓꢎꢁꢀ ꢑꢔꢕ ꢅꢔꢓꢀ ꢎꢁꢖ ꢓꢔ ꢗ ꢕꢀ ꢆꢔ ꢓ

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SCBS705H − AUGUST 1997 − REVISED MAY 2004

Support Mixed-Mode Signal Operation

(5-V Input and Output Voltages With

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

3.3-V V

)

Support Unregulated Battery Operation

Down to 2.7 V

Latch-Up Performance Exceeds 500 mA Per

JESD 17

Typical V

<0.8 V at V

(Output Ground Bounce)

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

OLP

= 3.3 V, T = 25°C

and Power-Up 3-State Support Hot

off

Insertion

SN54LVTH646 . . . JT OR W PACKAGE

SN74LVTH646 . . . DB, DGV, DW, NS, OR PW PACKAGE

(TOP VIEW)

SN54LVTH646 . . . FK PACKAGE

(TOP VIEW)

CLKAB

SAB

DIR

GND

CLKBA

SBA

28 27 26

12 13 14 15 16 17 18

NC − No internal connection

description/ordering information

These bus transceivers and registers are designed specifically for low-voltage (3.3-V) V

the capability to provide a TTL interface to a 5-V system environment.

operation, but with

ORDERING INFORMATION

ORDERABLE

†

PACKAGE

TOP-SIDE MARKING

PART NUMBER

SN74LVTH646DW

SN74LVTH646DWR

SN74LVTH646NSR

SN74LVTH646DBR

SN74LVTH646PW

SN74LVTH646PWR

SN74LVTH646DGVR

SNJ54LVTH646JT

SNJ54LVTH646W

SNJ54LVTH646FK

Tube

SOIC − DW

LVTH646

Tape and reel

Tube

SOP − NS

LVTH646

LXH646

SSOP − DB

−40°C to 85°C

TSSOP − PW

LXH646

Tape and reel

Tube

TVSOP − DGV

CDIP − JT

LXH646

SNJ54LVTH646JT

SNJ54LVTH646W

SNJ54LVTH646FK

−55°C to 125°C

CFP − W

Tube

LCCC − FK

Tube

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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ꢐ ꢛ ꢦ ꢞ ꢝꢩ ꢤꢣ ꢡꢢ ꢣꢝ ꢟꢦ ꢨꢚ ꢠꢛ ꢡ ꢡꢝ ꢯꢕ ꢄꢍ ꢙꢓ ꢰ ꢍꢋꢱꢂ ꢋꢂꢉ ꢠꢨꢨ ꢦꢠ ꢞ ꢠ ꢟꢥ ꢡꢥꢞ ꢢ ꢠ ꢞ ꢥ ꢡꢥ ꢢꢡꢥ ꢩ

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ꢡ ꢥ ꢢ ꢡꢚ ꢛꢮ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢌ

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ꢤ ꢛꢨ ꢥꢢꢢ ꢝ ꢡꢪꢥ ꢞ ꢬꢚ ꢢꢥ ꢛ ꢝꢡꢥ ꢩꢌ ꢐ ꢛ ꢠꢨ ꢨ ꢝ ꢡꢪꢥ ꢞ ꢦꢞ ꢝ ꢩꢤꢣ ꢡꢢ ꢉ ꢦꢞ ꢝ ꢩꢤꢣ ꢡꢚꢝ ꢛ

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCBS705H − AUGUST 1997 − REVISED MAY 2004

description/ordering information (continued)

The ’LVTH646 devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for

multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B

bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input.

Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ’LVTH646.

Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the

transceiver mode, data present at the high-impedance port can be stored in either register or in both.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The

direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high),

A data can be stored in one register and/or B data can be stored in the other register.

When an output function is disabled, the input function still is enabled and can be used to store and transmit

data. Only one of the two buses, A or B, can be driven at a time.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup

or pulldown resistors with the bus-hold circuitry is not recommended.

To ensure the high-impedance state during power up or power down, OE should be tied to V

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

through a pullup

These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry

off

disables the outputs, preventing damaging current backflow through the devices when they are powered down.

The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,

which prevents driver conflict.

FUNCTION TABLE

INPUTS

DATA I/Os

OPERATION OR FUNCTION

DIR

CLKAB

CLKBA

SAB

SBA

A1−A8

Input

B1−B8

†

↑

Unspecified

Store A, B unspecified

†

↑

Unspecified

Input

Store B, A unspecified

↑

H or L

↑

H or L

Input

Store A and B data

Isolation, hold storage

Real-time B data to A bus

Stored B data to A bus

Real-time A data to B bus

Stored A data to B bus

Input disabled

Output

Input disabled

Input

H or L

Output

Input

Output

H or L

Input

Output

†

The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e., data at

the bus terminals is stored on every low-to-high transition of the clock inputs.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCBS705H − AUGUST 1997 − REVISED MAY 2004

SBA

DIR

CLKAB CLKBA SAB

SBA

DIR CLKAB CLKBA SAB

REAL-TIME TRANSFER

BUS B TO BUS A

REAL-TIME TRANSFER

BUS A TO BUS B

DIR

SBA

DIR CLKAB CLKBA SAB

SBA

CLKAB CLKBA SAB

↑

H or L

↑

STORAGE FROM

A, B, OR A AND B

TRANSFER STORED DATA

TO A AND/OR B

Pin numbers shown are for the DB, DGV, DW, JT, NS, PW, and W packages.

Figure 1. Bus-Management Functions

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCBS705H − AUGUST 1997 − REVISED MAY 2004

logic diagram (positive logic)

DIR

CLKBA

SBA

CLKAB

SAB

One of Eight Channels

To Seven Other Channels

Pin numbers shown are for the DB, DGV, DW, JT, NS, PW, and W packages.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCBS705H − AUGUST 1997 − REVISED MAY 2004

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Voltage range applied to any output in the high-impedance

or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . −0.5 V to V

+ 0.5 V

Current into any output in the low state, I : SN54LVTH646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA

SN74LVTH646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA

Current into any output in the high state, I (see Note 2): SN54LVTH646 . . . . . . . . . . . . . . . . . . . . . . . 48 mA

SN74LVTH646 . . . . . . . . . . . . . . . . . . . . . . . 64 mA

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

Output clamp current, I

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W

DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W

DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W

NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C/W

PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and V > V

3. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 4)

SN54LVTH646 SN74LVTH646

UNIT

MIN

2.7

MAX

MIN

2.7

MAX

Supply voltage

3.6

High-level input voltage

Low-level input voltage

Input voltage

0.8

5.5

−24

0.8

5.5

−32

High-level output current

Low-level output current

Input transition rise or fall rate

Power-up ramp rate

ns/V

µs/V

°C

∆t/∆v

∆t/∆V

Outputs enabled

200

−55

200

−40

Operating free-air temperature

125

NOTE 4: All unused control inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCBS705H − AUGUST 1997 − REVISED MAY 2004

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54LVTH646

SN74LVTH646

PARAMETER

TEST CONDITIONS

I = −18 mA

UNIT

†

MIN TYP

MAX

MIN TYP

MAX

= 2.7 V,

−1.2

= 2.7 V to 3.6 V,

= 2.7 V,

= −100 µA

= −8 mA

= −24 mA

= −32 mA

= 100 µA

= 24 mA

= 16 mA

= 32 mA

= 48 mA

= 64 mA

−0.2

2.4

−0.2

2.4

= 3 V

0.2

0.5

0.2

0.5

0.4

0.5

= 2.7 V

0.4

0.5

= 3 V

0.55

= 3.6 V,

V = V

I CC

or GND

Control inputs

= 0 or 3.6 V,

V = 5.5 V

µA

‡

V = V

= 3.6 V

A or B ports

V = 0

−5

100

= 0,

V or V = 0 to 4.5 V

µA

off

V = 0.8 V

= 3 V

V = 2 V

−75

A or B ports

I(hold)

= 3.6 V ,

V = 0 to 3.6 V

500

100

= 0 to 1.5 V, V = 0.5 V to 3 V,

OE = don’t care

100

µA

OZPU

= 1.5 V to 0, V = 0.5 V to 3 V,

OE = don’t care

100

OZPD

Outputs high

Outputs low

0.19

= 3.6 V,

= 0,

V = V

or GND

Outputs disabled

0.19

= 3 V to 3.6 V, One input at V − 0.6 V,

Other inputs at V

∆I

0.2

or GND

V = 3 V or 0

= 3 V or 0

†

‡

All typical values are at V

= 3.3 V, T = 25°C.

Unused terminals at V

or GND

This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V

or GND.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCBS705H − AUGUST 1997 − REVISED MAY 2004

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (see Figure 2)

SN54LVTH646

SN74LVTH646

= 3.3 V

= 2.7 V

UNIT

0.3 V

MIN MAX

150

0.3 V

MIN MAX

150

MIN

MAX

MIN

MAX

Clock frequency

150

MHz

clock

Pulse duration, CLK high or low

3.3

1.3

1.9

1.2

3.3

1.6

2.6

1.2

3.3

1.2

1.6

0.8

3.3

1.5

2.2

0.8

Data high

Data low

Setup time,

A or B before CLKAB↑ or CLKBA↑

Hold time, A or B after CLKAB↑ or CLKBA↑

switching characteristics over recommended operating free-air temperature range, C = 50 pF

(unless otherwise noted) (see Figure 2)

SN54LVTH646

= 3.3 V

SN74LVTH646

= 3.3 V

FROM

(INPUT)

(OUTPUT)

= 2.7 V

MAX

= 2.7 V

MAX

PARAMETER

UNIT

0.3 V

†

MIN

MAX

MIN

MIN TYP

MAX

MIN

150

MHz

max

PLH

PHL

PLH

PHL

PLH

PHL

PZH

PZL

PHZ

PLZ

PZH

PZL

PHZ

PLZ

5.3

5.9

5.6

1.8

1.3

1.5

1.1

2.3

1.3

1.5

3.1

2.3

2.4

4.7

3.5

4.9

5.2

5.5

5.2

5.6

4.1

CLKBA or

CLKAB

A or B

B or A

A or B

1.5

4.9

4.8

5.3

5.4

5.6

6.3

5.6

6.7

7.2

6.1

A or B

SBA or SAB

1.2

6.3

6.7

6.5

6.8

8.1

6.6

‡

1.3

3.3

3.1

3.4

3.9

6.5

6.1

5.9

6.6

6.7

6.3

1.7

2.2

1.2

1.1

1.4

3.4

3.6

3.2

3.8

DIR

†

‡

All typical values are at V

= 3.3 V, T = 25°C.

These parameters are measured with the internal output state of the storage register opposite that of the bus input.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ

ꢁ

ꢂ

ꢃꢄꢅ

ꢆ

ꢇ

ꢈ

ꢃ

ꢈꢉ

ꢀ

ꢁ

ꢊ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈꢃ

ꢈ

ꢋ

ꢌ

ꢋ

ꢍ

ꢅ

ꢎ

ꢏ

ꢆ

ꢐ

ꢑ

ꢆꢎ

ꢄ

ꢏ

ꢒ

ꢀ

ꢆꢓ

ꢎ

ꢁ

ꢀ

ꢑ

ꢔꢕ

ꢅ

ꢔ

ꢓ

ꢀ

ꢎ

ꢁ

ꢖ

ꢓ

ꢔ

ꢗꢕ

ꢀ

ꢆ

ꢔ

ꢓ

ꢀ

ꢘ

ꢕ

ꢆ

ꢇ

ꢋ

ꢍ

ꢀ

ꢆ

ꢎ

ꢆ

ꢔ

ꢐ

ꢒ

ꢆ

ꢙ

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ꢀ

SCBS705H − AUGUST 1997 − REVISED MAY 2004

PARAMETER MEASUREMENT INFORMATION

6 V

TEST

Open

GND

500 Ω

From Output

Under Test

Open

6 V

PLH PHL

PLZ PZL

= 50 pF

GND

500 Ω

PHZ PZH

(see Note A)

2.7 V

0 V

LOAD CIRCUIT

1.5 V

Timing Input

Data Input

2.7 V

0 V

2.7 V

0 V

Input

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

2.7 V

0 V

2.7 V

Output

Control

1.5 V

Input

0 V

PLZ

PZL

PLH

PHL

Output

Waveform 1

S1 at 6 V

3 V

1.5 V

Output

+ 0.3 V

(see Note B)

PHL

PLH

PZH

PHZ

Output

Waveform 2

S1 at GND

− 0.3 V

1.5 V

Output

≈0 V

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A.

C includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

D. The outputs are measured one at a time, with one transition per measurement.

E. All parameters and waveforms are not applicable to all devices.

Figure 2. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2014

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

5962-9674801Q3A

ACTIVE

LCCC

TBD

POST-PLATE

N / A for Pkg Type

-55 to 125

5962-

9674801Q3A

SNJ54LVTH

646FK

5962-9674801QKA

5962-9674801QLA

ACTIVE

CFP

TBD

A42

N / A for Pkg Type

-55 to 125

5962-9674801QK

SNJ54LVTH646W

CDIP

5962-9674801QL

SNJ54LVTH646JT

SN74LVTH646DBLE

SN74LVTH646DW

OBSOLETE

ACTIVE

SSOP

SOIC

Call TI

-40 to 85

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

LVTH646

SN74LVTH646DWG4

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 85

SN74LVTH646PWLE

SN74LVTH646PWR

OBSOLETE

ACTIVE

TSSOP

TBD

Call TI

-40 to 85

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

LXH646

SNJ54LVTH646FK

ACTIVE

LCCC

TBD

POST-PLATE

N / A for Pkg Type

-55 to 125

5962-

9674801Q3A

SNJ54LVTH

646FK

SNJ54LVTH646JT

SNJ54LVTH646W

ACTIVE

CDIP

CFP

TBD

A42

N / A for Pkg Type

-55 to 125

5962-9674801QL

SNJ54LVTH646JT

5962-9674801QK

SNJ54LVTH646W

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2014

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54LVTH646, SN74LVTH646 :

Catalog: SN74LVTH646

•

Enhanced Product: SN74LVTH646-EP, SN74LVTH646-EP

•

Military: SN54LVTH646

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2014

Enhanced Product - Supports Defense, Aerospace and Medical Applications

Military - QML certified for Military and Defense Applications

•

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74LVTH646PWR

TSSOP

2000

330.0

16.4

6.95

8.3

1.6

8.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

TSSOP PW 24

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 38.0

SN74LVTH646PWR

2000

Pack Materials-Page 2

MECHANICAL DATA

MCER004A – JANUARY 1995 – REVISED JANUARY 1997

JT (R-GDIP-T**)

CERAMIC DUAL-IN-LINE

24 LEADS SHOWN

PINS **

DIM

1.280

(32,51) (37,08)

1.460

A MAX

1.240

(31,50) (36,58)

1.440

A MIN

B MAX

B MIN

0.300

(7,62)

0.291

(7,39)

0.070 (1,78)

0.030 (0,76)

0.245

(6,22)

0.285

(7,24)

0.320 (8,13)

0.290 (7,37)

0.015 (0,38) MIN

0.100 (2,54) MAX

0.200 (5,08) MAX

Seating Plane

0.130 (3,30) MIN

0.023 (0,58)

0.015 (0,38)

0°–15°

0.014 (0,36)

0.008 (0,20)

0.100 (2,54)

4040110/C 08/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification.

E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

0,15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

0,25

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

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