SN74LXC1T45DRL [TI]
SN74LXC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Level Shifting;
| 型号： | SN74LXC1T45DRL |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SN74LXC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Level Shifting |
| 文件： | 总30页 (文件大小：1178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LXC1T45
SCES934A – SEPTEMBER 2021 – REVISED DECEMBER 2021
SN74LXC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Level
Shifting
1 Features
3 Description
•
Fully configurable dual-rail design allows each port
to operate from 1.1 V to 5.5 V
The SN74LXC1T45 is
a
1-bit, dual-supply
noninverting bidirectional voltage level translation
device. The I/O pin A and control pin (DIR) are
referenced to VCCA logic levels, and the I/O pin B are
referenced to VCCB logic levels. The A pin is able to
accept I/O voltages ranging from 1.1 V to 5.5 V, while
the B pin can accept I/O voltages from 1.1 V to 5.5 V.
A high on DIR allows data transmission from A to B
and a low on DIR allows data transmission from B to
A. See Device Functional Modes for a summary of the
operation of the control logic.
•
•
•
•
Robust, glitch-free power supply sequencing
Up to 420-Mbps support for 3.3 V to 5.0 V
Schmitt-trigger inputs allow for slow or noisy inputs
I/O's with integrated dynamic pull-down resistors
help reduce external component count
Control inputs with integrated static pull-down
resistors allow for floating control inputs
High drive strength (up to 32 mA at 5 V)
Low power consumption
•
•
•
– 3-µA maximum (25°C)
Device Information (1)
– 6-µA maximum (–40°C to 125°C)
VCC isolation and Vcc disconnect (Ioff-float) feature
– If either VCC supply is < 100 mV or
disconnected, all I/O's get pulled-down and
then become high-impedance
Ioff supports partial-power-down mode operation
Compatible with LVC family level shifters
Control logic (DIR and OE) are referenced to VCCA
Operating temperature from –40°C to +125°C
Latch-up performance exceeds 100 mA per JESD
78, class II
PART NUMBER
SN74LXC1T45DRL
SN74LXC1T45DRY
SN74LXC1T45DBV
SN74LXC1T45DCK
SN74LXC1T45DTQ
PACKAGE
BODY SIZE (NOM)
1.60 mm × 1.20 mm
1.45 mm × 1.00 mm
2.90 mm × 1.60 mm
2.00 mm × 1.25 mm
1.00 mm × 0.80 mm
•
SOT (6)
SON (6)
SOT-23 (6)
SC70 (6)
X2SON (6)
•
•
•
•
•
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VCCA
VCCB
•
ESD protection exceeds JESD 22
– 4000-V human-body model
– 1000-V charged-device model
DIR
2 Applications
•
•
•
•
Eliminate slow or noisy input signals
Driving indicator LEDs or buzzers
Debouncing a mechanical switch
General purpose I/O level shifting
B1
A1
SN74LXC1T45 Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LXC1T45
SCES934A – SEPTEMBER 2021 – REVISED DECEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics, VCCA = 1.2 ± 0.1 V ........... 9
6.7 Switching Characteristics, VCCA = 1.5 ± 0.1 V ......... 10
6.8 Switching Characteristics, VCCA = 1.8 ± 0.15 V ....... 11
6.9 Switching Characteristics, VCCA = 2.5 ± 0.2 V ......... 12
6.10 Switching Characteristics, VCCA = 3.3 ± 0.3 V ....... 13
6.11 Switching Characteristics, VCCA = 5.0 ± 0.5 V ....... 14
6.12 Switching Characteristics: Tsk, TMAX ......................15
6.13 Operating Characteristics....................................... 15
6.14 Typical Characteristics............................................16
7 Parameter Measurement Information..........................17
7.1 Load Circuit and Voltage Waveforms........................17
8 Detailed Description......................................................19
8.1 Overview...................................................................19
8.2 Functional Block Diagram.........................................19
8.3 Feature Description...................................................19
8.4 Device Functional Modes..........................................22
9 Application and Implementation..................................23
9.1 Application Information............................................. 23
9.2 Enable Times............................................................ 23
9.3 Typical Application.................................................... 23
10 Power Supply Recommendations..............................24
11 Layout...........................................................................24
11.1 Layout Guidelines................................................... 24
11.2 Layout Example...................................................... 24
12 Device and Documentation Support..........................25
12.1 Device Support....................................................... 25
12.2 Documentation Support.......................................... 25
12.3 Receiving Notification of Documentation Updates..25
12.4 Support Resources................................................. 25
12.5 Trademarks.............................................................25
12.6 Electrostatic Discharge Caution..............................25
12.7 Glossary..................................................................25
13 Mechanical, Packaging, and Orderable
Information.................................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (September 2021) to Revision A (December 2021)
Page
•
Changed the status of the data sheet from: Advanced Information to: Production Data ...................................1
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5 Pin Configuration and Functions
1
2
3
6
5
4
VCCA
GND
A
VCCB
DIR
B
VCCA
1
2
3
6
5
4
VCCB
DIR
B
GND
A
Figure 5-2. DCK 6-Pin SC70
Top View
Figure 5-1. DBV 6-Pin SOT-23
Top View
1
2
3
6
5
4
VCCA
GND
A
VCCB
DIR
B
1
2
3
6
5
4
VCCA
GND
A
VCCB
DIR
B
Figure 5-3. DRL Package Preview 6-Pin SOT
Top View
Figure 5-4. DRY Package Preview 6-Pin SON
Top View
1
3
6
4
VCCA
VCCB
DIR
B
2
5
GND
A
Figure 5-5. DTQ Package Preview 6-Pin X2SON Transparent Top View
Table 5-1. Pin Functions
PIN
TYPE
DESCRIPTION
DBV, DCK,
DRL, DRY, DTQ
NAME
A
3
4
5
2
5
1
6
I/O
I/O
I
Input or output A. Referenced to VCCA
Input or output B. Referenced to VCCB
.
.
B
DIR
GND
DIR
VCCA
VCCB
Direction-control signal for all ports. Referenced to VCCA
Ground.
.
.
—
I
Direction-control signal for all ports. Referenced to VCCA
A-port supply voltage. 1.1 V ≤ VCCA ≤ 5.5 V.
B-port supply voltage. 1.1 V ≤ VCCB ≤ 5.5 V.
—
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
MAX UNIT
VCCA
VCCB
Supply voltage A
Supply voltage B
6.5
6.5
6.5
6.5
6.5
6.5
6.5
V
V
I/O Ports (A Port)
I/O Ports (B Port)
Control Inputs
A Port
VI
Input Voltage(2)
V
Voltage applied to any output in the high-impedance or power-off
state(2)
VO
VO
V
V
B Port
A Port
–0.5 VCCA + 0.5
–0.5 VCCB + 0.5
–50
Voltage applied to any output in the high or low state(2) (3)
B Port
IIK
IOK
IO
Input clamp current
VI < 0
mA
mA
Output clamp current
VO < 0
–50
Continuous output current
Continuous current through VCC or GND
Junction Temperature
–50
50 mA
200 mA
150 °C
150 °C
–200
Tj
Tstg
Storage temperature
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions
If briefly ooperating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, this device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 6.5 V maximum if the output current rating is observed.
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN
1.1
MAX UNIT
VCCA
VCCB
Supply voltage A
Supply voltage B
5.5
5.5
–0.1
–4
V
V
1.1
VCCO = 1.1 V
VCCO = 1.4 V
VCCO = 1.65 V
VCCO = 2.3 V
VCCO = 3 V
–8
IOH
High-level output current
mA
–12
–24
–32
0.1
4
VCCO = 4.5 V
VCCO = 1.1 V
VCCO = 1.4 V
VCCO = 1.65 V
VCCO = 2.3 V
VCCO = 3 V
8
IOL
Low-level output current
Input voltage (3)
mA
12
24
VCCO = 4.5 V
32
VI
0
0
5.5
VCCO
5.5
V
V
Active State
Tri-State
Operating free-air temperature
VO
TA
Output voltage
0
–40
125 °C
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
(3) All control inputs and data I/Os of this device have weak pulldowns to ensure the line is not floating when undefined external to the
device. The input leakage from these weak pulldowns is defined by the II specification indicated under the Electrical Characteristics.
6.4 Thermal Information
SN74LXC1T45
THERMAL METRIC(1)
DBV (SOT-23) DCK (SC70)
DRL (SOT)
6 PINS
DRY (SON) DTQ (X2SON)
UNIT
6 PINS
6 PINS
6 PINS
6 PINS
Junction-to-ambient thermal
resistance
RθJA
RθJC(top)
RθJB
YJT
217.4
216.1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal
resistance
136.0
98.5
75.8
98.2
N/A
143.6
75.9
58.5
75.6
N/A
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Junction-to-board thermal
resistance
Junction-to-top characterization
parameter
Junction-to-board
characterization parameter
YJB
Rθ
Junction-to-case (bottom) thermal
resistance
JC(bottom)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)(1) (2)
Operating free-air temperature (TA)
25°C –40°C to 85°C –40°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
PARAMETER
TEST CONDITIONS
VCCA
VCCB
1.1 V
1.1 V
0.44
0.60
0.76
1.08
1.48
2.19
2.65
0.44
0.60
0.76
1.08
1.48
2.19
2.65
0.17
0.28
0.35
0.56
0.89
1.51
1.88
0.17
0.28
0.35
0.56
0.89
1.51
1.88
0.2
0.88 0.44
0.98 0.60
1.13 0.76
1.56 1.08
1.92 1.48
2.74 2.19
3.33 2.65
0.88 0.44
0.98 0.60
1.13 0.76
1.56 1.08
1.92 1.48
2.74 2.19
3.33 2.65
0.48 0.17
0.59 0.28
0.69 0.35
0.97 0.56
1.5 0.89
0.88
0.98
1.13
1.56
1.92
2.74
3.33
0.88
0.98
1.13
1.56
1.92
2.74
3.33
0.48
0.59
0.69
0.97
1.5
1.4 V
1.65 V
2.3 V
3 V
1.4 V
1.65 V
2.3 V
3 V
Data Inputs
(Ax, Bx)
(Referenced to VCCI
V
V
V
V
V
V
)
)
)
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
Positive-
going input-
threshold
voltage
VT+
Control Input
(DIR)
(Referenced to
VCCA
)
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
Data Inputs
(Ax, Bx)
(Referenced to VCCI
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
1.97 1.51
2.4 1.88
1.97
2.4
Negative-
going input-
threshold
voltage
VT-
0.48 0.17
0.6 0.28
0.48
0.6
Control Input
(DIR)
(Referenced to
0.71 0.35
0.71
1
1
0.56
1.5 0.89
1.51
2.46 1.88
0.4 0.2
0.5 0.25
1.5
VCCA
)
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
2
2
2.46
0.4
0.25
0.3
0.5
0.55
0.3
0.65 0.38
0.72 0.46
0.93 0.58
1.06 0.69
0.55
0.65
0.72
0.93
1.06
0.4
Data Inputs
(Ax, Bx)
(Referenced to VCCI
0.38
0.46
0.58
0.69
0.2
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
Input-
threshold
hysteresis
(VT+ – VT-)
ΔVT
0.4
0.2
0.25
0.3
0.5 0.25
0.5
Control Input
(DIR)
(Referenced to
0.55
0.3
0.65 0.38
0.72 0.46
0.93 0.58
1.06 0.69
0.55
0.65
0.72
0.93
1.06
0.38
0.46
0.58
0.69
VCCA
)
4.5 V
5.5 V
4.5 V
5.5 V
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6.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)(1) (2)
Operating free-air temperature (TA)
PARAMETER
TEST CONDITIONS
VCCA
VCCB
25°C
–40°C to 85°C
–40°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
VCCO
– 0.1
VCCO
– 0.1
IOH = –100 µA
1.1V – 5.5V 1.1V – 5.5V
IOH = –4 mA
IOH = –8 mA
IOH = –12 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 µA
IOL = 4 mA
1.4 V
1.65 V
2.3 V
3 V
1.4 V
1.65 V
2.3 V
3 V
1
1.2
1.9
2.4
3.8
1
1.2
1.9
2.4
3.8
High-level
output
VOH
V
voltage (3)
4.5 V
4.5 V
1.1V – 5.5V 1.1V – 5.5V
0.1
0.3
0.1
0.3
1.4 V
1.65 V
2.3 V
3 V
1.4 V
1.65 V
2.3 V
3 V
Low-level
output
IOL = 8 mA
0.45
0.3
0.45
0.3
VOL
V
voltage (4)
IOL = 12 mA
IOL = 24 mA
IOL = 32 mA
0.55
0.55
0.55
0.55
4.5 V
4.5 V
Control input
(DIR)
VI = VCCA or GND
1.1V – 5.5V 1.1V – 5.5V
-0.1
1
1
-0.1
–1
2
1
-0.1
–2
2
2
µA
µA
µA
Input leakage
current
II
Data Inputs (5)
(Ax, Bx)
VI = VCCI or GND
1.1V – 5.5V 1.1V – 5.5V –0.3
A Port or B Port
VI or VO = 0 V - 5.5
V
0 V
0 V - 5.5 V
–1
–1
1
1
–2
–2
–2
2
2
2
–2.5
–2.5
–2.5
2.5
2.5
2.5
Partial power
down current
Ioff
0 V - 5.5 V 0 V
Floating
Floating (6) 0 V - 5.5 V
–1.5
1.5
supply Partial A Port or B Port
power down VI or VO = GND
current
Ioff-float
µA
µA
0 V - 5.5 V Floating (6)
–1.5
1.5
2
–2
2
2
–2.5
2.5
4
1.1V – 5.5V 1.1V – 5.5V
VI = VCCI or GND
0 V
5.5 V
0 V
–0.2
–0.5
–1
IO = 0
VCCA supply
current
ICCA
5.5 V
1
1
1
1
2
2
VI = GND
IO = 0
5.5 V
Floating (6)
1.1V – 5.5V 1.1V – 5.5V
2
1
2
1
4
2
VI = VCCI or GND
IO = 0
0 V
5.5 V
0 V
VCCB supply
current
ICCB
µA
µA
5.5 V
–0.2
–0.5
–1
VI = GND
IO = 0
Floating (6) 5.5 V
1
3
1
4
2
6
Combined
supply
current
ICCA
ICCB
+
VI = VCCI or GND
IO = 0
1.1V – 5.5V 1.1V – 5.5V
Control input (DIR):
VI = VCCA – 0.6 V
A port = VCCA or
GND
3.0V - 5.5V 3.0V - 5.5V
3.0V - 5.5V 3.0V - 5.5V
50
50
75
75
VCCA
additional
ΔICCA supply
current per
input
B Port = open
µA
A Port: VI = VCCA
0.6 V
–
DIR = VCCA, B Port
= open
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6.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)(1) (2)
Operating free-air temperature (TA)
25°C –40°C to 85°C –40°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
PARAMETER
TEST CONDITIONS
VCCA
VCCB
VCCB
additional
ΔICCB supply
current per
input
B Port: VI = VCCB
0.6 V
DIR = GND, A Port
= open
-
3.0V - 5.5V 3.0V - 5.5V
50
75 µA
Control Input
Capacitance
Ci
VI = 3.3 V or GND
3.3 V
3.3 V
3.3 V
3.3 V
2.2
4.3
5
5
pF
VCCO = 0V VO
=
Data I/O
Cio
1.65V DC +1 MHz
-16 dBm sine wave
10.5
10.5 pF
Capacitance
(1) VCCI is the VCC associated with the input port
(2) VCCO is the VCC associated with the output port
(3) Tested at VI = VT+(MAX)
(4) Tested at VI = VT-(MIN)
(5) For I/O ports, the parameter Il includes the IOZ current
(6) Floating is defined as a node that is both not actively driven by an external device and has leakage not exeeding 10nA
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6.6 Switching Characteristics, VCCA = 1.2 ± 0.1 V
See Figure 7-1 and Table 7-1 for test circuit and loading. See Figure 7-2, Figure 7-3, and Figure 7-4 for measurement waveforms.
B-Port Supply Voltage (VCCB
1.8 ± 0.15 V 2.5 ± 0.2 V
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
)
Test
Conditions
PARAMETER
FROM
TO
1.2 ± 0.1 V
1.5 ± 0.1 V
3.3 ± 0.3 V
5.0 ± 0.5 V
UNIT
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
6
8
85
55
4
6
41
37
71
47
53
47
47
48
110
89
89
79
3
5
36
33
67
43
53
47
41
41
99
80
84
73
1
3
33
30
60
38
53
47
34
34
86
68
81
68
1
3
34
30
57
37
53
47
33
33
83
65
82
67
1
2
44
33
58
36
53
47
32
32
85
63
92
70
A
B
A
A
B
A
B
Propagation
delay
tpd
tdis
ten
ns
6
85
5
4
3
3
3
B
8
55
6
6
5
4
4
5
53
5
5
5
5
4
DIR
DIR
DIR
DIR
7
47
7
7
7
7
7
Disable time
Enable time
ns
ns
10
14
21
27
16
19
85
7
6
5
5
4
71
11
17
23
14
18
10
16
21
13
17
8
8
6
150
121
118
97
13
17
12
16
13
17
11
15
12
15
11
14
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6.7 Switching Characteristics, VCCA = 1.5 ± 0.1 V
See Figure 7-1 and Table 7-1 for test circuit and loading. See Figure 7-2, Figure 7-3, and Figure 7-4 for measurement waveforms.
B-Port Supply Voltage (VCCB
1.8 ± 0.15 V 2.5 ± 0.2 V
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
)
Test
Conditions
PARAMETER
FROM
TO
1.2 ± 0.1 V
1.5 ± 0.1 V
3.3 ± 0.3 V
5.0 ± 0.5 V
UNIT
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
5
6
71
47
41
37
26
27
71
61
106
92
90
69
3
4
29
30
29
30
26
27
38
39
63
64
51
51
1
3
24
25
27
27
26
27
32
34
54
56
45
47
1
2
20
21
23
24
26
27
25
26
44
45
40
42
1
2
19
20
22
22
26
27
24
25
41
42
39
40
1
1
19
20
21
22
26
27
22
23
39
40
39
40
A
B
A
A
B
A
B
Propagation
delay
tpd
tdis
ten
ns
ns
ns
4
3
2
1
1
1
B
6
4
4
3
3
2
2
2
2
2
2
2
DIR
DIR
DIR
DIR
4
4
4
4
4
4
Disable time
Enable time
8
6
5
3
3
2
12
17
23
12
16
10
13
19
10
14
9
6
6
4
12
17
9
9
9
8
14
8
14
7
12
7
13
12
11
10
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6.8 Switching Characteristics, VCCA = 1.8 ± 0.15 V
See Figure 7-1 and Table 7-1 for test circuit and loading. See Figure 7-2, Figure 7-3, and Figure 7-4 for measurement waveforms.
B-Port Supply Voltage (VCCB
1.8 ± 0.15 V 2.5 ± 0.2 V
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
)
Test
Conditions
PARAMETER
FROM
TO
1.2 ± 0.1 V
1.5 ± 0.1 V
3.3 ± 0.3 V
5.0 ± 0.5 V
UNIT
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
4
6
67
43
36
33
21
22
65
56
96
82
80
60
2
4
27
27
24
25
21
22
35
36
54
56
42
43
1
3
22
22
22
22
21
22
29
30
46
48
37
39
1
2
18
18
19
19
21
22
22
24
36
38
33
34
1
1
16
17
18
18
21
22
21
22
34
35
31
33
1
1
16
16
17
18
21
22
19
20
31
33
30
32
A
B
A
A
B
A
B
Propagation
delay
tpd
tdis
ten
ns
3
1
1
1
1
1
B
5
3
3
2
2
1
2
2
2
2
2
1
DIR
DIR
DIR
DIR
3
3
3
3
3
3
Disable time
Enable time
ns
ns
7
5
4
2
2
1
10
15
20
11
14
8
7
6
5
3
11
17
9
10
15
7
8
7
6
13
7
12
6
10
6
12
11
10
9
9
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6.9 Switching Characteristics, VCCA = 2.5 ± 0.2 V
See Figure 7-1 and Table 7-1 for test circuit and loading. See Figure 7-2, Figure 7-3, and Figure 7-4 for measurement waveforms.
B-Port Supply Voltage (VCCB
1.8 ± 0.15 V 2.5 ± 0.2 V
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
)
Test
Conditions
PARAMETER
FROM
TO
1.2 ± 0.1 V
1.5 ± 0.1 V
3.3 ± 0.3 V
5.0 ± 0.5 V
UNIT
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
3
5
60
38
33
30
15
15
54
47
82
68
67
49
1
3
23
24
20
21
15
15
30
31
44
45
33
34
1
2
19
19
18
18
15
15
25
26
37
39
29
30
1
1
15
15
15
15
15
15
19
21
29
31
25
26
1
1
14
14
14
14
15
15
18
19
27
29
23
24
1
1
1
1
1
1
1
2
5
8
4
6
13
13
14
14
15
15
16
17
24
26
22
23
A
B
A
A
B
A
B
Propagation
delay
tpd
tdis
ten
ns
ns
ns
1
1
1
1
1
B
3
2
2
1
1
1
1
1
1
1
DIR
DIR
DIR
DIR
1
1
1
1
1
Disable time
Enable time
5
4
3
2
2
8
7
6
5
4
12
17
8
9
8
6
6
14
6
13
5
11
4
10
4
11
9
8
7
7
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6.10 Switching Characteristics, VCCA = 3.3 ± 0.3 V
See Figure 7-1 and Table 7-1 for test circuit and loading. See Figure 7-2, Figure 7-3, and Figure 7-4 for measurement waveforms.
B-Port Supply Voltage (VCCB
1.8 ± 0.15 V 2.5 ± 0.2 V
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
)
Test
Conditions
PARAMETER
FROM
TO
1.2 ± 0.1 V
1.5 ± 0.1 V
3.3 ± 0.3 V
5.0 ± 0.5 V
UNIT
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
3
4
57
37
34
30
14
14
49
44
78
64
64
46
1
3
22
22
19
20
14
14
27
28
39
40
30
31
1
2
18
18
16
17
14
14
23
24
33
35
26
27
1
1
1
1
1
1
1
4
6
9
4
7
14
14
13
14
14
14
18
19
26
28
23
24
1
1
1
1
1
1
2
4
5
9
4
6
13
13
13
13
14
14
17
18
25
26
21
22
1
1
1
1
1
1
1
2
4
7
4
6
12
12
12
12
14
14
15
16
22
23
20
21
A
B
A
A
B
A
B
Propagation
delay
tpd
tdis
ten
ns
1
1
1
B
3
2
1
1
1
1
DIR
DIR
DIR
DIR
1
1
1
Disable time
Enable time
ns
ns
5
3
3
8
6
5
12
16
8
8
7
13
6
11
5
11
9
8
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6.11 Switching Characteristics, VCCA = 5.0 ± 0.5 V
See Figure 7-1 and Table 7-1 for test circuit and loading. See Figure 7-2, Figure 7-3, and Figure 7-4 for measurement waveforms.
B-Port Supply Voltage (VCCB
1.8 ± 0.15 V 2.5 ± 0.2 V
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
)
Test
Conditions
PARAMETER
FROM
TO
1.2 ± 0.1 V
1.5 ± 0.1 V
3.3 ± 0.3 V
5.0 ± 0.5 V
UNIT
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
3
4
58
36
44
33
12
12
48
43
87
66
63
43
1
2
21
22
19
20
12
12
26
26
38
39
28
28
1
1
17
18
16
16
12
12
21
22
31
32
24
25
1
1
1
1
1
1
1
3
5
8
3
5
14
14
13
13
12
12
16
17
24
25
20
21
1
1
1
1
1
1
2
3
5
8
3
4
12
13
12
12
12
12
16
17
22
24
19
19
1
1
1
1
1
1
1
2
4
6
2
4
11
11
11
11
12
12
14
15
20
21
18
18
A
B
A
A
B
A
B
Propagation
delay
tpd
tdis
ten
ns
ns
ns
1
1
1
B
2
1
1
1
1
1
DIR
DIR
DIR
DIR
1
1
1
Disable time
Enable time
5
3
3
8
6
5
11
15
7
8
7
12
5
10
4
9
7
6
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6.12 Switching Characteristics: Tsk, TMAX
over operating free-air temperature range (unless otherwise noted)
Operating free-air
temperature (TA)
PARAMETER
TEST CONDITIONS
VCCI
VCCO
UNIT
-40°C to 125°C
MIN TYP MAX
3.0 V - 3.6 V
2.25 V - 2.75 V
1.65 V - 1.95 V
1.1 V - 1.3 V
1.65 V - 1.95 V
1.1 V - 1.3 V
1.1 V - 1.3 V
4.5 V - 5.5 V
4.5 V - 5.5 V
4.5 V - 5.5 V
4.5 V - 5.5 V
4.5 V - 5.5 V
4.5 V - 5.5 V
4.5 V - 5.5 V
3.0 V - 3.6 V
3.0 V - 3.6 V
1.65 V - 1.95 V
3.0 V - 3.6 V
2.25 V - 2.75 V
1.65 V - 1.95 V
1.1 V - 1.3 V
1.65 V - 1.95 V
1.1 V - 1.3 V
1.1 V - 1.3 V
200
150
100
20
420
300
200
40
Up Translation
100
10
210
20
50% Duty Cycle Input
TMAX - Maximum One channel switching
5
10
Mbps
Data Rate
20% of pulse > 0.7*VCCO
20% of pulse < 0.3*VCCO
100
75
210
140
75
50
Down Translation 4.5 V - 5.5 V
3.0 V - 3.6 V
15
30
40
75
3.0 V - 3.6 V
10
20
1.65 V - 1.95 V
5
10
6.13 Operating Characteristics
TA = 25℃ (1)
Supply Voltage (VCCB = VCCA
)
PARAMETER
Test Conditions 1.2 ± 0.1V 1.5 ± 0.1V 1.8 ± 0.15V 2.5 ± 0.2V 3.3 ± 0.3V 5.0 ± 0.5V UNIT
TYP
TYP
TYP
TYP
TYP
TYP
A to B
B to A
A to B
B to A
A Port
CL = 0, RL = Open
f = 10 MHz
3.2
3.4
3.5
3.7
3.9
5.1
(2)
(2)
CpdA
pF
pF
19.4
19.3
3.3
19.6
19.5
3.5
19.8
19.7
3.6
20.4
20.4
4.0
21.8
21.6
4.4
25.7
25.3
5.0
trise = tfall = 1 ns
B Port
CL = 0, RL = Open
f = 10 MHz
CpdB
trise = tfall = 1 ns
(1) For more information about power dissipation capacitance, see the CMOS Power Consumption and Cpd Calculation application report
(2) CpdA and CpdB are repectively A-Port and B-Port power dissipation capacitances per transceiver
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6.14 Typical Characteristics
5
4.5
4
1.8
1.6
1.4
1.2
1
VCC = 5 V
VCC = 3.3 V
VCC = 2.5 V
3.5
3
2.5
2
0.8
0.6
0.4
VCC = 1.8 V
VCC = 1.5 V
VCC = 1.2 V
1.5
0
5
10
15
20
25
30
35
40
45
50
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
IOH Output High Current (mA)
IOH Output High Current (mA)
Figure 6-1. Typical (TA=25°C) Output High Voltage (VOH) vs
Source Current (IOH
Figure 6-2. Typical (TA=25°C) Output High Voltage (VOH) vs
Source Current (IOH
)
)
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
VCC = 5 V
VCC = 3.3 V
VCC = 2.5 V
0.05
0
0
5
10
15
20
25
30
35
40
45
50
IOL Output Low Current (mA)
Figure 6-3. Typical (TA=25°C) Output High Voltage (VOL) vs Sink
Current (IOL
Figure 6-4. Typical (TA=25°C) Output High Voltage (VOL) vs Sink
Current (IOL
)
)
Figure 6-6. Typical (TA=25°C) Supply Current (ICC) vs Input
Voltage (VIN)
Figure 6-5. Typical (TA=25°C) Supply Current (ICC) vs Input
Voltage (VIN)
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7 Parameter Measurement Information
7.1 Load Circuit and Voltage Waveforms
Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:
•
•
•
f = 1 MHz
ZO = 50 Ω
Δt/ΔV ≤ 1 ns/V
Measurement Point
2 x VCCO
Open
RL
S1
Output Pin
Under Test
(1)
GND
CL
RL
A. CL includes probe and jig capacitance.
Figure 7-1. Load Circuit
Table 7-1. Load Circuit Conditions
Parameter
VCCO
RL
CL
S1
VTP
N/A
tpd
Propagation (delay) time
1.1 V – 5.5 V
1.1 V – 1.6 V
1.65 V – 2.7 V
3.0 V – 5.5 V
1.1 V – 1.6 V
1.65 V – 2.7 V
3.0 V – 5.5 V
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
15 pF
15 pF
15 pF
15 pF
15 pF
15 pF
15 pF
Open
2 × VCCO
2 × VCCO
2 × VCCO
GND
0.1 V
0.15 V
0.3 V
0.1 V
0.15 V
0.3 V
ten, tdis Enable time, disable time
ten, tdis Enable time, disable time
GND
GND
(1)
VCCI
(1)
VCCI
100 kHz
Input A, B
VCCI / 2
VCCI / 2
Input A, B
500 ps/V œ 1 s/V
0 V
VOH
0 V
VOH
(2)
tpd
tpd
(2)
Ensure Monotonic
Rising and Falling Edge
Output B, A
(2)
VOL
Output B, A
VCCI / 2
VCCI / 2
(2)
VOL
1. VCCI is the supply pin associated with the input port.
2. VOH and VOL are typical output voltage levels that occur
with specified RL, CL, and S1
1. VCCI is the supply pin associated with the input port.
2. VOH and VOL are typical output voltage levels that occur
with specified RL, CL, and S1
Figure 7-3. Input Transition Rise and Fall Rate
Figure 7-2. Propagation Delay
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VCCA
GND
VCCA / 2
VCCA / 2
DIR
(1)
ten
(5)
VCCO
Output A(2)
VCCO / 2
VOL + VTP
(6)
VOL
tdis
(6)
VOH
Output A(3)
VOH - VTP
VCCO / 2
GND
(1)
ten
(5)
VCCO
Output B(2)
Output B(3)
VCCO / 2
VOL + VTP
(6)
VOL
tdis
(6)
VOH
VOH - VTP
VCCO / 2
GND
A. 1. Illustrative purposes only. Enable time is a calculation as described in Enable Times.
2. Output waveform on the condition that input is driven to a valid Logic low.
3. Output waveform on the condition that input is driven to a valid Logic high.
4. VCCI is the supply pin associated with the input port.
5. VCCO is the supply pin associated with the output port.
6. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
Figure 7-4. Enable Time And Disable Time
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8 Detailed Description
8.1 Overview
The SN74LXC1T45 is an 1-bit translating transceiver that uses two individually configurable power-supply rails.
The device is operational with both VCCA and VCCB supplies as low as 1.1 V and as high as 5.5 V. Additionally,
the device can be operated with VCCA = VCCB. The A port is designed to track VCCA, and the B port is designed
to track VCCB
.
The SN74LXC1T45 device is designed for asynchronous communication between devices and transmits data
from A to B or from B to A based on the logic level of the direction-control input (DIR). The control pins of the
SN74LXC1T45 (DIR) is referenced to VCCA. The input circuitry on both A and B ports is always active and must
have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.
This device is fully specified for partial-power-down applications using the Ioff current. The Ioff protection circuitry
ensures that no excessive current is drawn from or sourced into an input, output, or I/O while the device is
powered down.
The VCC isolation or VCC disconnect feature ensures that if either VCC is less than 100 mV or disconnected
with the complementary supply within the recommended operating conditions, then both I/O ports are weakly
pulled-down and then set to the high-impedance state by disabling their outputs while the supply current is
maintained. The Ioff-float circuitry ensures that no excessive current is drawn from or sourced into an input, output,
or I/O while the supply is floating.
Glitch-free power supply sequencing allows either supply rail to be powered on or off in any order while providing
robust power sequencing performance.
8.2 Functional Block Diagram
VCCA
VCCB
DIR
B1
A1
8.3 Feature Description
8.3.1 CMOS Schmitt-Trigger Inputs with Integrated Pulldowns
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics,
which makes this device extremely tolerant to slow or noisy inputs. Driving the inputs slowly will increase
dynamic current consumption of the device. For additional information regarding Schmitt-trigger inputs, see
Understanding Schmitt Triggers.
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8.3.1.1 I/O's with Integrated Dynamic Pull-Down Resistors
Input circuits of the data I/O's are always active even when the device is disabled. It is recommended to keep a
valid voltage level at the I/O's to avoid high current consumption. To help avoid floating inputs on the I/O's during
disabling, this device has 100-kΩ typical integrated weak dynamic pull-downs on all data I/O's. When the device
is disabled, the dynamic pull-downs are activated for only a short period of time to help drive and keep low any
floating inputs before the device I/O's become high impedance. If the I/O lines are to be floated after the device
is disabled, then it is recommended to keep them at a valid input voltage level using the external pull-downs.
This feature is ideal for loads of 30 pF or less. If greater capactive loading is present, then external pull-downs
are recommended. If an external pull-up is required, then it should be no larger than 15 kΩ to avoid contention
with the 100 kΩ internal pull-down.
8.3.1.2 Control Inputs with Integrated Static Pull-Down Resistors
Similar to the data I/O's, a floating control input can cause high current consumption. To help avoid this concern,
this device has integrated weak static pull-downs of 5-MΩ typical on the control input (DIR). These pull-downs
are always present. So for example if the DIR pin is left floating, then the B port will be configured as an input
and the A port configured as an output.
8.3.2 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at
all times.
8.3.3 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting
current backflow into the device. The maximum leakage into or out of any input or output pin on the device is
specified by Ioff in the Electrical Characteristics.
8.3.4 VCC Isolation and VCC Disconnect (Ioff-float
)
This device has I/O's with Integrated Dynamic Pull-Down Resistors. The I/O's will get pulled down and then enter
a high-impedance state when either supply is < 100 mV or left floating (disconnected), while the other supply is
still connected to the device. It is recommended that the I/O's for this device are not driven and kept at a logic
low state prior to floating (disconnecting) either supply.
The maximum supply current is specified by ICCx, while VCCx is floating, in the Electrical Characteristics. The
maximum leakage into or out of any input or output pin on the device is specified by Ioff(float) in the Electrical
Characteristics.
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VCCA
VCCB
ICCB maintained
Supply disconnected
VCCA
VCCB
DIR
OE
Disabled
Hi-Z
B1
Hi-Z
A1
Ioff(float)
Ioff(float)
Disabled
GND
Figure 8-1. VCC Disconnect Feature
8.3.5 Over-Voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Recommended Operating Conditions.
8.3.6 Glitch-Free Power Supply Sequencing
Either supply rail may be powered on or off in any order without producing a glitch on the I/Os (that is, where
the output erroneously transitions to VCC when it should be held low or vice versa). Glitches of this nature can
be misinterpreted by a peripheral as a valid data bit, which could trigger a false device reset of the peripheral, a
false device configuration of the peripheral, or even a false data initialization by the peripheral.
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8.3.7 Negative Clamping Diodes
Figure 8-2 shows the inputs and outputs to this device that have negative clamping diodes.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input negative voltage and output voltage ratings may be exceeded if the input and
output clamp current ratings are observed.
VCCA VCCB
Device
Input or I/O
configured
as input
Level
Shifter
I/O configured
as output
-IIK
-IOK
GND
Figure 8-2. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.8 Fully Configurable Dual-Rail Design
Both the VCCA and VCCB pins can be supplied at any voltage from 1.1 V to 5.5 V, making the device suitable for
translating between any of the voltage nodes (1.2 V, 1.5 V, 1.8 V, 3.3 V, and 5.0 V).
8.3.9 Supports High-Speed Translation
The SN74LXC1T45 device can support high data rate applications. The translated signal data rate can be up to
420 Mbps when the signal is translated from 3.3 V to 5.0 V.
8.4 Device Functional Modes
Table 8-1. Function Table
CONTROL INPUTS (1)
PORT STATUS
OPERATION
DIR
L
A PORT
B PORT
Input (Hi-Z)
Output (Enabled)
Input (Hi-Z)
B data to A bus
A data to B bus
H
Output (Enabled)
(1) Input circuits of the data I/Os are always active and should be kept at a valid logic level.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LXC1T45 device can be used in level-translation applications for interfacing devices or systems
operating at different interface voltages with one another. The SN74LXC1T45 device is ideal for use in
applications where a push-pull driver is connected to the data I/Os. The maximum data rate can be up to
420 Mbps when the device translates a signal from 3.3 V to 5.0 V.
9.2 Enable Times
Calculate the enable times for the SN74LXC1T45 using the following formulas:
tA_en (DIR to A) = tdis (DIR to B) + tpd (B to A)
tB_en (DIR to B) = tdis (DIR to A) + tpd (A to B)
(1)
(2)
In a bidirectional application, these enable times provide the maximum delay time from the time the DIR bit is
switched until an output is expected. For example, if the SN74LXC1T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled (tdis) before presenting it with an input. After
the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay (tpd). To avoid bus contention, care should be taken to not apply an input signal prior to the
output being disabled (tdis maximum).
9.3 Typical Application
VCCB
VCCA
LDO
PMIC
DC/DC
GPIO1
RESET
System
Controller
SN74LXC1T45
Figure 9-1. LED Driver Application
9.3.1 Design Requirements
For this design example, use the parameters listed in Table 9-1.
Table 9-1. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUES
1.1 V to 5.5 V
Input voltage range
Output voltage range
1.1 V to 5.5 V
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9.3.2 Detailed Design Procedure
To begin the design process, determine the following:
•
Input voltage range
– Use the supply voltage of the device that is driving the SN74LXC1T45 device to determine the input
voltage range. For a valid logic-high, the value must exceed the positive-going input-threshold voltage
(Vt+) of the input port. For a valid logic low the value must be less than the negative-going input-threshold
voltage (Vt-) of the input port.
•
Output voltage range
– Use the supply voltage of the device that the SN74LXC1T45 device is driving to determine the output
voltage range.
10 Power Supply Recommendations
Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing
without any supply sequencing requirements such as ramp order or ramp rate.
This device was designed with various power supply sequencing methods in mind to help prevent unintended
triggering of downstream devices, as described in Glitch-free Power Supply Sequencing.
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, the following common printed-circuit board layout guidelines are
recommended:
•
Use bypass capacitors on the power supply pins and place them as close to the device as possible. A 0.1
µF capacitor is recommended, but transient performance can be improved by having both 1 µF and 0.1 µF
capacitors in parallel as bypass capacitors.
•
The high drive capability of this device creates fast edges into light loads so routing and load conditions
should be considered to prevent ringing.
11.2 Layout Example
Legend
Via to VCCA
Via to VCCB
A
B
G
Via to GND
Copper Traces
SN74LXC1T45DTQ
B
VCCA
1
VCCB
6
A
01005
0.1µF
01005
0.1µF
4 mil
GND
DIR
2
5
G
G
G
A
B
4
Reset Flag
to Controller
Reset Flag
from LDO
3
Figure 11-1. Layout Example − SN74LXC1T45
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Regulatory Requirements
No statutory or regulatory requirements apply to this device.
There are no special characteristics for this product.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
•
Texas Instruments, Understanding Schmitt Triggers application report
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74LXC1T45DBVR
ACTIVE
SOT-23
DBV
6
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2LSF
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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