SN74LXC8T245QPWRQ1 [TI]
SN74LXC8T245-Q1 Automotive 8-bit Dual-Supply Bus Transceiver with Configurable Level Shifting and 3-State Outputs;
| 型号： | SN74LXC8T245QPWRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SN74LXC8T245-Q1 Automotive 8-bit Dual-Supply Bus Transceiver with Configurable Level Shifting and 3-State Outputs |
| 文件： | 总31页 (文件大小：1009K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LXC8T245-Q1
SCES920 – SEPTEMBER 2020
SN74LXC8T245-Q1 Automotive 8-bit Dual-Supply Bus Transceiver with Configurable
Level Shifting and 3-State Outputs
1 Features
3 Description
•
•
AEC-Q100 Qualified for automotive applications
Fully configurable dual-rail design allows each port
to operate from 1.1 V to 5.5 V
The SN74LXC8T245-Q1 is an 8-bit, dual-supply
noninverting bidirectional voltage level translation
device. Ax pins and control pins (DIR and OE) are
referenced to VCCA logic levels, and Bx pins are
referenced to VCCB logic levels. The A port is able to
accept I/O voltages ranging from 1.1 V to 5.5 V, while
the B port can accept I/O voltages from 1.1 V to 5.5 V.
A high on DIR allows data transmission from A to B
and a low on DIR allows data transmission from B to
A when OE is set to low. When OE is set to high, both
Ax and Bx pins are in the high-impedance state. See
Device Functional Modes for a summary of the
operation of the control logic.
•
•
•
•
Robust, glitch-free power supply sequencing
Up to 420-Mbps support for 3.3 V to 5.0 V
Schmitt-trigger inputs allow for slow/noisy inputs
I/O's with Integrated Dynamic Pull-Down Resistors
help reduce external component count
Control Inputs with Integrated Static Pull-Down
Resistors allow for floating control inputs
High drive strength (up to 32 mA at 5 V)
Low power consumption
•
•
•
– 4-µA maximum (25°C)
Device Information
– 25-µA maximum (–40°C to 125°C)
VCC Isolation and VCC Disconnect (Ioff-float) feature
– If either VCC supply is < 100 mV or
disconnected, all I/O's get pulled-down and
then become high-impedance
Ioff supports partial-power-down mode operation
Compatible with LVC family level shifters
Control logic (DIR and OE) are referenced to VCCA
Operating temperature from –40°C to +125°C
Latch-up performance exceeds 100 mA per JESD
78, Class II
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
7.80 mm x 6.40 mm
5.50 mm x 3.50 mm
•
SN74LXC8T245PW-Q1 TSSOP (24)
SN74LXC8T245RHL-Q1 VQFN (24)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
•
•
•
•
VCCB
VCCA
DIR
OE
•
ESD protection exceeds JESD 22
– 4000-V human-body model
– 1000-V charged-device model
B1
B8
A1
A8
2 Applications
To other 7 channels
•
•
•
•
•
Eliminate slow or noisy input signals
Driving indicator LEDs or buzzers
Debouncing a mechanical switch
Infotainment head unit
GND
ADAS Fusion
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
SN74LXC8T245-Q1
SCES920 – SEPTEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics, VCCA = 1.2 ± 0.1 V............ 9
6.7 Switching Characteristics, VCCA = 1.5 ± 0.1 V.......... 10
6.8 Switching Characteristics, VCCA = 1.8 ± 0.15 V........ 11
6.9 Switching Characteristics, VCCA = 2.5 ± 0.2 V.......... 12
6.10 Switching Characteristics, VCCA = 3.3 ± 0.3 V........ 13
6.11 Switching Characteristics, VCCA = 5.0 ± 0.5 V........ 14
6.12 Operating Characteristics....................................... 15
7 Parameter Measurement Information..........................16
7.1 Load Circuit and Voltage Waveforms........................16
8 Detailed Description......................................................18
8.1 Overview...................................................................18
8.2 Functional Block Diagram.........................................18
8.3 Feature Description...................................................19
8.4 Device Functional Modes..........................................21
9 Application and Implementation..................................22
9.1 Application Information............................................. 22
9.2 Typical Application.................................................... 22
10 Power Supply Recommendations..............................23
11 Layout...........................................................................23
11.1 Layout Guidelines................................................... 23
11.2 Layout Example...................................................... 23
12 Device and Documentation Support..........................24
12.1 Regulatory Requirements....................................... 24
12.2 Support Resources................................................. 24
12.3 Trademarks.............................................................24
12.4 Electrostatic Discharge Caution..............................24
12.5 Glossary..................................................................24
13 Mechanical, Packaging, and Orderable
Information.................................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
September 2020
*
Initial release.
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5 Pin Configuration and Functions
VCCA
DIR
A1
1
2
3
4
5
6
7
VCCB
VCCB
24
23
22
21
20
19
18
2
3
23
OE
B1
B2
B3
B4
B5
B6
B7
B8
GND
VCCB
DIR
A1
22
OE
A2
4
21
A2
B1
A3
5
20
A3
B2
A4
6
19
A4
B3
PAD
7
18
A5
B4
A5
8
17
A6
B5
A6
8
17
16
15
14
13
9
16
A7
B6
A7
9
10
11
15
A8
B7
14
B8
GND
A8
10
11
12
GND
GND
All packages are on the same relative scale
Figure 5-1. PW, and RHL Package 24-Pin TSSOP, and VQFN Transparent Top View
Pin Functions
PIN
I/O
DESCRIPTION
NAME
VCCA
DIR
A1
PW, RHL
1
2
—
I
A-port supply voltage. 1.1 V ≤ VCCA ≤ 5.5 V.
Direction-control signal for all ports. Referenced to VCCA
.
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
Input/output A1. Referenced to VCCA
Input/output A2. Referenced to VCCA
Input/output A3. Referenced to VCCA
Input/output A4. Referenced to VCCA
Input/output A5. Referenced to VCCA
Input/output A6. Referenced to VCCA
Input/output A7. Referenced to VCCA
Input/output A8. Referenced to VCCA
Ground.
.
.
.
.
.
.
.
.
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
10
11
12
13
14
15
16
17
18
19
20
21
GND
—
Ground.
—
Ground.
B8
B7
B6
B5
B4
B3
B2
B1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input/output B8. Referenced to VCCB
Input/output B7. Referenced to VCCB
Input/output B6. Referenced to VCCB
Input/output B5. Referenced to VCCB
Input/output B4. Referenced to VCCB
Input/output B3. Referenced to VCCB
Input/output B2. Referenced to VCCB
Input/output B1. Referenced to VCCB
.
.
.
.
.
.
.
.
Output Enable. Pull to GND to enable all outputs. Pull to VCCA to place all outputs in high-impedance
mode. Referenced to VCCA
OE
22
I
.
23
24
—
—
—
—
B-port supply voltage. 1.1 V ≤ VCCB ≤ 5.5 V.
VCCB
PAD
B-port supply voltage. 1.1 V ≤ VCCB ≤ 5.5 V.
Thermal pad. May be grounded (recommended) or left floating
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
MAX UNIT
VCCA
VCCB
Supply voltage A
Supply voltage B
6.5
6.5
6.5
6.5
6.5
6.5
6.5
V
V
I/O Ports (A Port)
I/O Ports (B Port)
Control Inputs
A Port
VI
Input Voltage(2)
V
Voltage applied to any output in the high-impedance or power-off
state(2)
VO
VO
V
V
B Port
A Port
–0.5 VCCA + 0.5
–0.5 VCCB + 0.5
–50
Voltage applied to any output in the high or low state(2) (3)
B Port
IIK
IOK
IO
Input clamp current
VI < 0
mA
mA
Output clamp current
VO < 0
–50
Continuous output current
Continuous current through VCC or GND
Junction Temperature
–50
50 mA
200 mA
150 °C
150 °C
–200
Tj
Tstg
Storage temperature
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure beyond the limits listed in Recommended Operating Conditions. may affect device
reliability.
(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 6.5 V maximum if the output current rating is observed.
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN
MAX UNIT
VCCA
VCCB
Supply voltage A
Supply voltage B
1.1
1.1
5.5
5.5
–0.1
–2
V
V
VCCO = 1.1 V
VCCO = 1.4 V
VCCO = 1.65 V
VCCO = 2.3 V
VCCO = 3 V
–4
IOH
High-level output current
mA
–12
–24
–32
0.1
2
VCCO = 4.5 V
VCCO = 1.1 V
VCCO = 1.4 V
VCCO = 1.65 V
VCCO = 2.3 V
VCCO = 3 V
4
IOL
Low-level output current
Input voltage (3)
mA
12
24
VCCO = 4.5 V
32
VI
0
0
5.5
VCCO
5.5
V
V
Active State
Tri-State
Operating free-air temperature
VO
TA
Output voltage
0
–40
125 °C
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
(3) All control inputs and data I/Os of this device have weak pulldowns to ensure the line is not floating when undefined external to the
device. The input leakage from these weak pulldowns is defined by the II specification indicated under Electrical Characteristics.
6.4 Thermal Information
SN74LXC8T245
THERMAL METRIC(1)
PW (TSSOP)
24 PINS
RHL (VQFN)
24 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
99.6
43.7
54.7
6.4
47.4
42.6
25.1
2.7
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
YJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
YJB
54.3
N/A
25.1
14.9
RθJC(bottom)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)(1) (2)
Operating free-air temperature (TA)
25°C –40°C to 85°C –40°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
PARAMETER
TEST CONDITIONS
VCCA
VCCB
1.1 V
1.1 V
0.44
0.60
0.76
1.08
1.48
2.19
2.65
0.44
0.60
0.76
1.08
1.48
2.19
2.65
0.17
0.28
0.35
0.56
0.89
1.51
1.88
0.17
0.28
0.35
0.56
0.89
1.51
1.88
0.2
0.88 0.44
0.98 0.60
1.13 0.76
1.56 1.08
1.92 1.48
2.74 2.19
3.33 2.65
0.88 0.44
0.98 0.60
1.13 0.76
1.56 1.08
1.92 1.48
2.74 2.19
3.33 2.65
0.48 0.17
0.59 0.28
0.69 0.35
0.97 0.56
1.5 0.89
0.88
0.98
1.13
1.56
1.92
2.74
3.33
0.88
0.98
1.13
1.56
1.92
2.74
3.33
0.48
0.59
0.69
0.97
1.5
1.4 V
1.65 V
2.3 V
3 V
1.4 V
1.65 V
2.3 V
3 V
Data Inputs
(Ax, Bx)
(Referenced to VCCI
V
V
V
V
V
V
)
)
)
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
Positive-
going input-
threshold
voltage
VT+
Control Inputs
( OE, DIR)
(Referenced to
VCCA
)
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
Data Inputs
(Ax, Bx)
(Referenced to VCCI
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
1.97 1.51
2.4 1.88
1.97
2.4
Negative-
going input-
threshold
voltage
VT-
0.48 0.17
0.6 0.28
0.48
0.6
Control Inputs
( OE, DIR)
(Referenced to
0.71 0.35
0.71
1
1
0.56
1.5 0.89
1.51
2.46 1.88
0.4 0.2
0.5 0.25
1.5
VCCA
)
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
2
2
2.46
0.4
0.25
0.3
0.5
0.55
0.3
0.65 0.38
0.72 0.46
0.93 0.58
1.06 0.69
0.55
0.65
0.72
0.93
1.06
0.4
Data Inputs
(Ax, Bx)
(Referenced to VCCI
0.38
0.46
0.58
0.69
0.2
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
4.5 V
5.5 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
Input-
threshold
hysteresis
(VT+ – VT-)
ΔVT
0.4
0.2
0.25
0.3
0.5 0.25
0.5
Control Inputs
( OE, DIR)
(Referenced to
0.55
0.3
0.65 0.38
0.72 0.46
0.93 0.58
1.06 0.69
0.55
0.65
0.72
0.93
1.06
0.38
0.46
0.58
0.69
VCCA
)
4.5 V
5.5 V
4.5 V
5.5 V
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6.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)(1) (2)
Operating free-air temperature (TA)
25°C –40°C to 85°C –40°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
PARAMETER
TEST CONDITIONS
VCCA
VCCB
1.1 V – 5.5 1.1 V – 5.5
VCCO
– 0.1
VCCO
– 0.1
IOH = –100 µA
V
V
IOH = –4 mA
IOH = –8 mA
IOH = –12 mA
IOH = –24 mA
IOH = –32 mA
1.4 V
1.65 V
2.3 V
3 V
1.4 V
1.65 V
2.3 V
3 V
1
1.2
1.9
2.4
3.8
1
1.2
1.9
2.4
3.8
High-level
output
VOH
V
voltage (3)
4.5 V
4.5 V
1.1 V – 5.5 1.1 V – 5.5
IOL = 100 µA
0.1
0.1
V
V
IOL = 4 mA
IOL = 8 mA
IOL = 12 mA
IOL = 24 mA
IOL = 32 mA
1.4 V
1.65 V
2.3 V
3 V
1.4 V
1.65 V
2.3 V
3 V
0.3
0.45
0.3
0.3
0.45
0.3
Low-level
output
VOL
V
voltage (4)
0.55
0.55
0.55
0.55
4.5 V
4.5 V
Control inputs
(DIR, OE)
VI = VCCA or GND
1.1 V – 5.5 1.1 V – 5.5
–0.1
–0.3
1.5 –0.1
2
1
–0.1
–2
2
2
µA
µA
µA
V
V
Input leakage
current
II
Data Inputs
(Ax, Bx)
VI = VCCI or GND
1.1 V – 5.5 1.1 V – 5.5
0.3
–1
V
V
A Port or B Port
VI or VO = 0 V - 5.5
V
0 V
0 V – 5.5 V
–1.5
–1.5
–1.5
1.5
1.5
1.5
–2
–2
–2
2
2
2
–2.5
–2.5
–2.5
2.5
2.5
2.5
Partial power
down current
Ioff
0 V – 5.5 V 0 V
Floating
Floating (5) 0 V – 5.5 V
supply Partial A Port or B Port
power down VI or VO = GND
current
Ioff-float
µA
µA
0 V – 5.5 V Floating (5)
–1.5
1.5
–2
2
–2.5
2.5
A or B Port:
Tri-state
VI = VCCI or GND
output current
1.1 V – 5.5 1.1 V – 5.5
IOZ
–0.3
0.3
2
–1
1
–2
2
VO = VCCO or GND
V
V
(6)
OE= VT+(MAX)
1.1 V – 5.5 1.1 V – 5.5
15
20
V
V
VI = VCCI or GND
IO = 0
0 V
5.5 V
5.5 V
0 V
–0.3
–1
–2
VCCA supply
current
ICCA
µA
µA
2
2
15
15
20
20
VI = GND
IO = 0
5.5 V
Floating (5)
1.1 V – 5.5 1.1 V – 5.5
V
2
2
15
15
20
20
V
VI = VCCI or GND
IO = 0
0 V
5.5 V
5.5 V
0 V
VCCB supply
current
ICCB
–0.3
–1
–2
VI = GND
IO = 0
Floating (5) 5.5 V
2
4
15
20
20
Combined
supply
current
ICCA
ICCB
+
VI = VCCI or GND
IO = 0
1.1 V – 5.5 1.1 V – 5.5
25 µA
V
V
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6.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)(1) (2)
Operating free-air temperature (TA)
25°C –40°C to 85°C –40°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
PARAMETER
TEST CONDITIONS
VCCA
VCCB
Control inputs (DIR,
OE):
VI = VCCA – 0.6 V
A port = VCCA or
GND
3.0 V – 5.5 3.0 V – 5.5
50
75
75
VCCA
additional
ΔICCA supply
current per
input
V
V
µA
B Port = open
A Port: VI = VCCA
0.6 V
DIR = VCCA, B Port
= open
–
3.0 V – 5.5 3.0 V – 5.5
50
50
V
V
VCCB
additional
ΔICCB supply
current per
input
B Port: VI = VCCB
0.6 V
DIR = GND, A Port
= open
-
3.0 V – 5.5 3.0 V – 5.5
75 µA
V
V
Control Input
Capacitance
Ci
VI = 3.3 V or GND
3.3 V
3.3 V
3.3 V
3.3 V
2.6
5.8
5
5
pF
OE= VCCA, VO
=
Data I/O
Cio
1.65V DC +1 MHz
-16 dBm sine wave
10
10 pF
Capacitance
(1) VCCI is the VCC associated with the input port
(2) VCCO is the VCC associated with the output port
(3) Tested at VI = VT+(MAX)
(4) Tested at VI = VT-(MIN)
(5) Floating is defined as a node that is both not actively driven by an external device and has leakage not exeeding 10 nA
(6) For I/O ports, the parameter IOZ includes the input leakage current
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6.6 Switching Characteristics, VCCA = 1.2 ± 0.1 V
See Figure 7-1 and Table 7-1 for test circuit and loading. See Figure 7-2, Figure 7-3, and Figure 7-4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB
1.8 ± 0.15 V 2.5 ± 0.2 V
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
)
TEST
CONDITIONS
PARAMETER
FROM
TO
1.2 ± 0.1 V
1.5 ± 0.1 V
3.3 ± 0.3 V
5.0 ± 0.5 V
UNIT
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
100 0.4
100 0.4
100 0.4
100 0.4
100 0.4
100 0.4
110 0.4
110 0.4
130 0.4
130 0.4
130 0.4
130 0.4
50 0.4
50 0.4
80 0.4
80 0.4
100 0.4
100 0.4
75 0.4
78 0.4
130 0.4
130 0.4
90 0.4
90 0.4
40 0.4
40 0.4
80 0.4
80 0.4
100 0.4
100 0.4
80 0.4
80 0.4
130 0.4
130 0.4
80 0.4
80 0.4
40 0.4
40 0.4
70 0.4
70 0.4
100 0.4
100 0.4
70 0.4
70 0.4
125 0.4
125 0.4
70 0.4
70 0.4
40 0.4
40 0.4
60 0.4
60 0.4
100 0.4
100 0.4
60 0.4
60 0.4
130 0.4
130 0.4
60 0.4
60 0.4
40
40
A
B
A
A
B
A
B
Propagation
delay
tpd
tdis
ten
ns
60
B
60
100
100
60
OE
OE
OE
OE
Disable time
Enable time
ns
ns
60
130
130
50
50
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6.7 Switching Characteristics, VCCA = 1.5 ± 0.1 V
See Figure 7-1 and Table 7-1 for test circuit and loading. See Figure 7-2, Figure 7-3, and Figure 7-4 for measurement waveforms.
B–PORT SUPPLY VOLTAGE (VCCB
1.8 ± 0.15 V 2.5 ± 0.2 V
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
)
TEST
CONDITIONS
PARAMETER
FROM
TO
1.2 ± 0.1 V
1.5 ± 0.1 V
3.3 ± 0.3 V
5.0 ± 0.5 V
UNIT
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
80 1.7
80 1.7
50 0.9
50 0.9
90 1.5
90 1.5
90 2.4
90 2.4
90 0.4
90 0.4
125 1.8
125 1.8
30 1.7
32 1.7
30 0.9
32 0.9
55 1.5
55 1.5
65 2.4
65 2.4
65 0.4
65 0.4
65 1.8
65 1.8
23 1.3
27 1.3
28 0.8
30 0.8
55 1.5
55 1.5
55 1.9
55 1.9
65 0.4
65 0.4
55 1.5
55 1.5
18
21
1
1
16 0.8
18 0.8
23 0.7
28 0.7
55 1.4
55 1.4
50 1.3
50 1.3
65 0.4
65 0.4
35 0.9
35 0.9
15
16
22
26
55
55
40
40
60
60
35
35
A
B
A
A
B
A
B
Propagation
delay
tpd
tdis
ten
ns
ns
ns
23 0.7
28 0.7
55 1.5
55 1.5
50 1.7
50 1.7
65 0.4
65 0.4
40 1.2
40 1.2
B
OE
OE
OE
OE
Disable time
Enable time
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6.8 Switching Characteristics, VCCA = 1.8 ± 0.15 V
See Figure 7-1 and Table 7-1 for test circuit and loading. See Figure 7-2, Figure 7-3, and Figure 7-4 for measurement waveforms.
B–PORT SUPPLY VOLTAGE (VCCB
1.8 ± 0.15 V 2.5 ± 0.2 V
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
)
TEST
CONDITIONS
PARAMETER
FROM
TO
1.2 ± 0.1 V
1.5 ± 0.1 V
3.3 ± 0.3 V
5.0 ± 0.5 V
UNIT
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
80 1.7
80 1.7
40 0.9
40 0.9
80 1.5
80 1.5
85 2.4
85 2.4
80 0.4
80 0.4
115 1.8
115 1.8
26 1.7
30 1.7
23 0.9
27 0.9
45 1.5
45 1.5
55 2.4
58 2.4
45 0.4
47 0.4
60 1.8
60 1.8
21.9 1.3
25.9 1.3
23.8 0.8
28.8 0.8
45 1.5
45 1.5
50 1.9
50 1.9
50 0.4
50 0.4
50 1.5
50 1.5
15
15
1
1
13 0.8
13 0.8
23.4 0.7
27.4 0.7
45 1.4
45 1.4
40 1.3
40 1.3
50 0.4
50 0.4
30 0.9
30 0.9
11
12
A
B
A
A
B
A
B
Propagation
delay
tpd
tdis
ten
ns
23.6 0.7
27.6 0.7
45 1.5
45 1.5
40 1.7
40 1.7
50 0.4
50 0.4
40 1.2
40 1.2
23.4
27.4
45
B
OE
OE
OE
OE
45
Disable time
Enable time
ns
ns
35
35
50
50
30
30
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6.9 Switching Characteristics, VCCA = 2.5 ± 0.2 V
See Figure 7-1 and Table 7-1 for test circuit and loading. See Figure 7-2, Figure 7-3, and Figure 7-4 for measurement waveforms.
B–PORT SUPPLY VOLTAGEe (VCCB
1.8 ± 0.15 V 2.5 ± 0.2 V
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
)
TEST
CONDITIONS
PARAMETER
FROM
TO
1.2 ± 0.1 V
1.5 ± 0.1 V
3.3 ± 0.3 V
5.0 ± 0.5 V
UNIT
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
70 1.5
70 1.5
40 1.2
40 1.2
70 1.4
70 1.4
73 2.3
73 2.3
23 1.5
28 1.5
18 1.2
23 1.3
30 1.4
30 1.4
50 2.3
52 2.3
21.4 1.2
25.4 1.2
14 1.2
12 0.8
13 0.8
10 0.6
11 0.6
11 0.9
12.9 0.9
30 1.4
30 1.4
30 0.9
30 0.9
9
9
A
B
A
A
B
A
B
Propagation
delay
tpd
tdis
ten
ns
ns
ns
12
1
1
11
12
30
30
25
25
30
30
21
21
B
15
1
13.1
30 1.4
30 1.4
45 1.8
45 1.8
30 1.4
30 1.4
35 1.7
35 1.7
OE
OE
OE
OE
Disable time
Enable time
70
70
1
1
30
30
1
1
30
30
1
1
30
30
1
1
30
30
25
25
1
1
1
1
112 1.7
112 1.7
55 1.7
55 1.7
45 1.5
45 1.5
30 1.2
30 1.2
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6.10 Switching Characteristics, VCCA = 3.3 ± 0.3 V
See Figure 7-1 and Table 7-1 for test circuit and loading. See Figure 7-2, Figure 7-3, and Figure 7-4 for measurement waveforms.
B–PORT SUPPLY VOLTAGE (VCCB
1.8 ± 0.15 V 2.5 ± 0.2 V
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
)
TEST
CONDITIONS
PARAMETER
FROM
TO
1.2 ± 0.1 V
1.5 ± 0.1 V
3.3 ± 0.3 V
5.0 ± 0.5 V
UNIT
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
60 1.5
60 1.5
40 1.2
40 1.2
60 1.4
60 1.4
70 2.3
70 2.3
23 1.5
28 1.5
16 0.8
18 0.8
25 1.6
25 1.6
50 2.1
50 2.1
25 0.8
25 0.8
55 1.8
55 1.8
21.2 1.1
25.2 1.1
13 0.8
13 0.8
25 1.6
25 1.6
40 1.7
40 1.7
25 0.8
25 0.8
45 1.4
45 1.4
11 0.8
12.8 0.8
10 0.7
10.5 0.7
25 1.6
25 1.6
30 1.5
30 1.5
23 0.8
23 0.8
30 1.1
30 1.1
9
0.5
10.3 0.5
0.6
7.5
8
A
B
A
A
B
A
B
Propagation
delay
tpd
tdis
ten
ns
9
9
B
10.1 0.6
25 1.6
25 1.6
30 0.8
30 0.8
23 0.8
23 0.8
23 0.9
23 0.9
9
25
25
25
25
23
23
19
19
OE
OE
OE
OE
Disable time
Enable time
ns
ns
60
60
1
1
110 1.7
110 1.7
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6.11 Switching Characteristics, VCCA = 5.0 ± 0.5 V
See Figure 7-1 and Table 7-1 for test circuit and loading. See Figure 7-2, Figure 7-3, and Figure 7-4 for measurement waveforms.
B–PORT SUPPLY VOLTAGE (VCCB
1.8 ± 0.15 V 2.5 ± 0.2 V
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
)
TEST
CONDITIONS
PARAMETER
FROM
TO
1.2 ± 0.1 V
1.5 ± 0.1 V
3.3 ± 0.3 V
5.0 ± 0.5 V
UNIT
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
60 1.5
60 1.5
40 0.7
40 0.7
60 0.3
60 0.3
22 1.5
26 1.5
15 0.7
16 0.7
17 0.3
17 0.3
21.4
25.4
1
1
10.5 0.7
11 0.7
8.5 0.4
0.4
7.5 0.3
0.3
7
7.5
7
A
B
A
A
B
A
B
9
Propagation
delay
tpd
tdis
ten
ns
ns
ns
11 0.4
12 0.4
17 0.3
17 0.3
40 1.6
40 1.6
17 0.7
17 0.7
40 1.3
40 1.3
8.5 0.3
B
9
0.3
8
7.5
17
17
20
20
17
17
17
17
17 0.3
17 0.3
30 1.4
30 1.4
17 0.7
17 0.7
17 0.3
17 0.3
25 0.7
25 0.7
17 0.7
17 0.7
23 0.9
23 0.9
OE
OE
OE
OE
Disable time
Enable time
65
65
2
2
45
45
2
2
60 0.7
60 0.7
110 1.5
110 1.5
17 0.7
17 0.7
55 1.5
55 1.5
30
30
1
1
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6.12 Operating Characteristics
TA = 25℃ (1)
SUPPLY VOLTAGE (VCCB = VCCA
)
TEST
CONDITIONS
PARAMETER
1.2 ± 0.1V 1.5 ± 0.1V 1.8 ± 0.15V 2.5 ± 0.2V 3.3 ± 0.3V 5.0 ± 0.5V UNIT
TYP
2
TYP
2
TYP
2
TYP
2
TYP
2
TYP
3
A to B: outputs enabled
A to B: outputs disabled
B to A: outputs enabled
B to A: outputs disabled
A to B: outputs enabled
A to B: outputs disabled
B to A: outputs enabled
B to A: outputs disabled
A Port
CL = 0, RL = Open
f = 10 MHz
2
2
2
2
2
3
(2)
CpdA
pF
pF
12
2
12
2
12
2
13
2
13
2
16
3
trise = tfall = 1 ns
12
2
12
2
12
2
13
2
13
2
16
3
B Port
CL = 0, RL = Open
f = 10 MHz
(3)
CpdB
2
2
2
2
2
3
trise = tfall = 1 ns
2
2
2
2
2
3
(1) For additional information about how power dissipation capacitance affects power consumption, see the CMOS Power Consumption
and Cpd Calculation application report
(2) A-Port power dissipation capacitance per transceiver
(3) B-Port power dissipation capacitance per transceiver
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7 Parameter Measurement Information
7.1 Load Circuit and Voltage Waveforms
Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:
•
•
•
f = 1 MHz
ZO = 50 Ω
Δt/ΔV ≤ 1 ns/V
Measurement Point
2 x VCCO
Open
RL
S1
Output Pin
Under Test
(1)
GND
CL
RL
A. CL includes probe and jig capacitance.
Figure 7-1. Load Circuit
Table 7-1. Load Circuit Conditions
Parameter
VCCO
RL
CL
S1
VTP
N/A
tpd
Propagation (delay) time
1.1 V – 5.5 V
1.1 V – 1.6 V
1.65 V – 2.7 V
3.0 V – 5.5 V
1.1 V – 1.6 V
1.65 V – 2.7 V
3.0 V – 5.5 V
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
15 pF
15 pF
15 pF
15 pF
15 pF
15 pF
15 pF
Open
2 × VCCO
2 × VCCO
2 × VCCO
GND
0.1 V
0.15 V
0.3 V
0.1 V
0.15 V
0.3 V
ten, tdis Enable time, disable time
ten, tdis Enable time, disable time
GND
GND
(1)
VCCI
(1)
VCCI
100 kHz
Input A, B
VCCI / 2
VCCI / 2
Input A, B
500 ps/V œ 1 s/V
0 V
0 V
VOH
(2)
VOH
tpd
tpd
(2)
Ensure Monotonic
Rising and Falling Edge
Output B, A
(2)
VOL
Output B, A
VCCI / 2
VCCI / 2
(2)
VOL
1. VCCI is the supply pin associated with the input port.
2. VOH and VOL are typical output voltage levels that occur with
specified RL, CL, and S1
1. VCCI is the supply pin associated with the input port.
2. VOH and VOL are typical output voltage levels that occur with
specified RL, CL, and S1
Figure 7-3. Input Transition Rise and Fall Rate
Figure 7-2. Propagation Delay
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VCCA
GND
OE
VCCA / 2
VCCA / 2
tdis
ten
(3)
VCCO
Output(1)
VCCO / 2
VOL + VTP
(4)
VOL
(4)
VOH
VOH - VTP
Output(2)
VCCO / 2
GND
A. Output waveform on the condition that input is driven to a valid Logic Low.
B. Output waveform on the condition that input is driven to a valid Logic High.
C. VCCO is the supply pin associated with the output port.
D. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
Figure 7-4. Enable Time And Disable Time
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8 Detailed Description
8.1 Overview
The SN74LXC8T245-Q1 is an 8-bit translating transceiver that uses two individually configurable power-supply
rails. The device is operational with both VCCA and VCCB supplies as low as 1.1 V and as high as 5.5 V.
Additionally, the device can be operated with VCCA = VCCB. The A port is designed to track VCCA, and the B port
is designed to track VCCB
.
The SN74LXC8T245-Q1 device is designed for asynchronous communication between data buses, and
transmits data from the A bus to the B bus or from the B bus to the A bus based on the logic level of the
direction-control input (DIR). The output-enable input ( OE) is used to disable the outputs so the buses are
effectively isolated. The control pins of the SN74LXC8T245-Q1 (DIR and OE) are referenced to VCCA. To ensure
the high-impedance state of the level shifter I/Os during power up or power down, the OEpin should be tied to
VCCA through a pullup resistor.
This device is fully specified for partial-power-down applications using the Ioff current. The Ioff protection circuitry
ensures that no excessive current is drawn from or sourced into an input, output, or I/O while the device is
powered down.
The VCC isolation or VCC disconnect feature ensures that if either VCC is less than 100 mV or disconnected with
the complementary supply within recommended operating conditions, both I/O ports are weakly pulled-down and
then set to the high-impedance state by disabling their outputs while the supply current is maintained. The Ioff-float
circuitry ensures that no excessive current is drawn from or sourced into an input, output, or I/O while the supply
is floating.
Glitch-free power supply sequencing allows either supply rail to be powered on or off in any order while providing
robust power sequencing performance.
8.2 Functional Block Diagram
VCCB
VCCA
DIR
OE
B1
B8
A1
A8
To other 7 channels
GND
Figure 8-1. SN74LXC8T245-Q1 FBD
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8.3 Feature Description
8.3.1 CMOS Schmitt-Trigger Inputs with Integrated Pulldowns
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics,
which makes this device extremely tolerant to slow or noisy inputs. Driving the inputs slowly will increase
dynamic current consumption of the device. For additional information regarding Schmitt-trigger inputs, please
see Understanding Schmitt Triggers.
8.3.1.1 I/O's with Integrated Dynamic Pull-Down Resistors
Input circuits of the data I/O's are always active even when the device is disabled. It is recommended to keep a
valid voltage level at the I/O's to avoid high current consumption. To help avoid floating inputs on the I/O's during
disabling, this device has 100-kΩ typical integrated weak dynamic pull-downs on all data I/O's. When the device
is disabled, the dynamic pull-downs are activated for only a short period of time to help drive and keep low any
floating inputs before the device I/O's become high impedance. If the I/O lines are to be floated after the device
is disabled, it is recommended to keep them at a valid input voltage level using external pull-downs. This feature
is ideal for loads of 30 pF or less. If greater capactive loading is present then external pull-downs are
recommended. If an external pull-up is required, it should be no larger than 15 kΩ to avoid contention with the
100 kΩ internal pull-down.
8.3.1.2 Control Inputs with Integrated Static Pull-Down Resistors
Similar to the data I/O's, floating control inputs can cause high current consumption. To help avoid this concern,
this device has integrated weak static pull-downs of 5-MΩ typical on the control inputs (DIR and OE). These pull-
downs are always present so for example if the DIR pin is left floating, then the B port will be configured as an
input and the A port configured as an output.
8.3.2 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at
all times.
8.3.3 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting
current backflow into the device. The maximum leakage into or out of any input or output pin on the device is
specified by Ioff in the Electrical Characteristics.
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8.3.4 VCC Isolation and VCC Disconnect (Ioff-float
)
This device has I/O's with Integrated Dynamic Pull-Down Resistors. The I/O's will get pulled down and then enter
a high-impedance state when either supply is < 100 mV or left floating (disconnected), while the other supply is
still connected to the device. It is recommended that the I/O's for this device are not driven and kept at a logic
low state prior to floating (disconnecting) either supply.
The maximum supply current is specified by ICCx, while VCCx is floating, in the Electrical Characterstics. The
maximum leakage into or out of any input or output pin on the device is specified by Ioff(float) in the Electrical
Characteristics
VCCA
VCCB
ICCB maintained
Supply disconnected
VCCA
VCCB
DIR
OE
Disabled
Hi-Z
B1
Hi-Z
A1
Ioff(float)
Ioff(float)
Disabled
GND
Figure 8-2. VCC Disconnect Feature
8.3.5 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Recommended Operating Conditions.
8.3.6 Glitch-free Power Supply Sequencing
Either supply rail may be powered on or off in any order without producing a glitch on the I/Os (that is, where the
output erroneously transitions to VCC when it should be held low or vice versa). Glitches of this nature can be
misinterpreted by a peripheral as a valid data bit, which could trigger a false device reset of the peripheral, a
false device configuration of the peripheral, or even a false data initialization by the peripheral.
8.3.7 Negative Clamping Diodes
The inputs and outputs to this device have negative clamping diodes as depicted in Figure 8-3.
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CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input negative-voltage and output voltage ratings may be exceeded if the input and
output clamp-current ratings are observed.
VCCA VCCB
Device
Input or I/O
configured
as input
Level
Shifter
I/O configured
as output
-IIK
-IOK
GND
Figure 8-3. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.8 Fully Configurable Dual-Rail Design
Both the VCCA and VCCB pins can be supplied at any voltage from 1.1 V to 5.5 V, making the device suitable for
translating between any of the voltage nodes (1.2 V, 1.5 V, 1.8 V, 3.3 V, and 5.0 V).
8.3.9 Supports High-Speed Translation
The SN74LXC8T245-Q1 device can support high data-rate applications. The translated signal data rate can be
up to 420 Mbps when the signal is translated from 3.3 V to 5.0 V.
8.4 Device Functional Modes
Table 8-1. Function Table
CONTROL INPUTS (1)
PORT STATUS
OPERATION
OE
L
DIR
L
A PORT
B PORT
Input (Hi-Z)
Output (Enabled)
Input (Hi-Z)
B data to A bus
A data to B bus
Isolation
L
H
Output (Enabled)
Input (Hi-Z)
H
X
Input (Hi-Z)
(1) Input circuits of the data I/Os are always active and should be kept at a valid logic level.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LXC8T245-Q1 device can be used in level-translation applications for interfacing devices or systems
operating at different interface voltages with one another. The SN74LXC8T245-Q1 device is ideal for use in
applications where a push-pull driver is connected to the data I/Os. The max data rate can be up to 420 Mbps
when device translates a signal from 3.3 V to 5.0 V.
9.2 Typical Application
VCCB
VCCA
PWM0
PWM1
GPIO0
GPIO1
LED Array,
FET Array,
Buzzer,
MCU,
Controller
Etc...
PWM7
GPIO7
1010
SN74LXC8T245
Figure 9-1. LED Driver Application
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 9-1.
Table 9-1. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUES
1.1 V to 5.5 V
Input voltage range
Output voltage range
1.1 V to 5.5 V
9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
•
Input voltage range
– Use the supply voltage of the device that is driving the SN74LXC8T245-Q1 device to determine the input
voltage range. For a valid logic-high, the value must exceed the positive-going input-threshold voltage
(Vt+) of the input port. For a valid logic low the value must be less than the negative-going input-threshold
voltage (Vt-) of the input port.
•
Output voltage range
– Use the supply voltage of the device that the SN74LXC8T245-Q1 device is driving to determine the output
voltage range.
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10 Power Supply Recommendations
Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing
without any supply sequencing requirements such as ramp order or ramp rate.
This device was designed with various power supply sequencing methods in mind to help prevent unintended
triggering of downstream devices, as described in Glitch-free Power Supply Sequencing.
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended:
•
Use bypass capacitors on the power supply pins and place them as close to the device as possible. A 0.1-µF
capacitor is recommended, but transient performance can be improved by having both 1-µF and 0.1-µF
capacitors in parallel as bypass capacitors.
•
The high drive capability of this device creates fast edges into light loads so routing and load conditions
should be considered to prevent ringing.
11.2 Layout Example
Legend
Via to VCCA
Via to VCCB
A
B
G
Via to GND
Copper Traces
SN74LXC8T245QPWRQ1
VCCA
VCCB
0.1µF
1
2
3
4
5
6
7
24
23
22
21
20
19
18
020 1
0.1µF
020 1
A
G
B
G
VCCB
DIR
G
A1
A2
OE
B1
B2
B3
B4
B5
B6
B7
B8
GND
A3
A4
From
Controller
To LED
Array
A5
A6
8
17
16
15
14
13
A7
9
A8
10
11
12
GND
G
G
G
GND
Figure 11-1. Layout Example - SN74LXC8T245PW-Q1
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12 Device and Documentation Support
12.1 Regulatory Requirements
No statutory or regulatory requirements apply to this device.
There are no special characteristics for this product.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CLXC8T245QRHLRQ1
PCLXC8T245QPWRQ1
PREVIEW
ACTIVE
VQFN
RHL
PW
24
24
1000
2000
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
TSSOP
SN74LXC8T245QPWRQ1
PREVIEW
TSSOP
PW
24
2000
TBD
Call TI
Call TI
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2020
Addendum-Page 2
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
B
13
0.30
24X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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