SN74LXCH8T245RHLR [TI]

具有可配置电压转换和三态输出的 8 位双电源总线收发器 | RHL | 24 | -40 to 125;


型号：	SN74LXCH8T245RHLR
厂家：	TEXAS INSTRUMENTS
描述：	具有可配置电压转换和三态输出的 8 位双电源总线收发器 \| RHL \| 24 \| -40 to 125 总线收发器
文件：	总37页 (文件大小：1732K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74LXCH8T245

ZHCSN53B –DECEMBER 2019 –REVISED MARCH 2021

具有可配置电平转换的SN74LXCH8T245 8 位转换收发器

1 特性

3 说明

• 完全可配置的双电源轨设计可允许各个端口在1.1V

至5.5V 范围内运行

• 稳健、无干扰电源定序

• 在3.3V 至5.0V 范围内，支持高达420Mbps 的速

率

• 总线保持数据输入消除了对外部上拉或下拉电阻器

的需求

• 施密特触发控制输入可实现慢速或高噪声输入

• 带集成静态下拉电阻器的控制输入允许浮动控制输

入

SN74LXCH8T245 是一款 8 位双电源同相双向电压电

平转换器件，具有总线保持电路。 Ax 引脚和控制引脚

（DIR 和 OE）以 VCCA 逻辑电平为基准，Bx 引脚以

VCCB 逻辑电平为基准。A 端口能够接受 1.1V 至5.5V

的 I/O 电压，而 B 端口可接受 1.1V 至 5.5V 的 I/O 电

压。如果OE 设为低电平，DIR 上为高电平时允许数据

从 A 传输到 B，DIR 上为低电平时允许数据从 B 传输

到A。OE 设为高电平时，Ax 和Bx 引脚均处于高阻抗

状态。请参阅器件功能模式，了解控制逻辑的运行摘

要。

• 高驱动强度（在5V 时最高达32mA）

• 低功耗

器件信息⁽¹⁾

封装尺寸（标称值）

器件型号

封装

– 最大值4µA (25°C)

– 最大值12µA（–40°C 至125°C）

• VCC 隔离和VCC 断开特性

SN74LXCH8T245PWR

SN74LXCH8T245RHLR

TSSOP (24) 7.80mm × 6.40mm

VQFN (24)

5.50mm × 3.50mm

– 如果任何一个VCC 电源低于100mV，则所有

I/O 均变为高阻抗状态

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

– Ioff-float 支持VCC 断开操作

• I_off支持局部断电模式运行

• 兼容LVC 系列电平转换器

V_CCB

V_CCA

DIR

• 控制逻辑（DIR 和OE）以VCCA 为基准

• 工作温度范围为–40°C 至+125°C

• 闩锁性能超出100mA，符合JESD 78 II 类规范的

要求

• ESD 保护性能超过JESD 22 规范要求

Bus-Hold

– 4000V 人体放电模型

– 1000V 充电器件模型

To other 7 channels

GND

2 应用

• 消除慢速或高噪声输入信号

• 驱动指示LED 或蜂鸣器

• 机械开关去抖

功能模块图

• 通用I/O 电平转换

• 推挽电平转换（UART、SPI、JTAG 等等。）

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCES917

SN74LXCH8T245

ZHCSN53B –DECEMBER 2019 –REVISED MARCH 2021

www.ti.com.cn

Table of Contents

8 Detailed Description......................................................19

8.1 Overview...................................................................19

8.2 Functional Block Diagram.........................................19

8.3 Feature Description...................................................20

8.4 Device Functional Modes..........................................22

9 Application and Implementation..................................23

9.1 Application Information............................................. 23

9.2 Typical Application.................................................... 23

10 Power Supply Recommendations..............................25

11 Layout...........................................................................25

11.1 Layout Guidelines................................................... 25

11.2 Layout Example...................................................... 25

12 Device and Documentation Support..........................26

12.1 Documentation Support ......................................... 26

12.2 接收文档更新通知................................................... 26

12.3 支持资源..................................................................26

12.4 Trademarks.............................................................26

12.5 静电放电警告.......................................................... 26

12.6 术语表..................................................................... 26

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings ....................................... 4

6.2 ESD Ratings .............................................................. 4

6.3 Recommended Operating Conditions ........................5

6.4 Thermal Information ...................................................5

6.5 Electrical Characteristics ............................................6

6.6 Switching Characteristics, V_CCA= 1.2 ± 0.1 V............ 9

6.7 Switching Characteristics, V_CCA= 1.5 ± 0.1 V.......... 10

6.8 Switching Characteristics, V_CCA= 1.8 ± 0.15 V........ 11

6.9 Switching Characteristics, V_CCA= 2.5 ± 0.2 V.......... 12

6.10 Switching Characteristics, V_CCA= 3.3 ± 0.3 V........ 13

6.11 Switching Characteristics, V_CCA= 5.0 ± 0.5 V........ 14

6.12 Switching Characteristics: T_sk, T_MAX......................15

6.13 Operating Characteristics....................................... 15

6.14 Typical Characteristics............................................16

7 Parameter Measurement Information..........................17

7.1 Load Circuit and Voltage Waveforms........................17

Information.................................................................... 26

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (January 2021) to Revision B (March 2021)

Page

• Updated t_pdvalues in Switching Characteristics, V_CCA= 1.2 ± 0.1 V section.....................................................9

• Updated t_pdvalues in Switching Characteristics, V_CCA= 1.5 ± 0.1 V section...................................................10

• Updated t_pdvalues in Switching Characteristics, V_CCA= 1.8 ± 0.15 V section................................................. 11

• Updated t_pdvalues in Switching Characteristics, V_CCA= 2.5 ± 0.2 V section...................................................12

• Updated t_pdvalues in Switching Characteristics, V_CCA= 3.3 ± 0.3 V section...................................................13

• Updated t_pdvalues in Switching Characteristics, V_CCA= 5.0 ± 0.5 V section...................................................14

• Changed the t_sk–output skew's maximum operating free-air temperature (T_A) range for V_CCIand V_CCOin

the Switching Characteristics: T_sk, T_MAXsection.............................................................................................. 15

Changes from Revision * (January 2021) to Revision A (January 2021)

Page

• Changed I_OZspec at 25C................................................................................................................................... 6

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5 Pin Configuration and Functions

V_CCA

DIR

V_CCB

GND

V_CCB

DIR

PAD

GND

All packages are on the same relative scale.

图5-1. PW, and RHL Package 24-Pin TSSOP, and VQFN Transparent Top View

表5-1. Pin Functions

I/O

DESCRIPTION

NAME

PW, RHL

I/O

Input or output A1. Referenced to V_CCA

Input or output A2. Referenced to V_CCA

Input or output A3. Referenced to V_CCA

Input or output A4. Referenced to V_CCA

Input or output A5. Referenced to V_CCA

Input or output A6. Referenced to V_CCA

Input or output A7. Referenced to V_CCA

Input or output A8. Referenced to V_CCA

Input or output B1. Referenced to V_CCB

Input or output B2. Referenced to V_CCB

Input or output B3. Referenced to V_CCB

Input or output B4. Referenced to V_CCB

Input or output B5. Referenced to V_CCB

Input or output B6. Referenced to V_CCB

Input or output B7. Referenced to V_CCB

Input or output B8. Referenced to V_CCB

DIR

Direction-control signal for all ports. Referenced to V_CCA.

Ground.

—

GND

—

Output Enable. Pull to GND to enable all outputs. Pull to V_CCAto place all outputs in high-

impedance mode. Referenced to V_CCA

V_CCA

A-port supply voltage. 1.1 V ≤V_CCA≤5.5 V.

B-port supply voltage. 1.1 V ≤V_CCB≤5.5 V.

Thermal pad. May be grounded (recommended) or left floating.

—

V_CCB

PAD

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

–50

MAX UNIT

V_CCA

V_CCB

Supply voltage A

Supply voltage B

6.5

I/O Ports (A Port)

I/O Ports (B Port)

Control Inputs

A Port

6.5

V_I

Input Voltage⁽²⁾

6.5

Voltage applied to any output in the high-impedance or power-off

state⁽²⁾

V_O

B Port

6.5

A Port

V_CCA+ 0.5

V_CCB+ 0.5

Voltage applied to any output in the high or low state^{(2) (3)}

B Port

I_IK

I_OK

I_O

Input clamp current

V_I< 0

Output clamp current

V_O< 0

–50

Continuous output current

Continuous current through V_CCor GND

Junction Temperature

50 mA

200 mA

150 °C

–50

–200

T_j

T_stg

Storage temperature

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure beyond the limits listed in Recommended Operating Conditions. may affect device

reliability.

(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

(3) The output positive-voltage rating may be exceeded up to 6.5 V maximum if the output current rating is observed.

6.2 ESD Ratings

VALUE

±4000

±1000

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

1.1

MAX UNIT

V_CCA

V_CCB

Supply voltage A

Supply voltage B

5.5

1.1

V_CCI= 1.1 V - 1.3 V

V_CCI= 1.4 V - 1.95 V

V_CCI= 2.3 V - 2.7 V

V_CCI= 3.0 V - 3.6 V

V_CCI= 4.5 V - 5.5 V

V_CCI= 1.1 V - 1.3 V

V_CCI= 1.4 V - 1.95 V

V_CCI= 2.3 V - 2.7 V

V_CCI= 3.0 V - 3.6 V

V_CCI= 4.5 V - 5.5 V

V_CCO= 1.1 V

V_CCIx 0.8

V_CCIx 0.65

1.7

Data Inputs

(Ax, Bx)

(Referenced to V_CCI

High-level input

voltage

V_IH

)

V_CCIx 0.7

V_CCIx 0.2

V_CCIx 0.35

0.7

Data Inputs

(Ax, Bx)

(Referenced to V_CCI

Low-level input

voltage

V_IL

0.8

V_CCIx 0.3

–0.1

–2

V_CCO= 1.4 V

V_CCO= 1.65 V

–4

I_OH

High-level output current

V_CCO= 2.3 V

–12

–24

–32

0.1

V_CCO= 3 V

V_CCO= 4.5 V

V_CCO= 1.1 V

V_CCO= 1.4 V

V_CCO= 1.65 V

I_OL

Low-level output current

Input voltage

V_CCO= 2.3 V

V_CCO= 3 V

V_CCO= 4.5 V

V_I

5.5

Active State

Tri-State

V_CCO

5.5

V_O

Output voltage

Input transition rise and fall time

Operating free-air temperature

20 ns/V

125 °C

Δt/Δv

T_A

–40

(1) V_CCIis the V_CCassociated with the input port. V_CCOis the V_CCassociated with the output port.

6.4 Thermal Information

SN74LXC8T245

THERMAL METRIC⁽¹⁾

PW (TSSOP)

24 PINS

98.2

RHL (VQFN)

24 PINS

45.6

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

42.3

41.0

53.3

23.3

Y_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

5.8

2.2

Y_JB

52.9

23.3

R_θJC(bottom)

N/A

13.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics app report.

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6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

Operating free-air temperature (T_A)

25°C

MIN TYP MAX MIN TYP MAX MIN TYP MAX

PARAMETER

TEST CONDITIONS

V_CCA

V_CCB

UNIT

–40°C to 85°C

–40°C to 125°C

1.1 V

0.44

0.60

0.76

1.08

1.48

2.19

2.65

0.17

0.28

0.35

0.56

0.89

1.51

1.88

0.2

0.88 0.44

0.98 0.60

1.13 0.76

1.56 1.08

1.92 1.48

2.74 2.19

3.33 2.65

0.48 0.17

0.6 0.28

0.88

0.98

1.13

1.56

1.92

2.74

3.33

0.48

0.6

1.4 V

1.65 V

2.3 V

3 V

1.4 V

1.65 V

2.3 V

3 V

Positive-

going input-

threshold

voltage

Control Inputs

(OE, DIR)

(Referenced to

V_T+

V_CCA

)

4.5 V

5.5 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

4.5 V

5.5 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

Negative-

going input-

threshold

voltage

Control Inputs

(OE, DIR)

(Referenced to

0.71 0.35

0.71

V_T-

0.56

1.5 0.89

1.51

2.46 1.88

0.4 0.2

0.5 0.25

1.5

V_CCA

)

4.5 V

5.5 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

4.5 V

5.5 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

2.46

0.4

0.25

0.3

0.5

Input-

threshold

Control Inputs

(OE, DIR)

0.55

0.3

0.65 0.38

0.72 0.46

0.93 0.58

1.06 0.69

V_CCO

0.55

0.65

0.72

0.93

1.06

0.38

0.46

0.58

0.69

V_CCO

ΔV_T

hysteresis

(Referenced to

V_CCA

)

(V_T+–V_T-)

4.5 V

5.5 V

4.5 V

5.5 V

1.1V –

5.5V

1.1V –

5.5V

I_OH= –100 µA

–

0.1

–

0.1

1.4 V

1.65 V

2.3 V

3 V

1.4 V

1.65 V

2.3 V

3 V

1.2

1.9

2.4

3.8

1.2

1.9

2.4

3.8

I_OH= –4 mA

I_OH= –8 mA

I_OH= –12 mA

I_OH= –24 mA

I_OH= –32 mA

High-level

output

V_OH

voltage ⁽³⁾

4.5 V

1.1V –

5.5V

1.1V –

5.5V

I_OL= 100 µA

0.1

I_OL= 4 mA

I_OL= 8 mA

I_OL= 12 mA

I_OL= 24 mA

I_OL= 32 mA

V_I= 0.39

1.4 V

1.65 V

2.3 V

3 V

1.4 V

1.65 V

2.3 V

3 V

0.3

0.45

0.3

0.55

0.3

0.45

0.3

Low-level

output

V_OL

voltage ⁽⁴⁾

0.55

4.5 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

4.5 V

1.1 V

1.4 V

1.65 V

2.3 V

3 V

V_I= 0.49

Bus-hold low

sustaining

current

V_I= 0.58

I_BHL

µA

V_I= 0.70

Port A or Port

B ⁽⁶⁾

V_I= 0.80

V_I= 1.35

4.5 V

100

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6.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

Operating free-air temperature (T_A)

PARAMETER

TEST CONDITIONS

V_CCA

V_CCB

25°C

MIN TYP MAX MIN TYP MAX MIN TYP MAX

UNIT

–40°C to 85°C

–40°C to 125°C

V_I= 0.71 V

V_I= 0.91 V

V_I= 1.07 V

V_I= 1.70 V

V_I= 2.00 V

1.1 V

–4

–15

–25

–45

–75

–4

–10

–20

–45

–75

1.4 V

1.65 V

2.3 V

3 V

1.4 V

1.65 V

2.3 V

3 V

Bus-hold high

sustaining

current

I_BHH

µA

Port A or Port

B ⁽⁷⁾

–

100

–

100

V_I= 3.15 V

4.5 V

1.3 V

1.6 V

1.95 V

2.7 V

3.6 V

5.5 V

1.3 V

1.6 V

1.95 V

2.7 V

3.6 V

5.5 V

1.3 V

125

200

300

500

900

–75

125

200

300

500

900

–75

Bus-hold low

Ramp input up

V_I= 0 to V_CCI

I_BHLOoverdrive

µA

current ⁽⁸⁾

–

125

–

125

1.6 V

1.95 V

2.7 V

3.6 V

5.5 V

1.6 V

1.95 V

2.7 V

3.6 V

5.5 V

–

200

–

200

Bus-hold high

Ramp input down

V_I= V_CCIto 0

I_BHHOoverdrive

µA

–

300

–

300

current ⁽⁹⁾

–

500

–

500

–

900

–

900

Control inputs

(DIR, OE)

V_I= V_CCAor GND

1.1V –

5.5V

1.1V –

5.5V

1.5

0.3

1.5

µA

–0.1

–0.3

–0.1

–1

–0.1

–2

Input leakage

current

I_I

Data Inputs

(Ax, Bx)

V_I= V_CCIor GND

1.1V –

5.5V

1.1V –

5.5V

A Port

V_Ior V_O= 0 V - 5.5 0 V

2.5

0 V –5.5 V –1.5

–2

–2.5

Partial power

down current

I_off

µA

B Port

V_Ior V_O= 0 V - 5.5

0 V

0 V –5.5 V

–1.5

–2

A Port

V_Ior V_O= GND

Floating

1.5

2.5

0 V –5.5 V –1.5

–2

–2.5

supply Partial

power down

current

I_off-float

µA

B Port

V_Ior V_O= GND

0 V - 5.5 V Floating

–1.5

–1

A or B Port: (Rev)

V_I= V_CCIor GND

V_O= V_CCOor GND

OE = V_T+(MAX)

Tri-state

1.1V –

5.5V

1.1V –

5.5V

I_OZ

output current

–1

–2

(5)

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6.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

Operating free-air temperature (T_A)

25°C

MIN TYP MAX MIN TYP MAX MIN TYP MAX

PARAMETER

TEST CONDITIONS

V_CCA

V_CCB

UNIT

–40°C to 85°C

–40°C to 125°C

1.1V –

5.5V

1.1V –

5.5V

V_CCAsupply V_I= V_CCIor GND

current I_O= 0

0 V

5.5 V

0 V

–0.2

–0.5

–1

I_CCA

µA

5.5 V

Floating

1.1V –

5.5V

1.1V –

5.5V

V_CCBsupply V_I= V_CCIor GND

0 V

5.5 V

0 V

I_CCB

µA

current

I_O= 0

5.5 V

Floating

–0.2

–0.5

–1

5.5 V

Combined

supply

current

I_CCA

I_CCB

V_I= V_CCIor GND

I_O= 0

1.1V –

5.5V

1.1V –

5.5V

12 µA

Control inputs (DIR,

OE):

V_I= V_CCA–0.6 V

A port = VCCA or

GND

V_CCA

additional

supply

current per

input

3.0 V –

5.5V

3.0 V –

5.5V

75 µA

ΔI_CCA

B Port = open

Control Input

Capacitance

C_i

V_I= 3.3 V or GND

3.3 V

2.9

5.9

OE = V_CCA, V_O

Data I/O

Capacitance

C_io

1.65V DC +1 MHz

-16 dBm sine wave

10 pF

(1) V_CCIis the V_CCassociated with the input port.

(2) V_CCOis the V_CCassociated with the output port.

(3) Tested at V_I= V_T+(MAX).

(4) Tested at V_I= V_T-(MIN).

(5) For I/O ports, the parameter I_OZincludes the input leakage current.

(6) I_BHLshould be measured after lowering V_Ito GND and then raising it to the defined input voltage.

(7) I_BHHshould be measured after raising V_Ito V_CCIand then lowering it to the defined input voltage.

(8) An external driver must source at least I_BHLOto switch this node from low-to-high.

(9) An external driver must sink at least I_BHHOto switch this node from high to low.

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6.6 Switching Characteristics, V_CCA= 1.2 ± 0.1 V

See 图7-1 and 表7-1 for test circuit and loading. See Propagation Delay, Input Transition Rise and Fall Rate, and Enable Time And Disable Time for measurement

waveforms.

B-Port Supply Voltage (V_CCB

1.8 ± 0.15 V 2.5 ± 0.2 V

MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX

)

Test

Conditions

PARAMETER

FROM

1.2 ± 0.1 V

1.5 ± 0.1 V

3.3 ± 0.3 V

5.0 ± 0.5 V

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

100

Propagation

delay

t_pd

t_dis

t_en

Disable time

Enable time

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6.7 Switching Characteristics, V_CCA= 1.5 ± 0.1 V

See 图7-1 and 表7-1 for test circuit and loading. See Propagation Delay, Input Transition Rise and Fall Rate, and Enable Time And Disable Time for measurement

waveforms.

B-Port Supply Voltage (V_CCB

1.8 ± 0.15 V 2.5 ± 0.2 V

MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX

)

Test

Conditions

PARAMETER

FROM

1.2 ± 0.1 V

1.5 ± 0.1 V

3.3 ± 0.3 V

5.0 ± 0.5 V

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

Propagation

delay

t_pd

t_dis

t_en

Disable time

Enable time

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6.8 Switching Characteristics, V_CCA= 1.8 ± 0.15 V

See 图7-1 and 表7-1 for test circuit and loading. See Propagation Delay, Input Transition Rise and Fall Rate, and Enable Time And Disable Time for measurement

waveforms.

B-Port Supply Voltage (V_CCB

1.8 ± 0.15 V 2.5 ± 0.2 V

MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX

)

Test

Conditions

PARAMETER

FROM

1.2 ± 0.1 V

1.5 ± 0.1 V

3.3 ± 0.3 V

5.0 ± 0.5 V

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

Propagation

delay

t_pd

t_dis

t_en

Disable time

Enable time

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6.9 Switching Characteristics, V_CCA= 2.5 ± 0.2 V

See 图7-1 and 表7-1 for test circuit and loading. See Propagation Delay, Input Transition Rise and Fall Rate, and Enable Time And Disable Time for measurement

waveforms.

B-Port Supply Voltage (V_CCB

1.8 ± 0.15 V 2.5 ± 0.2 V

MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX

)

Test

Conditions

PARAMETER

FROM

1.2 ± 0.1 V

1.5 ± 0.1 V

3.3 ± 0.3 V

5.0 ± 0.5 V

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

Propagation

delay

t_pd

t_dis

t_en

Disable time

Enable time

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6.10 Switching Characteristics, V_CCA= 3.3 ± 0.3 V

See 图7-1 and 表7-1 for test circuit and loading. See Propagation Delay, Input Transition Rise and Fall Rate, and Enable Time And Disable Time for measurement

waveforms.

B-Port Supply Voltage (V_CCB

1.8 ± 0.15 V 2.5 ± 0.2 V

MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX

)

Test

Conditions

PARAMETER

FROM

1.2 ± 0.1 V

1.5 ± 0.1 V

3.3 ± 0.3 V

5.0 ± 0.5 V

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

6.5

7.5

8.5

Propagation

delay

t_pd

t_dis

t_en

Disable time

Enable time

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6.11 Switching Characteristics, V_CCA= 5.0 ± 0.5 V

See 图7-1 and 表7-1 for test circuit and loading. See Propagation Delay, Input Transition Rise and Fall Rate, and Enable Time And Disable Time for measurement

waveforms.

B-Port Supply Voltage (V_CCB

1.8 ± 0.15 V 2.5 ± 0.2 V

MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX

)

Test

Conditions

PARAMETER

FROM

1.2 ± 0.1 V

1.5 ± 0.1 V

3.3 ± 0.3 V

5.0 ± 0.5 V

UNIT

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

-40°C to 125°C

9.5

10.5

8.5

7.5

Propagation

delay

t_pd

t_dis

t_en

10.5

11.5

8.5

7.5

Disable time

Enable time

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6.12 Switching Characteristics: T_sk, T_MAX

over operating free-air temperature range (unless otherwise noted)

Operating free-air

temperature (T_A)

PARAMETER

TEST CONDITIONS

V_CCI

V_CCO

UNIT

-40°C to 125°C

MIN TYP MAX

200

100

420

200

Mbps

3.0 V –3.6 V

1.65 V –1.95 V

1.1 V –1.3 V

1.65 V –1.95 V

1.1 V –1.3 V

4.5 V –5.5 V

3.0 V –3.6 V

1.65 V –1.95 V

3.0 V –3.6 V

1.65 V –1.95 V

1.1 V –1.3 V

1.65 V –1.95 V

1.1 V –1.3 V

4.5 V –5.5 V

3.0 V –3.6 V

1.65 V –1.95 V

4.5 V –5.5 V

3.0 V –3.6 V

1.65 V –1.95 V

3.0 V –3.6 V

1.65 V –1.95 V

1.1 V –1.3 V

1.65 V –1.95 V

1.1 V –1.3 V

4.5 V –5.5 V

3.0 V –3.6 V

1.65 V –1.95 V

3.0 V –3.6 V

1.65 V –1.95 V

1.1 V –1.3 V

1.65 V –1.95 V

1.1 V –1.3 V

Up Translation

Down Translation

Up Translation

Down Translation

210

50% Duty Cycle

Input

One channel

switching

20% of pulse >

0.7*V_CCO

T_MAX- Maximum

Data Rate

100

210

20% of pulse <

0.3*V_CCO

0.5

1.5

Timing skew

between any two

switching outputs

within the same

device

t_sk–Output skew

0.5

1.5

6.13 Operating Characteristics

T_A= 25℃⁽¹⁾

Supply Voltage (V_CCB= V_CCA

)

PARAMETER

Test Conditions 1.2 ± 0.1V 1.5 ± 0.1V 1.8 ± 0.15V 2.5 ± 0.2V 3.3 ± 0.3V 5.0 ± 0.5V UNIT

TYP

A to B: outputs enabled

A to B: outputs disabled

B to A: outputs enabled

B to A: outputs disabled

A to B: outputs enabled

A to B: outputs disabled

B to A: outputs enabled

B to A: outputs disabled

A Port

CL = 0, RL = Open

f = 10 MHz

(2)

C_pdA

t_rise= t_fall= 1 ns

B Port

CL = 0, RL = Open

f = 10 MHz

(2)

C_pdB

t_rise= t_fall= 1 ns

(1) See the CMOS Power Consumption and C_pdCalculation application report for more information about power dissipation capacitance.

(2) C_pdAand C_pdBare respectively A-Port and B-Port power dissipation capacitances per transceiver.

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6.14 Typical Characteristics

4.5

1.8

1.6

1.4

1.2

V_CC= 5 V

V_CC= 3.3 V

V_CC= 2.5 V

3.5

2.5

0.8

0.6

0.4

V_CC= 1.8 V

V_CC= 1.5 V

V_CC= 1.2 V

1.5

2.5

7.5 10 12.5 15 17.5 20 22.5 25

I_OH Output High Current (mA)

图6-1. Typical (T_A=25°C) Output High Voltage (V_OH) vs Source

Current (I_OH

图6-2. Typical (T_A=25°C) Output High Voltage (V_OH) vs Source

Current (I_OH

)

0.45

0.4

0.45

0.4

0.35

0.3

0.35

0.3

0.25

0.2

0.25

0.2

0.15

0.1

0.15

0.1

V_CC= 5 V

V_CC= 3.3 V

V_CC= 2.5 V

V_CC= 1.8 V

V_CC= 1.5 V

V_CC= 1.2 V

0.05

2.5

7.5 10 12.5 15 17.5 20 22.5 25

I_OL Output Low Current (mA)

图6-3. Typical (T_A=25°C) Output High Voltage (V_OL) vs Sink

Current (I_OL

图6-4. Typical (T_A=25°C) Output High Voltage (V_OL) vs Sink

Current (I_OL

)

0.22

0.2

1.8

1.6

1.4

1.2

V_CC= 1.8 V

V_CC= 1.5 V

V_CC= 1.2 V

V_CC= 5 V

V_CC= 3.3 V

V_CC= 2.5 V

0.18

0.16

0.14

0.12

0.1

0.8

0.6

0.4

0.2

0.08

0.06

0.04

0.02

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

0.5

1.5

2.5

3.5

4.5

V_IN Input Voltage (V)

图6-6. Typical (T_A=25°C) Supply Current (I_CC) vs Input Voltage

(V_IN

图6-5. Typical (T_A=25°C) Supply Current (I_CC) vs Input Voltage

(V_IN

)

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7 Parameter Measurement Information

7.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

• f = 1 MHz

• Z_O= 50 Ω

• Δt/ΔV ≤1 ns/V

Measurement Point

2 x V_CCO

R_L

Output Pin

Under Test

Open

(1)

GND

C_L

R_L

A. C_Lincludes probe and jig capacitance.

图7-1. Load Circuit

表7-1. Load Circuit Conditions

Parameter

V_CCO

R_L

C_L

S₁

V_TP

N/A

t_pd

Propagation (delay) time

15 pF

Open

1.1 V –5.5 V

1.1 V –1.6 V

1.65 V –2.7 V

3.0 V –5.5 V

1.1 V –1.6 V

1.65 V –2.7 V

3.0 V –5.5 V

2 kΩ

2 × V_CCO

GND

0.1 V

0.15 V

0.3 V

0.1 V

0.15 V

0.3 V

t_en, t_disEnable time or disable time

GND

(1)

V_CCI

(1)

V_CCI

100 kHz

Input A, B

V_CCI/ 2

Input A, B

500 ps/V œ 1 s/V

0 V

V_OH

t_pd

(2)

V_OH

(2)

Ensure Monotonic

Rising and Falling Edge

Output B, A

V_CCI/ 2

(2)

V_OL

(2)

V_OL

1. V_CCIis the supply pin associated with the input port.

2. V_OHand V_OLare typical output voltage levels that occur

with specified R_L, C_L, and S₁.

2. V_OHand V_OLare typical output voltage levels that occur

with specified R_L, C_L, and S₁.

图7-3. Input Transition Rise and Fall Rate

图7-2. Propagation Delay

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V_CCA

GND

V_CCA/ 2

t_dis

t_en

(3)

V_CCO

Output⁽¹⁾

V_CCO/ 2

V_OL+ V_TP

(4)

V_OL

(4)

V_OH

V_OH- V_TP

Output⁽²⁾

V_CCO/ 2

GND

1. Output waveform on the condition that input is driven to a valid Logic Low.

2. Output waveform on the condition that input is driven to a valid Logic High.

3. V_CCOis the supply pin associated with the output port.

4. V_OHand V_OLare typical output voltage levels with specified R_L, C_L, and S₁.

图7-4. Enable Time And Disable Time

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8 Detailed Description

8.1 Overview

The SN74LXCH8T245 is an 8-bit translating transceiver that uses two individually configurable power-supply

rails. The device is operational with V_CCAand V_CCBsupplies as low as 1.1 V and as high as 5.5 V. Additionally,

the device operates with V_CCA= V_CCB. The A port is designed to track V_CCA, and the B port is designed to track

V_CCB

The SN74LXCH8T245 device is designed for asynchronous communication between data buses and transmits

data from the A bus to the B bus or from the B bus to the A bus based on the logic level of the direction-control

input (DIR). The output-enable input (OE) is used to disable the outputs so the buses are effectively isolated.

The control pins of the SN74LXCH8T245 (DIR and OE) are referenced to V_CCA. The OE pin should be tied to

V_CCAthrough a pullup resistor to ensure the high-impedance state of the level shifter I/Os during power up or

power down.

This device is fully specified for partial-power-down applications using the I_offcurrent. The I_offprotection circuitry

ensures that no excessive current is drawn from or sourced into an input, output, or I/O while the device is

powered down.

The V_CCisolation and V_CCdisconnect feature ensures that if either V_CCis less than 100 mV or floating with the

complementary supply within the recommended operating conditions, both I/O ports are set to the high-

impedance state by disabling their outputs and the supply current is maintained.

Glitch-free power supply sequencing allows either supply rail to power on or off in any order while providing

robust power sequencing performance.

8.2 Functional Block Diagram

V_CCB

V_CCA

DIR

Bus-Hold

Note: Bus-hold circuits are only present for data inputs, not control inputs

图8-1. SN74LXCH8T245 Functional Block Diagram

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8.3 Feature Description

8.3.1 CMOS Schmitt-Trigger Inputs with Integrated Pulldowns

Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input

capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum

input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the

Electrical Characteristics, using ohm's law (R = V ÷ I).

The Schmitt-trigger input architecture provides hysteresis as defined by ΔV_Tin the Electrical Characteristics,

which makes this device extremely tolerant to slow or noisy inputs. Driving the inputs slowly will increase

dynamic current consumption of the device. See Understanding Schmitt Triggers for additional information

regarding Schmitt-trigger inputs.

8.3.1.1 Control Inputs with Integrated Static Pull-Down Resistors

Similar to the data I/O's, floating control inputs can cause high current consumption. This device has integrated

weak static pull-downs of 5-MΩ typical on the control inputs (DIR and OE) to help avoid this concern. These

pull-downs are always present. For example, if the DIR pin is left floating, then the B port will be configured as an

input and the A port will be configured as an output.

8.3.2 Balanced High-Drive CMOS Push-Pull Outputs

A balanced output allows the device to sink and source similar currents. The high drive capability of this device

creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.

Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without

being damaged. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at

all times.

8.3.3 Partial Power Down (I_off)

The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting

current backflow into the device. I_offin the Electrical Characteristics specifies the maximum leakage into or out of

any input or output pin on the device.

8.3.4 V_CCIsolation and V_CCDisconnect

The inputs and outputs for this device enter a high-impedance state when either supply is <100 mV, requiring

one supply to connect to the device. Note: the bus-hold circuitry always remains active even when the device is

disabled and all outputs are in the high-impedance state.

Either supply can be disconnected (floated), while the other supply is still connected and the device will maitain

the maximum supply current specified by I_{CCx(floating)}, in the Electrical Characteristics. The I/O's will not enter a

high-impedance state unless the supply is disconnected after it is driven to <100 mV. I_off(float)in the Electrical

Characteristics specifies the maximum leakage into or out of any input or output pin on the device.

V_CCA

V_CCB

I_CCBmaintained

Supply disconnected

V_CCA

V_CCB

DIR

Disabled

Hi-Z

Bus-Hold

I_off(float)

Disabled

GND

图8-2. V_CCDisconnect Feature

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8.3.5 Over-Voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage as long as they remain below the maximum

input voltage value specified in the Recommended Operating Conditions.

8.3.6 Glitch-Free Power Supply Sequencing

Either supply rail may be powered on or off in any order without producing a glitch on the I/Os (that is, where the

output erroneously transitions to VCC when it should be held low or vice versa). Glitches of this nature can be

misinterpreted by a peripheral as a valid data bit, which could trigger a false device reset of the peripheral, a

false device configuration of the peripheral, or even a false data initialization by the peripheral.

8.3.7 Negative Clamping Diodes

The inputs and outputs to this device have negative clamping diodes as depicted in 图8-3.

CAUTION

Voltages beyond the values specified in 节 6.1 table can cause damage to the device. The input

negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current

ratings are observed.

V_CCAV_CCB

Device

Input or I/O

configured

as input

Level

Shifter

I/O configured

as output

-I_IK

-I_OK

GND

图8-3. Electrical Placement of Clamping Diodes for Each Input and Output

8.3.8 Fully Configurable Dual-Rail Design

The V_CCAand V_CCBpins can be supplied at any voltage from 1.1 V to 5.5 V, making the device suitable for

translating between any of the voltage nodes (1.2 V, 1.5 V, 1.8 V, 3.3 V, and 5.0 V).

8.3.9 Supports High-Speed Translation

The SN74LXCH8T245 device can support high data-rate applications. The translated signal data rate can be up

to 420 Mbps when the signal is translated from 3.3 V to 5.0 V.

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8.3.10 Bus-Hold Data Inputs

Each data input on this device includes a weak latch that maintains a valid logic level on the input. The state of

these latches is unknown at startup and remains unknown until the input has been forced to a valid high or low

state. After data is sent through a channel, the latch maintains the previous state on the input (if the line is left

floating). It is not recommended to use pull-up or pull-down resistors together with a bus-hold input, as it may

cause undefined inputs to occur which leads to excessive current consumption.

Bus-hold data inputs prevent floating inputs on this device. The Implications of Slow or Floating CMOS Inputs

application report explains the problems associated with leaving the CMOS inputs floating. These latches remain

active at all times, independent of all control signals such as direction control or output enable. The latches also

remain active when the device is in the partial power down state, corresponding supply is still present, or when

the I/O's are floated. The Bus-Hold Circuit application report has additional details regarding bus-hold inputs.

Level

Bus-Hold

Shifter

图8-4. Schematic Description of Location of Bus-Hold Circuits

8.4 Device Functional Modes

表8-1. Function Table⁽¹⁾

CONTROL INPUTS

OE DIR

Port Status

OPERATION

A PORT

B PORT

Input (Hi-Z)

Output (Enabled)

Input (Hi-Z)

B data to A bus

A data to B bus

Isolation

Output (Enabled)

Input (Hi-Z)

(1) Input circuits of the data I/Os are always active.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The SN74LXCH8T245 device can be used in level-translation applications for interfacing devices or systems

operating at different interface voltages with one another. The SN74LXCH8T245 device is ideal for use in

applications where a push-pull driver is connected to the data I/Os. The maximum data rate can be up to 420

Mbps when the device translates a signal from 3.3 V to 5.0 V.

9.2 Typical Application

1.2 V

5.0 V

0.1 µF

System

Controller

V_CCB

V_CCA

DIR

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

SN74LXC8T245

GND

图9-1. LED Driver Application

9.2.1 Design Requirements

Use the parameters listed in 表9-1 for this design example.

表9-1. Design Parameters

DESIGN PARAMETERS

EXAMPLE VALUES

1.1 V to 5.5 V

Input voltage range

Output voltage range

1.1 V to 5.5 V

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9.2.2 Detailed Design Procedure

To begin the design process, determine the following:

• Input voltage range:

– Use the supply voltage of the device that is driving the SN74LXCH8T245 device to determine the input

voltage range. The value must exceed the high-level input voltage (V_IH) of the input port for a valid logic-

high. The value must be less than the low-level input voltage (V_IL) of the input port for a valid logic low.

• Output voltage range:

– Use the device's supply voltage that the SN74LXCH8T245 device is driving to determine the output

voltage range.

9.2.3 Application Curve

图9-2. Up Translation at 2.5 MHz (1.2 V to 5 V)

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10 Power Supply Recommendations

Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing

without any supply sequencing requirements such as ramp order or ramp rate.

节8.3.6 describes how this device was designed with various power supply sequencing methods in mind to help

prevent unintended triggering of downstream devices.

11 Layout

11.1 Layout Guidelines

Following common printed-circuit board layout guidelines are recommended to ensure reliability of the device,

which follows:

• Use bypass capacitors on the power supply pins and place them as close to the device as possible. A 0.1 µF

capacitor is recommended, but transient performance can be improved by having both 1 µF and 0.1 µF

capacitors in parallel as bypass capacitors.

• The high drive capability of this device creates fast edges into light loads; so routing and load conditions

should be considered to prevent ringing.

11.2 Layout Example

Legend

Via to V_CCA

Via to V_CCB

Via to GND

Copper Traces

SN74LXCH8T245RHLR

V_CCA

V_CCB

DIR

V_CCB

From

Controller

PAD

To LED

Array

GND

图11-1. Layout Example

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, CMOS Power Consumption and C_pdCalculation application report

• Texas Instruments, Implications of Slow or Floating CMOS Inputs application report

• Texas Instruments, Semiconductor and IC Package Thermal Metrics appliction report

• Texas Instruments, System Considerations for Using Bus-Hold Curcuits to Avoid Floating Inputs application

report

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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3-Mar-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

SN74LXCH8T245PWR

SN74LXCH8T245RHLR

ACTIVE

TSSOP

VQFN

2000 RoHS & Green

3000 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

LXH8T245

LX8T245H

RHL

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

3-Mar-2021

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74LXCH8T245PWR TSSOP

SN74LXCH8T245RHLR VQFN

2000

3000

330.0

16.4

12.4

6.95

3.8

8.3

5.8

1.6

1.2

8.0

16.0

12.0

RHL

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74LXCH8T245PWR

SN74LXCH8T245RHLR

TSSOP

VQFN

2000

3000

356.0

367.0

356.0

367.0

35.0

RHL

Pack Materials-Page 2

PACKAGE OUTLINE

PW0024A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SEATING

PLANE

6.6

6.2

TYP

0.1 C

PIN 1 INDEX AREA

22X 0.65

7.15

7.9

7.7

NOTE 3

0.30

24X

4.5

4.3

NOTE 4

0.19

1.2 MAX

0.1

C A B

0.25

GAGE PLANE

0.15

0.05

(0.15) TYP

SEE DETAIL A

0.75

0.50

0 -8

DETAIL A

TYPICAL

4220208/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

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EXAMPLE BOARD LAYOUT

PW0024A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SYMM

24X (1.5)

(R0.05) TYP

24X (0.45)

22X (0.65)

SYMM

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4220208/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

PW0024A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

24X (1.5)

SYMM

(R0.05) TYP

24X (0.45)

22X (0.65)

SYMM

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

4220208/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

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PACKAGE OUTLINE

VQFN - 1 mm max height

RHL0024A

PLASTIC QUAD FLATPACK- NO LEAD

3.6

3.4

PIN 1 INDEX AREA

5.6

5.4

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2.05±0.1

2X 1.5

SYMM

0.5

0.3

24X

(0.1) TYP

18X 0.5

SYMM

4.05±0.1

4.5

0.30

24X

0.18

0.1

0.05

PIN 1 ID

(OPTIONAL)

C A B

4X (0.2)

2X (0.55)

4225250/A 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RHL0024A

PLASTIC QUAD FLATPACK- NO LEAD

(3.3)

(2.05)

2X (1.5)

SYMM

24X (0.6)

24X (0.24)

2X (0.4)

18X (0.5)

2X (1.105)

6X (0.67)

(4.05)

SYMM

4.6

4.4

(5.3)

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

(Ø 0.2) VIA

TYP

(R0.05) TYP

(0.775)

4X (0.2)

2X (0.55)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 18X

SOLDER MASK

OPENING

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED METAL

METAL

METAL UNDER

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4225250/A 09/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RHL0024A

PLASTIC QUAD FLATPACK- NO LEAD

(3.3)

(2.05)

2X (1.5)

SYMM

SOLDER MASK EDGE

TYP

24X (0.6)

24X (0.24)

18X (0.5)

SYMM

4.6

4.4

(5.3)

(1.34)

METAL TYP

(R0.05) TYP

2X (0.84)

6X (0.56)

4X (0.2)

2X (0.55)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

80% PRINTED COVERAGE BY AREA

SCALE: 18X

4225250/A 09/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

SN74LXCH8T245RHLR [TI]

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