SN74S1051PWG4 [TI]
12-Bit Schottky Barrier Diode Bus-Termination Array 16-TSSOP 0 to 70;
| 型号： | SN74S1051PWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-Bit Schottky Barrier Diode Bus-Termination Array 16-TSSOP 0 to 70 光电二极管 接口集成电路 |
| 文件： | 总17页 (文件大小：958K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74S1051
12-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003
D, N, NS, OR PW PACKAGE
(TOP VIEW)
Designed to Reduce Reflection Noise
Repetitive Peak Forward Current to 200 mA
12-Bit Array Structure Suited for
Bus-Oriented Systems
V
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC
CC
D12
D11
D10
D09
D08
D07
GND
D01
D02
D03
D04
D05
D06
GND
description/ordering information
This Schottky barrier diode bus-termination array
is designed to reduce reflection noise on memory
bus lines. This device consists of a 12-bit
high-speed Schottky diode array suitable for
clamping to V
and/or GND.
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
SOIC – D
Tube
SN74S1051N
SN74S1051N
Tube
SN74S1051D
S1051
0°C to 70°C
Tape and reel
Tape and reel
Tape and reel
SN74S1051DR
SN74S1051NSR
SN74S1051PWR
SOP – NS
74S1051
S1051
TSSOP – PW
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
schematic diagrams
D01 D02
D03 D04
D05 D06 D07 D08 D09
10 11 12
D10
13
D11
14
D12
15
V
CC
1
V
CC
16
2
3
4
5
6
7
8
9
GND GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74S1051
12-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Steady-state reverse voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
R
Continuous forward current, I : Any D terminal from GND or to V . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
F
CC
Total through all GND or V
terminals . . . . . . . . . . . . . . . . . . . . . . . 170 mA
CC
‡
Repetitive peak forward current , I
: Any D terminal from GND or V
Total through all GND or V
. . . . . . . . . . . . . . . . . . . . . 200 mA
FRM
CC
terminals . . . . . . . . . . . . . . . . . . . . 1 A
CC
Package thermal impedance, θ (see Note 1): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These values apply for t ≤ 100 µs, duty cycle ≤ 20%.
w
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
single-diode operation (see Note 2)
§
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
1.05
1.3
UNIT
I
F
I
F
I
F
I
F
I
F
= 18 mA
= 50 mA
= 18 mA
= 50 mA
= 200 mA
0.85
1.05
0.75
0.95
1.45
To V
CC
V
V
Static forward voltage
V
F
0.95
1.2
From GND
Peak forward voltage
Static reverse current
V
FM
To V
5
5
CC
From GND
I
R
V
R
= 7 V
µA
V
= 0 V,
= 2 V,
f = 1 MHz
f = 1 MHz
8
4
16
8
R
R
C
Total capacitance
pF
t
V
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
NOTE 2: Test conditions and limits apply separately to each of the diodes. The diodes not under test are open-circuited during the measurement
of these characteristics.
multiple-diode operation
§
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
2
UNIT
Total I current = 1 A,
See Note 3
See Note 3
0.8
F
I
x
Internal crosstalk current
mA
Total I current = 198 mA,
0.02
0.2
F
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
I is measured under the following conditions with one diode static, all others switching:
x
NOTE 3:
Switching diodes: t = 100 µs, duty cycle = 20%
Static diode: V = 5 V
The static diode input current is the internal crosstalk current, I .
w
R
x
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
PARAMETER
TEST CONDITIONS
= 10 mA,
MIN
TYP
MAX
UNIT
t
rr
Reverse recovery time
I
F
= 10 mA,
I
I
= 1 mA,
R = 100 Ω
L
8
16
ns
RM(REC)
R(REC)
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74S1051
12-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003
PARAMETER MEASUREMENT INFORMATION
50 Ω
450 Ω
Pulse
Generator
Sampling
Oscilloscope
(See Note A)
(See Note B)
DUT
90%
V
FM
V
F
Output
Waveform
Input Pulse
(See Note A)
(See Note B)
10%
t
r
NOTES: A. The input pulse is supplied by a pulse generator having the following characteristics: t = 20 ns, Z = 50 Ω, freq = 500 Hz,
r
O
duty cycle = 1%.
B. The output waveform is monitored by an oscilloscope having the following characteristics: t ≤ 350 ps, R = 50 Ω, C ≤ 5 pF.
r
i
i
Figure 1. Forward Recovery Voltage
DUT
Sampling
Oscilloscope
Pulse
Generator
I
F
(See Note B)
(See Note A)
t
rr
I
f
t
f
10%
0
Output
Waveform
(See Note B)
Input Pulse
(See Note A)
I
R(REC)
90%
I
RM(REC)
NOTES: A. The input pulse is supplied by a pulse generator having the following characteristics: t = 0.5 ns, Z = 50 Ω, t ≥ 50 ns,
f
O
w
duty cycle = 1%.
B. The output waveform is monitored by an oscilloscope having the following characteristics: t ≤ 350 ps, R = 50 Ω, C ≤ 5 pF.
r
i
i
Figure 2. Reverse Recovery Time
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74S1051
12-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003
APPLICATION INFORMATION
Large negative transients at the inputs of memory devices (DRAMs, SRAMs, EPROMs, etc.) or on the CLOCK lines
of many clocked devices can result in improper operation of the devices. The SN74S1051 diode termination array
helps suppress negative transients caused by transmission-line reflections, crosstalk, and switching noise.
Diode terminations have several advantages when compared to resistor termination schemes. Split-resistor or
Thevenin-equivalent termination can cause a substantial increase in power consumption. The use of a single resistor
togroundtoterminatealineusuallyresultsindegradationoftheoutputhighlevel, resultinginreducednoiseimmunity.
Series damping resistors placed on the outputs of the driver reduce negative transients, but they also can increase
propagation delays down the line because a series resistor reduces the output drive capability of the driving device.
Diode terminations have none of these drawbacks.
The operation of the diode arrays in reducing negative transients is explained in the following figures. The diode
conducts current when the voltage reaches a negative value large enough for the diode to turn on. Suppression of
negative transients is tracked by the current-voltage characteristic curve for that diode. Typical
current-versus-voltage curves for the SN74S1051 are shown in Figures 3 and 4.
To illustrate how the diode arrays act to reduce negative transients at the end of a transmission line, the test setup
in Figure 5 was evaluated. The resulting waveforms with and without the diode are shown in Figure 6.
The maximum effectiveness of the diode arrays in suppressing negative transients occurs when the diode arrays are
placed at the end of a line and/or the end of a long stub branching off a main transmission line. The diodes can also
reduce the negative transients that occur due to discontinuities in the middle of a line. An example of this is a slot in
a backplane that is provided for an add-on card.
DIODE FORWARD CURRENT
vs
DIODE FORWARD VOLTAGE
–100
T
A
= 25°C
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
V – Forward Voltage – V
I
Figure 3. Typical Input Current vs Input Voltage
(Lower Diode)
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74S1051
12-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003
DIODE FORWARD CURRENT
vs
DIODE FORWARD VOLTAGE
100
90
80
70
60
50
40
30
T
A
= 25°C
20
10
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
V – Forward Voltage – V
I
Figure 4. Typical Input Current vs Input Voltage
(Upper Diode)
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74S1051
12-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003
APPLICATION INFORMATION
Z
= 50 Ω
O
Length = 36 in.
Figure 5. Diode Test Setup
31.500 ns
56.500 ns
81.500 ns
End-of-
Line
Without
Diode
End-of-Line With Diode
Vmarker 1
Vmarker 2
Ch 2
= 1.880 V/div
Offset = 0.000 V
Timebase = 5.00 ns/V
Memory 1 = 1.880 V/div
Vmarker 1 = –1.353 V
Vmarker 2 = –3.647 V
Delay = 56.500 ns
Delta V = –2.293 V
Figure 6. Reduction of Negative Transients at the End of a Transmission Line
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
SN74S1051D
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
S1051
SN74S1051DE4
SN74S1051DG4
SN74S1051DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
40
40
Green (RoHS
& no Sb/Br)
S1051
Green (RoHS
& no Sb/Br)
S1051
D
2500
2500
2500
25
Green (RoHS
& no Sb/Br)
S1051
SN74S1051DRE4
SN74S1051DRG4
SN74S1051N
D
Green (RoHS
& no Sb/Br)
S1051
D
Green (RoHS
& no Sb/Br)
S1051
N
Pb-Free
(RoHS)
SN74S1051N
SN74S1051N
74S1051
74S1051
74S1051
S1051
SN74S1051NE4
SN74S1051NSR
SN74S1051NSRE4
SN74S1051NSRG4
SN74S1051PW
PDIP
N
25
Pb-Free
(RoHS)
N / A for Pkg Type
SO
NS
NS
NS
PW
PW
PW
PW
PW
PW
2000
2000
2000
90
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
SO
Green (RoHS
& no Sb/Br)
SO
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
Green (RoHS
& no Sb/Br)
SN74S1051PWE4
SN74S1051PWG4
SN74S1051PWR
SN74S1051PWRE4
SN74S1051PWRG4
90
Green (RoHS
& no Sb/Br)
S1051
90
Green (RoHS
& no Sb/Br)
S1051
2000
2000
2000
Green (RoHS
& no Sb/Br)
S1051
Green (RoHS
& no Sb/Br)
S1051
Green (RoHS
& no Sb/Br)
S1051
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74S1051DR
SN74S1051NSR
SN74S1051PWR
SOIC
SO
D
16
16
16
2500
2000
2000
330.0
330.0
330.0
16.4
16.4
12.4
6.5
8.2
6.9
10.3
10.5
5.6
2.1
2.5
1.6
8.0
12.0
8.0
16.0
16.0
12.0
Q1
Q1
Q1
NS
PW
TSSOP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74S1051DR
SN74S1051NSR
SN74S1051PWR
SOIC
SO
D
16
16
16
2500
2000
2000
333.2
367.0
367.0
345.9
367.0
367.0
28.6
38.0
35.0
NS
PW
TSSOP
Pack Materials-Page 2
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相关型号：
SN74S1052NE4
16-LINE DIODE BUS TERMINATION ARRAY, PDIP20, 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-001AD, DIP-20
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