SN74SSTU32866A [TI]
25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST; 25位可配置寄存缓冲器，具有地址奇偶校验
| 型号： | SN74SSTU32866A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST |
| 文件： | 总35页 (文件大小：654K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢗ ꢎꢄ ꢘ ꢊꢖꢖ ꢓꢕꢀꢀ ꢌꢙꢊꢓ ꢎꢄ ꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
D
Member of the Texas Instruments
Widebus+ Family
Pinout Optimizes DDR2 DIMM PCB Layout
D
D
D
Checks Parity on DIMM-Independent Data
Inputs
D
Able to Cascade with a Second
SN74SSTU32866A
D
Configurable as 25-Bit 1:1 or 14-Bit 1:2
Registered Buffer
RESET Input Disables Differential Input
Receivers, Resets All Registers, and
Forces All Outputs Low, Except QERR
D
D
D
D
D
Chip-Select Inputs Gate the Data Outputs
from Changing State and Minimizes System
Power Consumption
D
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Output Edge-Control Circuitry Minimizes
Switching Noise in an Unterminated Line
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Supports SSTL_18 Data Inputs
Differential Clock (CLK and CLK) Inputs
− 1000-V Charged-Device Model (C101)
Supports LVCMOS Switching Levels on the
Control and RESET Inputs
description/ordering information
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V V
operation. In the
CC
1:1 pinout configuration, only 1 device per DIMM is required to drive 9 SDRAM loads. In the 1:2 pinout
configuration, 2 devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs which are LVCMOS. All outputs are
edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except the
open-drain error (QERR) output.
The SN74SSTU32866A buffer operates from a differential clock (CLK and CLK). Data are registered at the
crossing of CLK going high and CLK going low.
The SN74SSTU32866A buffer accepts a parity bit from the memory controller on the parity bit (PAR_IN) input,
compares it with the data received on the DIMM-independent D-inputs (D2−D3, D5−D6, D8−D25 when C0 = 0
and C1 = 0; D2−D3, D5−D6, D8−D14 when C0 = 0 and C1=1; or D1−D6, D8−D13 when C0 = 1 and C1 = 1)
and indicates whether a parity error has occurred on the open-drain QERR pin (active low). The convention is
even parity; i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs,
combined with the parity input bit. To calculate parity, all DIMM-independent data inputs must be tied to a known
logic state.
When used as a single device, the C0 and C1 inputs are tied low. In this configuration, parity is checked on the
PAR_IN input signal, which arrives one cycle after the input data to which it applies. Two clock cycles after the
data are registered, the corresponding partial-parity-out (PPO) and QERR signals are generated.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
PACKAGE
LFBGA − ZKE
A
0°C to 70°C
Tape and reel SN74SSTU32866AZKER
SU866A
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
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Copyright 2005, Texas Instruments Incorporated
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1
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ꢗꢎ ꢄ ꢘ ꢊ ꢖꢖ ꢓ ꢕꢀꢀ ꢌꢙꢊꢓ ꢎ ꢄꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
description/ordering information (continued)
When used in pairs, the C0 input of the first register is tied low, and the C0 input of the second register is tied
high. The C1 input of both registers is tied high. Parity, which arrives one cycle after the data input to which it
applies, is checked on the PAR_IN input signal of the first device. Two clock cycles after the data are registered,
the corresponding PPO and QERR signals are generated on the second device. The PPO output of the first
register is cascaded to the PAR_IN of the second SN74SSTU32866A. The QERR output of the first
SN74SSTU32866A is left floating, and the valid error information is latched on the QERR output of the second
SN74SSTU32866A.
If an error occurs and the QERR output is driven low, then it stays latched low for a minimum of two clock cycles
or until RESET is driven low. If two or more consecutive parity errors occur, then the QERR output is driven low
and latched low for a clock duration equal to the parity-error duration or until RESET is driven low. The
DIMM-dependent signals (DCKE, DCS, DODT, and CSR) are not included in the parity-check computation.
The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to
register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low)
to 14-bit 1:2 (when high). C0 and C1 must not be switched during normal operation. They must be hard-wired
to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration,
the A6, D6, and H6 terminals are driven low and are do-not-use (DNU) pins.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and
CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is
cleared, and the data outputs are driven low quickly, relative to the time required to disable the differential input
receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required
to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the
time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the
SN74SSTU32866A ensures that the outputs remain low, thus ensuring there will be no glitches on the output.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (V
) inputs are allowed. In addition, when
REF
RESET is low, all registers are reset and all outputs are forced low, except QERR. The LVCMOS RESET and
Cn inputs always must be held at a valid logic high or low level.
The device also supports low-power active operation by monitoring both system chip select (DCS and CSR)
inputs and gates the Qn and PPO outputs from changing states when both DCS and CSR inputs are high. If
either DCS or CSR input is low, then the Qn and PPO outputs function normally. Also, if the internal low-power
signal (LPS1) is high (one cycle after DCS and CSR go high), then the device gates the QERR output from
changing states. If LPS1 is low, then the QERR output functions normally. The RESET input has priority over
the DCS and CSR control and, when driven low, forces the Qn and PPO outputs low and forces the QERR output
high. If the DCS control functionality is not desired, then the CSR input can be hard-wired to ground, in which
case the setup-time requirement for DCS is the same as for the other D data inputs. To control the low-power
mode with DCS only, the CSR input must be pulled up to V
through a pullup resistor.
CC
The two V
pins (A3 and T3) are connected together internally by approximately 150 Ω. However, it is
REF
necessary to connect only one of the two V
must be terminated with a V
pins to the external V
power supply. An unused V
pin
REF
REF
REF
coupling capacitor.
REF
2
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SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
ZKE PACKAGE
(TOP VIEW)
terminal assignments for 1:1 register (C0 = 0, C1 = 0)
1
2
3
4
5
6
1
D1 (DCKE)
D2
2
PPO
D15
3
4
5
Q1 (QCKE)
Q2
6
A
B
C
D
E
F
V
V
DNU
Q15
Q16
DNU
Q17
Q18
C0
REF
CC
A
B
C
D
GND
GND
D3
D16
V
V
Q3
CC
GND
CC
GND
D4 (DODT)
D5
QERR
D17
Q4 (QODT)
Q5
V
CC
GND
V
CC
GND
E
F
G
H
J
D6
D18
Q6
G
H
J
PAR_IN
CLK
RESET
D7 (DCS)
CSR
D19
V
V
C1
CC
GND
CC
GND
Q7 (QCS)
NC
DNU
NC
CLK
V
CC
V
CC
K
L
D8
GND
GND
Q8
Q19
Q20
Q21
Q22
Q23
Q24
Q25
D9
D20
V
CC
V
CC
Q9
K
L
M
N
P
R
T
D10
D21
GND
GND
Q10
D11
D22
V
CC
GND
V
CC
GND
Q11
M
N
P
R
T
D12
D23
Q12
D13
D24
V
CC
V
V
Q13
CC
D14
D25
V
REF
Q14
CC
Each pin name in parentheses indicates the DDR2 DIMM signal name.
DNU − Do not use
NC − No internal connection
3
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SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
logic diagram for 1:1 register configuration (positive logic); C0 = 0, C1 = 0
G2
RESET
H1
CLK
J1
CLK
A3, T3
V
REF
A1
D1
H2
J2
D1 (DCKE)
D4 (DODT)
D7 (DCS)
CSR
D
R
A5
D5
H5
Q1 (QCKE)
Q4 (QODT)
Q7 (QCS)
CLK
CLK
CLK
Q
Q
Q
D
R
D
R
LPS0
(internal node)
D
R
CLK
Q
LPS1
(internal node)
One of 22 Channels
B1
D2
CE
CLK
D
R
B5
Q
Q2
To 21 Other Channels (D3, D5, D6, D8−D25)
4
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SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
parity logic diagram for 1:1 register configuration (positive logic); C0 = 0, C1 = 0
G2
RESET
H1
CLK
J1
CLK
LPS0
(internal node)
D2−D3,
22
D5−D6,
D8-D25
D2−D3,
D5−D6,
D8−D25
Q2−Q3,
Q5−Q6,
Q8−Q25
CE
D
R
A3, T3
22
V
REF
CLK
Q
22
D2−D3,
D5−D6,
D8−D25
22
Parity
Generator
G5
C1
1
0
0
A2
PPO
D
Q
1
D
R
Q
D
R
Q
CLK
CLK
CLK
R
CE
G1
G6
PAR_IN
D2
QERR
C0
CLK
0
1
2−Bit
LPS1
(internal node)
Counter
R
D
R
Q
CLK
5
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SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
ZKE PACKAGE
(TOP VIEW)
terminal assignments for 1:2 register-A (C0 = 0, C1 = 1)
1
2
3
4
5
6
1
2
3
4
5
6
Q1A
(QCKEA)
Q1B
(QCKEB)
A
D1 (DCKE)
PPO
V
REF
V
CC
A
B
C
D
B
C
D2
D3
DNU
DNU
GND
GND
Q2A
Q3A
Q2B
Q3B
V
V
CC
GND
CC
GND
Q4A
(QODTA)
Q4B
(QODTB)
D
D4 (DODT)
QERR
E
F
G
H
J
E
F
D5
D6
DNU
DNU
V
V
Q5A
Q6A
C1
Q5B
Q6B
C0
CC
GND
CC
GND
G
PAR_IN
RESET
V
V
CC
GND
CC
GND
Q7A
(QCSA)
Q7B
(QCSB)
H
CLK
D7 (DCS)
J
K
L
CLK
D8
CSR
DNU
DNU
DNU
DNU
DNU
DNU
DNU
V
V
NC
NC
CC
GND
CC
GND
K
L
Q8A
Q8B
D9
V
CC
GND
V
CC
GND
Q9A
Q9B
M
N
P
R
T
M
N
P
R
T
D10
D11
D12
D13
D14
Q10A
Q11A
Q12A
Q13A
Q14A
Q10B
Q11B
Q12B
Q13B
Q14B
V
CC
GND
V
CC
GND
V
CC
V
V
CC
V
REF
CC
Each pin name in parentheses indicates the DDR2 DIMM signal name.
DNU − Do not use
NC − No internal connection
6
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ꢗ ꢎꢄ ꢘ ꢊꢖꢖ ꢓꢕꢀꢀ ꢌꢙꢊꢓ ꢎꢄ ꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
logic diagram for 1:2 register-A configuration (positive logic); C0 = 0, C1 = 1
G2
RESET
H1
CLK
J1
CLK
A3, T3
V
REF
A1
D1
A5
A6
D1 (DCKE)
Q1A (QCKEA)
Q1B (QCKEB)
D
R
CLK
CLK
Q
Q
D5
D6
D4 (DODT)
Q4A (QODTA)
Q4B (QODTB)
D
R
H2
J2
H5
H6
D7 (DCS)
Q7A (QCSA)
Q7B (QCSB)
D
R
CLK
Q
LPS0
(internal node)
CSR
D
LPS1
(internal node)
CLK
Q
R
One of Eleven Channels
CE
B1
D2
B5
B6
Q2A
Q2B
D
R
Q
CLK
To 10 Other Channels (D3, D5, D6, D8−D14)
7
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ꢗꢎ ꢄ ꢘ ꢊ ꢖꢖ ꢓ ꢕꢀꢀ ꢌꢙꢊꢓ ꢎ ꢄꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
parity logic diagram for 1:2 register-A configuration (positive logic); C0 = 0, C1 = 1
G2
RESET
H1
CLK
J1
CLK
LPS0
(internal node)
D2−D3,
Q2A−Q3A,
Q5A−Q6A,
Q8A−Q14A
11
D5−D6,
D8-D14
D2−D3,
D5−D6,
D8−D14
11
11
CE
CLK
D
R
A3, T3
V
REF
Q
11
Q2B−Q3B,
Q5B−Q6B,
Q8B−Q14B
D2−D3,
D5−D6,
D8−D14
11
Parity
Generator
G5
C1
1
0
0
A2
PPO
D
R
Q
1
D
R
Q
D
Q
CLK
CLK
CLK
R
CE
G1
G6
PAR_IN
D2
QERR
C0
CLK
0
1
2−Bit
LPS1
(internal node)
Counter
D
R
R
Q
CLK
8
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ꢗ ꢎꢄ ꢘ ꢊꢖꢖ ꢓꢕꢀꢀ ꢌꢙꢊꢓ ꢎꢄ ꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
ZKE PACKAGE
(TOP VIEW)
terminal assignments for 1:2 register-B (C0 = 1, C1 = 1)
1
2
3
4
5
6
1
D1
2
3
4
5
6
A
B
C
D
E
F
PPO
V
V
Q1A
Q2A
Q3A
Q4A
Q5A
Q6A
C1
Q1B
Q2B
Q3B
Q4B
Q5B
Q6B
C0
REF
CC
A
B
C
D
D2
DNU
DNU
QERR
DNU
DNU
RESET
GND
GND
D3
V
V
CC
GND
CC
GND
D4
D5
V
V
CC
GND
CC
GND
E
F
G
H
J
D6
G
PAR_IN
V
V
CC
GND
CC
GND
Q7A
(QCSA)
Q7B
H
CLK
D7 (DCS)
(QCSB)
J
K
L
CLK
D8
CSR
DNU
DNU
DNU
V
V
NC
Q8A
Q9A
Q10A
NC
Q8B
Q9B
Q10B
CC
GND
CC
GND
K
L
D9
V
CC
GND
V
CC
GND
M
D10
M
N
P
R
T
D11
(DODT)
Q11A
(QODTA)
Q11B
(QODTB)
N
DNU
V
V
CC
CC
P
R
D12
D13
DNU
DNU
GND
GND
Q12A
Q13A
Q12B
Q13B
V
CC
V
V
CC
D14
(DCKE)
Q14A
(QCKEA)
Q14B
(QCKEB)
T
DNU
V
REF
CC
Each pin name in parentheses indicates the DDR2 DIMM signal name.
DNU − Do not use
NC − No internal connection
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ꢗꢎ ꢄ ꢘ ꢊ ꢖꢖ ꢓ ꢕꢀꢀ ꢌꢙꢊꢓ ꢎ ꢄꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
logic diagram for 1:2 register-B configuration (positive logic); C0 = 1, C1 = 1
G2
RESET
H1
CLK
J1
CLK
A3, T3
V
REF
T1
A5
A6
D14 (DCKE)
Q14A (QCKEA)
Q14B (QCKEB)
D
R
CLK
CLK
Q
Q
N1
D5
D6
D11 (DODT)
Q11A (QODTA)
Q11B (QODTB)
D
R
H2
J2
H5
H6
D7 (DCS)
Q7A (QCSA)
Q7B (QCSB)
D
R
CLK
Q
LPS0
(internal node)
CSR
D
R
LPS1
(internal node)
CLK
Q
One of Eleven Channels
A1
D1
A5
A6
CE
CLK
Q1A
Q1B
D
R
Q
To 10 Other Channels (D2−D6, D8−D10, D12−D13)
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SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
parity logic diagram for 1:2 register-B configuration (positive logic); C0 = 1, C1 = 1
G2
RESET
H1
CLK
J1
CLK
LPS0
(internal node)
D1−D6,
D8-D13
11
11
11
Q1A−Q6A,
Q8A−Q13A
D1−D6,
D8−D13
CE
D
R
A3, T3
V
REF
CLK
Q
11
Q1B−Q6B,
Q8B−Q13B
D1−D6,
11
D8−D10,
D12−D13
Parity
Generator
G5
C1
1
0
0
A2
PPO
D
Q
1
D
R
Q
D
Q
CLK
CLK
CLK
R
R
CE
G1
G6
PAR_IN
D2
QERR
C0
CLK
0
1
2−Bit
LPS1
(internal node)
Counter
R
D
R
Q
CLK
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ꢗꢎ ꢄ ꢘ ꢊ ꢖꢖ ꢓ ꢕꢀꢀ ꢌꢙꢊꢓ ꢎ ꢄꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
TERMINAL FUNCTIONS
ELECTRICAL
CHARACTERISTICS
TERMINAL NAME
DESCRIPTION
Ground
Ground input
GND
Power-supply voltage
Input reference voltage
Positive master clock input
1.8 V nominal
0.9 V nominal
Differential input
Differential input
LVCMOS input
V
V
CC
REF
CLK
Negative master clock input
Configuration control input. Register A or Register B and 1:1 mode or 1:2 mode select.
Asynchronous reset input. Resets registers and disables V , data, and clock
differential-input receivers. When RESET is low, all Q outputs are forced low and the QERR
output is forced high.
CLK
C0, C1
REF
LVCMOS input
RESET
Data input. Clocked in on the crossing of the rising edge of CLK and the falling edge of CLK.
SSTL_18 inputs
SSTL_18 inputs
SSTL_18 input
D1−D25
CSR, DCS
DODT
†
Chip select inputs. Disables D1−D25 outputs switching when both inputs are high.
The outputs of this register bit will not be suspended by the DCS and CSR control
The outputs of this register bit will not be suspended by the DCS and CSR control
Parity input. Arrives one clock cycle after the corresponding data input.
Data outputs that are suspended by the DCS and CSR control
SSTL_18 input
DCKE
SSTL_18 input
PAR_IN
‡
1.8 V CMOS outputs
1.8 V CMOS output
1.8 V CMOS output
1.8 V CMOS output
1.8 V CMOS output
Open-drain output
Q1−Q25
†
Partial parity out. Indicates odd parity of inputs D1−D25.
PPO
Data output that will not be suspended by the DCS and CSR control
Data output that will not be suspended by the DCS and CSR control
Data output that will not be suspended by the DCS and CSR control
Output error bit. Timing is determined by the device mode.
No internal connection
QCS
QODT
QCKE
QERR
NC
Do not use. Inputs are in standby-equivalent mode, and outputs are driven low.
DNU
†
‡
Data inputs = D2, D3, D5, D6, D8−D25 when C0 = 0 and C1 = 0
Data inputs = D2, D3, D5, D6, D8−D14 when C0 = 0 and C1 = 1
Data inputs = D1−D6, D8−D10, D12, D13 when C0 = 1 and C1 = 1.
Data outputs = Q2, Q3, Q5, Q6, Q8−Q25 when C0 = 0 and C1 = 0
Data outputs = Q2, Q3, Q5, Q6, Q8−Q14 when C0 = 0 and C1 = 1
Data outputs = Q1−Q6, Q8−Q10, Q12, Q13 when C0 = 1 and C1 = 1.
FUNCTION TABLES
INPUTS
OUTPUTS
RESET
DCS
L
CSR
CLK
CLK
Dn
L
Qn
L
H
H
H
H
H
H
X
X
↑
↑
↓
↓
L
H
H
L
X
L
↑
↓
L
X
L
↑
↓
H
H
H
H
↑
↓
X
Q
Q
0
0
X
X
L or H
L or H
X
X or
X or
X or
X or
X or
L
L
floating floating floating floating floating
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ꢗ ꢎꢄ ꢘ ꢊꢖꢖ ꢓꢕꢀꢀ ꢌꢙꢊꢓ ꢎꢄ ꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
Function Tables (Continued)
INPUTS
OUTPUTS
DCKE,
DCS,
QCKE,
QCS,
RESET
CLK
CLK
DODT
QODT
H
H
H
↑
↑
↓
↓
H
L
H
L
L or H
L or H
X
Q
0
X or
X or
X or
L
L
floating floating floating
PARITY AND STANDBY FUNCTION
INPUTS
OUTPUTS
PPO QERR
Σ OF INPUTS = H
‡
§
RESET
CLK
CLK
DCS
CSR
PAR_IN
†
D1−D25
H
H
H
H
H
H
H
H
H
H
↑
↓
L
L
X
X
Even
Odd
Even
Odd
Even
Odd
Even
Odd
X
L
L
L
H
H
↑
↓
L
↑
↓
L
X
H
H
L
↑
↓
L
X
H
L
H
↑
↑
↓
↓
H
L
L
L
H
L
H
L
L
H
↑
↓
H
L
H
H
L
↑
↓
H
L
H
L
H
↑
↓
H
H
X
X
PPO
PPO
QERR
QERR
0
0
0
0
L or H
L or H
X
X
X
X or
X or
X or
X or
X or
floating
L
X
L
H
floating floating floating floating
†
Data inputs = D2−D3, D5−D6, D8−D25 when C0 = 0 and C1 = 0
Data inputs = D2−D3, D5−D6, D8−D14 when C0 = 0 and C1 = 1
Data inputs = D1−D6, D8−D13 when C0 = 1 and C1 = 1
PAR_IN arrives one clock cycle (C0 = 0) or two clock cycles (C0 = 1) after the data to which it applies.
This transition assumes that QERR is high at the crossing of CLK going high and CLK going low. If QERR
goes low, then it stays latched low for a minimum of two clock cycles or until RESET is driven low. If two
or more consecutive parity errors occur, then the QERR output is driven low and latched low for a clock
duration equal to the parity duration or until RESET is driven low.
‡
§
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SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
¶
PARITY ERROR DETECT IN LOW-POWER MODE
1:1 MODE
(C0 = 0, C1 = 0)
1:2 REGISTER-A MODE
(C0 = 0, C1 = 1)
1:2 REGISTER-B MODE
(C0 = 1, C1 = 1)
CASCADED MODE
(Registers A and B)
INPUT−DATA
ERROR
OCCURANCE
PPO
QERR
PPO
DURATION
QERR
DURATION
PPO
DURATION
QERR
DURATION
PPO
DURATION
QERR
DURATION
#
||
||
||
||
||
||
||
||
DURATION
DURATION
2 Cycles
2 Cycles
2 Cycles
n − 4
n − 3
n − 2
1 Cycle
1 Cycle
1 Cycle
1 Cycle
2 Cycles
2 Cycles
2 Cycles
1 Cycle
1 Cycle
1 Cycle
2 Cycles
2 Cycles
2 Cycles
1 Cycle
1 Cycle
1 Cycle
2 Cycles
2 Cycles
2 Cycles
1 Cycle
1 Cycle
LPM + 2
Cycles
LPM + 2
Cycles
LPM + 1
Cycle
LPM + 1
Cycle
LPM + 2
Cycles
LPM + 2
Cycles
LPM + 2
Cycles
LPM + 2
Cycles
n − 1
n
Not detected Not detected Not detected Not detected Not detected Not detected Not detected Not detected
¶
If a parity error occurs before the device enters the low-power mode (LPM), then the behavior of PPO and QERR is dependent on the mode of
the device and the position of the parity error occurrence. This table illustrates the low-power-mode effect on parity detect. The low-power mode
is activated on the n clock cycle when DCS and CSR go high.
#
||
The clock-edge position of a one cycle data-input error relative to the clock-edge (n) which initiates LPM at the DCS and CSR inputs.
If an error occurs, then the QERR output may be driven low and the PPO output driven high. These columns show the clock duration for which
the PPO signal will be high.
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ꢗ ꢎꢄ ꢘ ꢊꢖꢖ ꢓꢕꢀꢀ ꢌꢙꢊꢓ ꢎꢄ ꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.5 V
CC
Input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.5 V
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through each V
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, q (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36°C/W
JA
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 2.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
MIN
1.7
NOM
MAX
1.9
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
Supply voltage
CC
REF
TT
I
Reference voltage
0.49 × V
0.5 × V
0.51 × V
CC
V
CC
CC
Termination voltage
V
−40 mV
REF
V
REF
V
+ 40 mV
V
REF
Input voltage
0
V
CC
V
AC high-level input voltage
AC low-level input voltage
DC high-level input voltage
DC low-level input voltage
High-level input voltage
Low-level input voltage
Data inputs, CSR, PAR_IN
Data inputs, CSR, PAR_IN
Data inputs, CSR, PAR_IN
Data inputs, CSR, PAR_IN
V
V
+ 250 mV
+ 125 mV
V
IH
REF
REF
V
V
−250 mV
REF
V
IL
V
IH
−125 mV
REF
V
IL
RESET, C
RESET, C
0.65 × V
CC
V
IH
n
0.35 × V
CC
V
IL
n
Common-mode input voltage range CLK, CLK
0.675
600
1.125
V
ICR
I(PP)
Peak-to-peak input voltage
High-level output current
CLK, CLK
mV
mA
I
Q outputs, PPO
Q outputs, PPO
QERR output
−8
8
OH
I
Low-level output current
mA
OL
8
T
Operating free-air temperature
0
70
_C
A
NOTE 4: The RESET and Cn inputs of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The
differential inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS
Inputs, literature number SCBA004.
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SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
V
MIN TYP
−0.2
MAX
UNIT
CC
I
I
I
I
I
= −100 µA
= −6 mA
= 100 µA
= 6 mA
1.7 V to 1.9 V
1.7 V
V
OH
OH
OL
OL
OL
CC
1.3
V
OH
V
OL
V
Q outputs, PPO
1.7 V to 1.9 V
1.7 V
0.2
0.4
0.35
5
Q outputs, PPO
QERR output
V
= 8 mA
1.7 V
‡
I
I
All inputs
V = V
CC
or GND
or GND
1.9 V
µA
µA
µA
mA
I
I
QERR output
Static standby
Static operating
V
= V
O CC
1.9 V
10
OZ
RESET = GND
RESET = V , V = V
100
50
I
I
I
= 0
= 0
1.9 V
1.8 V
CC
O
or V
or V
CC
I
IH(AC)
IH(AC)
IL(AC)
Dynamic operating − RESET = V , V = V
clock only
,
,
µA/
MHz
CC
I
IL(AC)
43
25
CLK and CLK switching 50% duty cycle
Dynamic operating −
per each data input,
1:1 configuration
µA/
clock
RESET = V , V = V
CC IH(AC)
or V
IL(AC)
I
I
CCD
O
CLK and CLK switching 50% duty cycle,
MHz/
D input
one data input switching at one-half clock
frequency, 50% duty cycle
Dynamic operating −
per each data input,
1:2 configuration
49
46
Chip-select-enabled
low-power active
mode − clock only
RESET = V , V = V
CC IH(AC)
or V
,
µA/
MHz
I
IL(AC)
CLK and CLK switching 50% duty cycle
Chip-select-enabled
low-power active
mode −
2
2
I
I
O
= 0
1.8 V
CCDLP
µA/
clock
MHz/
D input
RESET = V , V = V
CC IH(AC)
or V
IL(AC)
,
I
1:1 configuration
CLK and CLK switching 50% duty cycle,
one data input switching at one-half clock
frequency, 50% duty cycle
Chip-select-enabled
low-power active
mode −
1:2 configuration
Data inputs, CSR,
PAR_IN
V = V
REF
250 mV
2.5
2
3
3.5
3
I
C
pF
1.8 V
i
CLK, CLK
RESET
V
= 0.9 V, V = 600 mV
I(PP)
ICR
V = V
or GND
2.5
I
CC
†
‡
All typical values are at V
CC
= 1.8 V, T = 25°C.
A
Each V
pin (A3 or T3) must be tested independently, with the other (untested) pin open. Since the two V pins are connected internally,
REF
REF
the total maximum current on the V
REF
pin is doubled ( 10 µA).
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢀ ꢀꢄ ꢅꢆ ꢇꢈ ꢉꢉ ꢊ
ꢇ ꢋ ꢌꢍꢎ ꢄ ꢏꢐ ꢁꢑ ꢎꢒ ꢅꢓ ꢊꢍꢔ ꢕ ꢓꢕ ꢒꢎ ꢀꢄ ꢕꢓꢕꢖ ꢍ ꢅꢑ ꢑꢕ ꢓ
ꢗ ꢎꢄ ꢘ ꢊꢖꢖ ꢓꢕꢀꢀ ꢌꢙꢊꢓ ꢎꢄ ꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1 and Note 5)
V = 1.8 V
CC
0.1 V
UNIT
MIN MAX
UNIT
MHz
ns
f
t
t
t
Clock frequency
500
clock
Pulse duration, CLK, CLK high or low
Differential inputs active time (see Note 6)
Differential inputs inactive time (see Note 7)
1
w
10
15
ns
act
ns
inact
0.6
0.5
0.5
0.5
0.5
0.5
DCS before CLK↑, CLK↓, CSR high; CSR before CLK↑, CLK↓, DCS high
DCS before CLK↑, CLK↓, CSR low
DODT, DCKE, and Data before CLK↑, CLK↓
PAR_IN before CLK↑, CLK↓
t
Setup time
Hold time
ns
ns
su
DCS, DODT, DCKE, and Data after CLK↑, CLK↓
PAR_IN after CLK↑, CLK↓
t
h
NOTES: 5. All inputs slew rate is 1 V/ns 20%.
6.
7.
V
V
low.
must be held at a valid input level, and data inputs must be held low for a minimum time of t
, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of t
REF inact
max, after RESET is taken high.
max, after RESET is taken
REF
act
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)
V
= 1.8 V
CC
0.1 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
f
t
(see Figure 1)
500
MHz
ns
max
†
Q
1.41
2.15
(see Figure 1)
CLK and CLK
CLK and CLK
pdm
see Figure 4
see Figure 3
PPO
0.4
0.7
0.7
1.7
2.5
2.1
2.35
3
ns
t
t
t
t
t
t
t
pd
PLH
PHL
pdmss
ns
ns
ns
ns
CLK and CLK
CLK and CLK
RESET
QERR
†
(see Figure 1)
Q
Q
†
(see Figure 1)
RPHL
RPHL
RPLH
PPO
QERR
3
(see Figure 4)
(see Figure 3)
3
RESET
†
Includes 350-ps test-load transmission-line delay.
output slew rates over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 2)
V = 1.8 V
CC
0.1 V
PARAMETER
FROM
TO
UNIT
MIN
MAX
dV/dt_r
dV/dt_f
20%
80%
80%
20%
1
1
4
4
V/ns
V/ns
V/ns
‡
dV/dt_∆
80% or 20%
1
20% or 80%
‡
Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢀꢀ ꢄ ꢅ ꢆꢇꢈ ꢉ ꢉꢊ
ꢇꢋ ꢌꢍꢎ ꢄ ꢏ ꢐꢁ ꢑ ꢎꢒꢅ ꢓꢊꢍ ꢔꢕ ꢓꢕ ꢒ ꢎꢀ ꢄꢕ ꢓꢕ ꢖ ꢍꢅꢑ ꢑ ꢕꢓ
ꢗꢎ ꢄ ꢘ ꢊ ꢖꢖ ꢓ ꢕꢀꢀ ꢌꢙꢊꢓ ꢎ ꢄꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
PARAMETER MEASUREMENT INFORMATION
V
CC
Z
= 50 Ω,
= 350 ps
O
Test
DUT
t
D
Point
CLK
R
= 1 kΩ
L
Output
Test Point
Out
Clock Inputs
R
= 100 Ω
L
C
= 30 pF
L
Z
t
= 50 Ω,
= 350 ps
O
D
CLK
R = 1 kΩ
L
(see Note A)
Test
Point
Z
= 50 Ω,
= 350 ps
O
t
D
LOAD CIRCUIT
t
w
V
V
IH
V
REF
V
V
Input
REF
V
IL
LVCMOS
RESET
Input
CC
V
/2
V
/2
CC
CC
VOLTAGE WAVEFORMS
PULSE DURATION
0 V
V
I(PP)
t
t
act
inact
Timing
Inputs
V
ICR
ICR
I
I
(operating)
I
CC
CC
90%
(see
Note B)
10%
(standby)
CC
t
t
PLH
PHL
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
V
OH
Output
V
CC
/2
V
CC
/2
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
V
I(PP)
V
V
IH
Timing
Inputs
LVCMOS
RESET
Input
V
ICR
V
CC
/2
IL
t
PHL
/2
t
t
h
su
V
V
V
OH
IH
V
Input
V
REF
Output
V
REF
CC
V
OL
IL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
NOTES: A.
B.
C
includes probe and jig capacitance.
tested with clock and data inputs held at V
L
I
or GND, and I = 0 mA.
CC
CC O
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω,
O
input slew rate = 1 V/ns 20% (unless otherwise noted).
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
H.
I.
V
V
V
V
= V = V /2
REF TT
IH
IL
CC
+ 250 mV (ac voltage levels) for differential inputs. V = V for LVCMOS input.
CC
= V
REF
IH
= V
− 250 mV (ac voltage levels) for differential inputs. V = GND for LVCMOS input.
REF
= 600 mV
IL
I(PP)
t
and t
PHL
are the same as t .
pd
PLH
Figure 1. Data Output Load Circuit and Voltage Waveforms
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢀ ꢀꢄ ꢅꢆ ꢇꢈ ꢉꢉ ꢊ
ꢇ ꢋ ꢌꢍꢎ ꢄ ꢏꢐ ꢁꢑ ꢎꢒ ꢅꢓ ꢊꢍꢔ ꢕ ꢓꢕ ꢒꢎ ꢀꢄ ꢕꢓꢕꢖ ꢍ ꢅꢑ ꢑꢕ ꢓ
ꢗ ꢎꢄ ꢘ ꢊꢖꢖ ꢓꢕꢀꢀ ꢌꢙꢊꢓ ꢎꢄ ꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
PARAMETER MEASUREMENT INFORMATION
V
CC
DUT
R
= 50 Ω
L
V
V
Output
OH
Out
Test Point
80%
C
= 10 pF
L
20%
(see Note A)
OL
dV_f
dt_f
VOLTAGE WAVEFORMS
LOAD CIRCUIT
HIGH-TO-LOW SLEW-RATE MEASUREMENT
HIGH-TO-LOW SLEW-RATE MEASUREMENT
DUT
Out
dt_r
dV_r
Test Point
= 50 Ω
V
OH
80%
C
= 10pF
L
R
L
(see Note A)
20%
V
OL
Output
LOAD CIRCUIT
LOW-TO-HIGH SLEW-RATE MEASUREMENT
VOLTAGE WAVEFORMS
LOW-TO-HIGH SLEW-RATE MEASUREMENT
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω,
O
input slew rate = 1 V/ns 20% (unless otherwise specified).
Figure 2. Data Output Slew-Rate Measurement Information
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢀꢀ ꢄ ꢅ ꢆꢇꢈ ꢉ ꢉꢊ
ꢇꢋ ꢌꢍꢎ ꢄ ꢏ ꢐꢁ ꢑ ꢎꢒꢅ ꢓꢊꢍ ꢔꢕ ꢓꢕ ꢒ ꢎꢀ ꢄꢕ ꢓꢕ ꢖ ꢍꢅꢑ ꢑ ꢕꢓ
ꢗꢎ ꢄ ꢘ ꢊ ꢖꢖ ꢓ ꢕꢀꢀ ꢌꢙꢊꢓ ꢎ ꢄꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
PARAMETER MEASUREMENT INFORMATION
V
CC
V
I(PP)
Timing
Inputs
DUT
V
ICR
V
ICR
R
= 1 kΩ
L
t
PHL
Out
Test Point
V
V
CC
Output
Waveform 1
C
= 10 pF
V
CC
/2
L
(see Note A)
OL
VOLTAGE WAVEFORMS
OPEN-DRAIN OUTPUT TRANSITION TIME
(HIGH-TO-LOW)
LOAD CIRCUIT
V
I(PP)
LVCMOS
RESET
Input
V
CC
Timing
Inputs
V
CC
/2
V
ICR
V
ICR
0 V
t
PLH
t
PHL
V
OH
V
OH
Output
Waveform 2
Output
Waveform 2
0.15 V
0.15 V
0 V
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
OPEN-DRAIN OUTPUT TRANSITION TIME
(LOW-TO-HIGH)
OPEN-DRAIN OUTPUT TRANSITION TIME
(LOW-TO-HIGH)
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω,
O
input slew rate = 1 V/ns 20% (unless otherwise noted).
C.
t
and t
PHL
are the same as t .
pd
PLH
Figure 3. Error Output Load Circuit and Voltage Waveforms
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢀ ꢀꢄ ꢅꢆ ꢇꢈ ꢉꢉ ꢊ
ꢇ ꢋ ꢌꢍꢎ ꢄ ꢏꢐ ꢁꢑ ꢎꢒ ꢅꢓ ꢊꢍꢔ ꢕ ꢓꢕ ꢒꢎ ꢀꢄ ꢕꢓꢕꢖ ꢍ ꢅꢑ ꢑꢕ ꢓ
ꢗ ꢎꢄ ꢘ ꢊꢖꢖ ꢓꢕꢀꢀ ꢌꢙꢊꢓ ꢎꢄ ꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
PARAMETER MEASUREMENT INFORMATION
DUT
Out
Test Point
= 1 kΩ
C
= 5 pF
L
R
L
(see Note A)
LOAD CIRCUIT
V
I(PP)
V
V
IH
LVCMOS
RESET
Input
Timing
Inputs
V
ICR
V
ICR
V
CC
/2
IL
t
t
PHL
t
PLH
PHL
V
OH
OL
V
V
OH
Output
V
TT
V
TT
Output
V
TT
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω,
O
input slew rate = 1 V/ns 20% (unless otherwise noted).
C.
D.
E.
F.
V
V
V
V
= V = V /2
REF TT
IH
IL
CC
+ 250 mV (ac voltage levels) for differential inputs. V = V for LVCMOS input.
CC
= V
REF
IH
= V
− 250 mV (ac voltage levels) for differential inputs. V = GND for LVCMOS input.
REF
= 600 mV
IL
I(PP)
G.
t
and t
are the same as t .
pd
PLH
PHL
Figure 4. Partial-Parity-Out Load Circuit and Voltage Waveforms
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢀꢀ ꢄ ꢅ ꢆꢇꢈ ꢉ ꢉꢊ
ꢇꢋ ꢌꢍꢎ ꢄ ꢏ ꢐꢁ ꢑ ꢎꢒꢅ ꢓꢊꢍ ꢔꢕ ꢓꢕ ꢒ ꢎꢀ ꢄꢕ ꢓꢕ ꢖ ꢍꢅꢑ ꢑ ꢕꢓ
ꢗꢎ ꢄ ꢘ ꢊ ꢖꢖ ꢓ ꢕꢀꢀ ꢌꢙꢊꢓ ꢎ ꢄꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
APPLICATION INFORMATION
SN74SSTU32866A used as a single device in the 1:1 register configuration; C0 = 0, C1 = 0
Register 1 of 1
Qn
1D
C1
Dn
22
22
22
22
QERR
PPO
1D
C1
1D
C1
1D
C1
Latching
and
Reset
†
Function
C0 = 0
PAR_IN
Clock
C1 = 0
†
This function holds the error for two cycles. For details, see the parity logic diagram.
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢀ ꢀꢄ ꢅꢆ ꢇꢈ ꢉꢉ ꢊ
ꢇ ꢋ ꢌꢍꢎ ꢄ ꢏꢐ ꢁꢑ ꢎꢒ ꢅꢓ ꢊꢍꢔ ꢕ ꢓꢕ ꢒꢎ ꢀꢄ ꢕꢓꢕꢖ ꢍ ꢅꢑ ꢑꢕ ꢓ
ꢗ ꢎꢄ ꢘ ꢊꢖꢖ ꢓꢕꢀꢀ ꢌꢙꢊꢓ ꢎꢄ ꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
timing diagram for SN74SSTU32866A used as a single device; C0 = 0, C1 = 0
(RESET switches from L to H)
RESET
DCS
CSR
n
n + 1
n + 2
n + 3
n + 4
CLK
CLK
t
t
t
h
su
act
†
D1−D25
t
, t
pdm pdmss
CLK to Q
Q1−Q25
t
t
su
h
†
PAR_IN
t
pd
CLK to PPO
PPO
t
t
, t
PHL PLH
PHL
CLK to QERR
CLK to QERR
‡
Data to QERR Latency
QERR
H, L, or X
H or L
†
‡
After RESET is switched from low to high, all data and PAR_IN input signals must be set and held low for a minimum time of t
to avoid false error.
If the data is clocked in on the n clock pulse, then the QERR output signal will be generated on the n + 2 clock pulse, and it will be valid
on the n + 3 clock pulse.
max,
act
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢀꢀ ꢄ ꢅ ꢆꢇꢈ ꢉ ꢉꢊ
ꢇꢋ ꢌꢍꢎ ꢄ ꢏ ꢐꢁ ꢑ ꢎꢒꢅ ꢓꢊꢍ ꢔꢕ ꢓꢕ ꢒ ꢎꢀ ꢄꢕ ꢓꢕ ꢖ ꢍꢅꢑ ꢑ ꢕꢓ
ꢗꢎ ꢄ ꢘ ꢊ ꢖꢖ ꢓ ꢕꢀꢀ ꢌꢙꢊꢓ ꢎ ꢄꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
timing diagram for SN74SSTU32866A used as a single device; C0 = 0, C1 = 0
(RESET = H)
RESET
DCS
CSR
n
n + 1
n + 2
n + 3
n + 4
CLK
CLK
t
t
su
h
D1−D25
Q1−Q25
t
, t
pdm pdmss
CLK to Q
t
t
su
h
PAR_IN
PPO
t
pd
CLK to PPO
t
or t
PLH
PHL
CLK to QERR
Data to PPO Latency
†
QERR
Data to QERR Latency
Output signal is dependent on
the prior unknown input event
Unknown input
event
H or L
†
If the data is clocked in on the n clock pulse, then the QERR output signal will be generated on the n + 2 clock pulse, and it will be valid on n
+ 3 clock pulse. If an error occurs and the QERR output is driven low, then it stays latched low for a minimum of two clock cycles or until RESET
is driven low.
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢀ ꢀꢄ ꢅꢆ ꢇꢈ ꢉꢉ ꢊ
ꢇ ꢋ ꢌꢍꢎ ꢄ ꢏꢐ ꢁꢑ ꢎꢒ ꢅꢓ ꢊꢍꢔ ꢕ ꢓꢕ ꢒꢎ ꢀꢄ ꢕꢓꢕꢖ ꢍ ꢅꢑ ꢑꢕ ꢓ
ꢗ ꢎꢄ ꢘ ꢊꢖꢖ ꢓꢕꢀꢀ ꢌꢙꢊꢓ ꢎꢄ ꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
timing diagram for SN74SSTU32866A used as a single device; C0 = 0, C1 = 0
(RESET switches from H to L)
RESET
t
inact
†
†
DCS
CSR
†
†
CLK
CLK
†
D1−D25
t
RPHL
RESET to Q
Q1−Q25
†
PAR_IN
t
RPHL
RESET to PPO
PPO
QERR
t
RPLH
RESET to QERR
H, L, or X
H or L
†
After RESET is switched from high to low, all data and clock input signals must be held at valid logic levels (not floating) for a minimum
time of t max.
inact
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢀꢀ ꢄ ꢅ ꢆꢇꢈ ꢉ ꢉꢊ
ꢇꢋ ꢌꢍꢎ ꢄ ꢏ ꢐꢁ ꢑ ꢎꢒꢅ ꢓꢊꢍ ꢔꢕ ꢓꢕ ꢒ ꢎꢀ ꢄꢕ ꢓꢕ ꢖ ꢍꢅꢑ ꢑ ꢕꢓ
ꢗꢎ ꢄ ꢘ ꢊ ꢖꢖ ꢓ ꢕꢀꢀ ꢌꢙꢊꢓ ꢎ ꢄꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
SN74SSTU32866A used in pair in the 1:2 register configuration
Register 1 of 2 (1:2 Register-A Configuration); C0 = 0, C1 = 1
QnA
QnB
Dn
1D
C1
22
11
11
11
11
11
QERR
PPO
1D
C1
1D
C1
1D
C1
Latching
and
Reset
C0 = 0
†
Function
PAR_IN
Clock
C1 = 0
Register 2 of 2 (1:2 Register-B Configuration); C0 = 1, C1 = 1
QnA
QnB
1D
C1
11
11
11
11
11
QERR
PPO
1D
C1
1D
C1
1D
C1
Latching
and
Reset
C0 = 1
†
Function
PAR_IN
Clock
C1 = 0
†
This function holds the error for two cycles. For details, see the parity logic diagram.
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢀ ꢀꢄ ꢅꢆ ꢇꢈ ꢉꢉ ꢊ
ꢇ ꢋ ꢌꢍꢎ ꢄ ꢏꢐ ꢁꢑ ꢎꢒ ꢅꢓ ꢊꢍꢔ ꢕ ꢓꢕ ꢒꢎ ꢀꢄ ꢕꢓꢕꢖ ꢍ ꢅꢑ ꢑꢕ ꢓ
ꢗ ꢎꢄ ꢘ ꢊꢖꢖ ꢓꢕꢀꢀ ꢌꢙꢊꢓ ꢎꢄ ꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
timing diagram for the first SN74SSTU32866A (1:2 Register-A configuration) device used in pair;
C0 = 0, C1 = 1 (RESET switches from L to H)
RESET
DCS
CSR
n
n + 1
n + 2
n + 3
n + 4
CLK
CLK
t
t
t
h
su
act
†
D1−D14
t
, t
pdm pdmss
CLK to Q
Q1−Q14
t
t
su
h
†
PAR_IN
t
pd
CLK to PPO
PPO
t
t
, t
PHL PLH
PHL
CLK to QERR
CLK to QERR
‡
QERR
(not used)
Data to QERR
Latency
H, L, or X
H or L
†
‡
After RESET is switched from low to high, all data and PAR_IN input signals must be set and held low for a minimum time of t
to avoid false error.
If the data is clocked in on the n clock pulse, then the QERR output signal will be generated on the n + 1 clock pulse, and it will be valid
on the n + 2 clock pulse.
max,
act
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢀꢀ ꢄ ꢅ ꢆꢇꢈ ꢉ ꢉꢊ
ꢇꢋ ꢌꢍꢎ ꢄ ꢏ ꢐꢁ ꢑ ꢎꢒꢅ ꢓꢊꢍ ꢔꢕ ꢓꢕ ꢒ ꢎꢀ ꢄꢕ ꢓꢕ ꢖ ꢍꢅꢑ ꢑ ꢕꢓ
ꢗꢎ ꢄ ꢘ ꢊ ꢖꢖ ꢓ ꢕꢀꢀ ꢌꢙꢊꢓ ꢎ ꢄꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
timing diagram for the first SN74SSTU32866A (1:2 Register-A configuration) device used in pair;
C0 = 0, C1 = 1 (RESET = H)
RESET
DCS
CSR
n
n + 1
n + 2
n + 3
n + 4
CLK
CLK
t
t
su
h
D1−D14
t
, t
pdm pdmss
CLK to Q
Q1−Q14
PAR_IN
t
t
su
h
t
pd
CLK to PPO
PPO
t
or t
PLH
PHL
CLK to QERR
Data to PPO
Latency
†
QERR
(not used)
Data to QERR
Latency
Output signal is dependent on
the prior unknown input event
Unknown input
event
H or L
†
If the data is clocked in on the n clock pulse, then the QERR output signal will be generated on the n + 1 clock pulse, and it will be valid on n
+ 2 clock pulse. If an error occurs and the QERR output is driven low, then it stays latched low for a minimum of two clock cycles or until RESET
is driven low.
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢀ ꢀꢄ ꢅꢆ ꢇꢈ ꢉꢉ ꢊ
ꢇ ꢋ ꢌꢍꢎ ꢄ ꢏꢐ ꢁꢑ ꢎꢒ ꢅꢓ ꢊꢍꢔ ꢕ ꢓꢕ ꢒꢎ ꢀꢄ ꢕꢓꢕꢖ ꢍ ꢅꢑ ꢑꢕ ꢓ
ꢗ ꢎꢄ ꢘ ꢊꢖꢖ ꢓꢕꢀꢀ ꢌꢙꢊꢓ ꢎꢄ ꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
timing diagram for the first SN74SSTU32866A (1:2 Register-A configuration) device used in pair;
C0 = 0, C1 = 1 (RESET switches from H to L)
RESET
t
inact
†
†
DCS
CSR
†
†
CLK
CLK
†
D1−D14
Q1−Q14
t
RPHL
RESET to Q
†
PAR_IN
t
RPHL
RESET to PPO
PPO
QERR
(not used)
t
RPLH
RESET to QERR
H, L, or X
H or L
†
After RESET is switched from high to low, all data and clock input signals must be held at valid logic levels (not floating) for a minimum
time of t max.
inact
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢀꢀ ꢄ ꢅ ꢆꢇꢈ ꢉ ꢉꢊ
ꢇꢋ ꢌꢍꢎ ꢄ ꢏ ꢐꢁ ꢑ ꢎꢒꢅ ꢓꢊꢍ ꢔꢕ ꢓꢕ ꢒ ꢎꢀ ꢄꢕ ꢓꢕ ꢖ ꢍꢅꢑ ꢑ ꢕꢓ
ꢗꢎ ꢄ ꢘ ꢊ ꢖꢖ ꢓ ꢕꢀꢀ ꢌꢙꢊꢓ ꢎ ꢄꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
timing diagram for the second SN74SSTU32866A (1:2 Register-B configuration) device used in
pair; C0 = 1, C1 = 1 (RESET switches from L to H)
RESET
DCS
CSR
n
n + 1
n + 2
n + 3
n + 4
CLK
CLK
t
t
t
h
su
act
†
D1−D14
t
, t
pdm pdmss
CLK to Q
Q1−Q14
t
t
su
h
†‡
PAR_IN
t
pd
CLK to PPO
PPO
(not used)
t
t
, t
PHL PLH
PHL
CLK to QERR
CLK to QERR
§
QERR
Data to QERR Latency
H, L, or X
H or L
†
After RESET is switched from low to high, all data and PAR_IN input signals must be set and held low for a minimum time of t
to avoid false error.
PAR_IN is driven from PPO of the first SN74SSTU32866A device.
If the data is clocked in on the n clock pulse, then the QERR output signal will be generated on the n + 2 clock pulse, and it will be valid
on the n + 3 clock pulse.
max,
act
‡
§
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢀ ꢀꢄ ꢅꢆ ꢇꢈ ꢉꢉ ꢊ
ꢇ ꢋ ꢌꢍꢎ ꢄ ꢏꢐ ꢁꢑ ꢎꢒ ꢅꢓ ꢊꢍꢔ ꢕ ꢓꢕ ꢒꢎ ꢀꢄ ꢕꢓꢕꢖ ꢍ ꢅꢑ ꢑꢕ ꢓ
ꢗ ꢎꢄ ꢘ ꢊꢖꢖ ꢓꢕꢀꢀ ꢌꢙꢊꢓ ꢎꢄ ꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
timing diagram for the second SN74SSTU32866A (1:2 Register-B configuration) device used in
pair; C0 = 1, C1 = 1 (RESET = H)
RESET
DCS
CSR
n
n + 1
n + 2
n + 3
n + 4
CLK
CLK
t
t
su
h
D1−D14
Q1−Q14
t
, t
pdm pdmss
CLK to Q
t
t
su
h
†
PAR_IN
t
pd
CLK to PPO
PPO
(not used)
t
or t
PLH
PHL
CLK to QERR
Data to PPO Latency
‡
QERR
Data to QERR Latency
Unknown input
event
Output signal is dependent on
the prior unknown input event
H or L
†
‡
PAR_IN is driven from PPO of the first SN74SSTU32866A device.
If the data is clocked in on the n clock pulse, then the QERR output signal will be generated on the n + 2 clock pulse, and it will be valid on n
+ 3 clock pulse. If an error occurs and the QERR output is driven low, then it stays latched low for a minimum of two clock cycles or until RESET
is driven low.
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢀꢀ ꢄ ꢅ ꢆꢇꢈ ꢉ ꢉꢊ
ꢇꢋ ꢌꢍꢎ ꢄ ꢏ ꢐꢁ ꢑ ꢎꢒꢅ ꢓꢊꢍ ꢔꢕ ꢓꢕ ꢒ ꢎꢀ ꢄꢕ ꢓꢕ ꢖ ꢍꢅꢑ ꢑ ꢕꢓ
ꢗꢎ ꢄ ꢘ ꢊ ꢖꢖ ꢓ ꢕꢀꢀ ꢌꢙꢊꢓ ꢎ ꢄꢚ ꢄꢕ ꢀ ꢄ
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
timing diagram for the second SN74SSTU32866A (1:2 Register-B configuration) device used in
pair; C0 = 1, C1 = 1 (RESET switches from H to L)
RESET
t
inact
†
DCS
†
†
CSR
CLK
†
CLK
†
D1−D14
t
RPHL
RESET to Q
Q1−Q14
†
PAR_IN
t
RPHL
RESET to PPO
PPO
(not used)
QERR
t
RPLH
RESET to QERR
H, L, or X
H or L
†
After RESET is switched from high to low, all data and clock input signals must be held at valid logic levels (not floating) for a minimum
time of t max.
inact
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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