SN75107BNSRE4 [TI]
DUAL LINE RECEIVERS; 双线路接收器
| 型号： | SN75107BNSRE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL LINE RECEIVERS |
| 文件： | 总30页 (文件大小：869K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
SN55107A . . . J OR W PACKAGE
SN75107A, SN75107B, SN75108A . . . D OR N PACKAGE
(TOP VIEW)
High Speed
Standard Supply Voltage
Dual Channels
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
NC
1Y
1G
S
V
V
CC+
CC–
High Common-Mode Rejection Ratio
High Input Impedance
High Input Sensitivity
2A
2B
NC
2Y
2G
Differential Common-Mode Input Voltage
Range of ±3 V
8
GND
Strobe Inputs for Receiver Selection
Gate Inputs for Logic Versatility
TTL Drive Capability
SN55107A . . . FK PACKAGE
(TOP VIEW)
High dc Noise Margin
Totem-Pole Outputs
B Version Has Diode-Protected Input for
Power-Off Condition
3
2
1
20 19
18
description
NC
NC
1Y
2A
4
5
6
7
8
NC
2B
17
16
15
14
These circuits are TTL-compatible, high-speed
line receivers. Each is a monolithic dual circuit
featuring two independent channels. They are
designed for general use, as well as for such
specific applications as data comparators and
balanced, unbalanced, and party-line transmis-
sion systems. These devices are unilaterally
interchangeable with and are replacements for
the SN55107, SN75107, and SN75108, but offer
diode-clamped strobe inputs to simplify circuit
design.
NC
1G
NC
NC
9 10 11 12 13
NC – No internal connection
The essential difference between the A and B versions can be seen in the schematics. Input-protection diodes
are in series with the collectors of the differential-input transistors of the B versions. These diodes are useful
incertainparty-linesystemsthathavemultipleV
powersuppliesandcanbeoperatedwithsomeoftheV
CC+
CC+
supplies turned off. In such a system, if a supply is turned off and allowed to go to ground, the equivalent input
circuit connected to that supply would be as follows:
Input
Input
A Version
B Version
This would be a problem in specific systems that might have the transmission lines biased to some potential
greater than 1.4 V.
The SN55107A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN75107A, SN75107B, and SN75108A are characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
FUNCTION TABLE
STROBES
DIFFERENTIAL INPUTS
A – B
OUTPUT
Y
G
X
X
L
S
X
L
V
ID
≥ 25 mV
H
H
–25 mV < V < 25 mV
ID
X
H
L
H
H
X
L
Indeterminate
H
H
L
V
ID
≤ –25 mV
X
H
H
H = high level, L = low level, X = irrelevant
†
logic symbol
SN55107A, SN75107A, and SN75107B
SN75108A
6
6
S
EN
S
EN
1
1
4
2
1A
1B
1G
2A
2B
2G
4
9
1A
1B
1G
2A
2B
2G
2
1Y
2Y
1Y
2Y
5
5
12
11
8
12
11
8
9
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
logic diagram (positive logic)
6
S
1
1A
2
4
9
1B
5
1Y
2Y
1G
8
2G
12
2A
11
2B
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
schematic (each receiver)
See
Note 2
14
V
CC +
400 Ω
4 kΩ
1.6 kΩ
1 kΩ
120 Ω
1 kΩ
See
Note 2
4.8 kΩ
800 Ω
4, 9
7
Output Y
GND
1, 12
2, 11
A
Inputs
B
†
760 Ω
R
5, 8
Strobe G
4.25 kΩ
3 kΩ
3 kΩ
Common
to Both
Receivers
13
6
V
CC –
Strobe S
To Other Receiver
Pin numbers shown are for D, J, N, and W packages.
†
R = 1 kΩ for ’107A and SN75107B, 750 Ω for SN75108A.
NOTES: 1. Resistor values shown are nominal.
2. Components shown with dashed lines in the output circuitry are applicable to the ’107A and SN75107B only. Diodes in series with
the collectors of the differential input transistors are short circuited on ’107A and SN75108A.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
Supply voltage, V
(see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V
CC+
CC–
Differential input voltage, V (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6 V
Common-mode input voltage, V (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 V
ID
IC
Strobe input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range, T
Case temperature for 60 seconds, T : FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
c
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or W package . . . . . . . . . . . . . 260°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
†
NOTES: 3. All voltage values, except differential voltages, are with respect to network ground terminal.
4. Differential voltage values are at the noninverting (A) terminal with respect to the inverting (B) terminal.
5. Common-mode input voltage is the average of the voltages at the A and B inputs.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 125°C
A
POWER RATING
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
A
D
FK
J
950 mW
7.6 mW/°C
11.0 mW/°C
11.0 mW/°C
9.2 mW/°C
8.0 mW/°C
608 mW
—
1375 mW
880 mW
275 mW
275 mW
—
1375 mW
880 mW
N
1150 mW
736 mW
W
1000 mW
640 mW
200 mW
recommended operating conditions (see Note 6)
SN75107A, SN75107B,
SN75108A
SN55107A
UNIT
MIN NOM
MAX
5.5
–5.5 –4.75
MIN NOM
MAX
5.25
–5.25
5
Supply voltage, V
Supply voltage, V
4.5
–4.5
5
4.75
5
V
V
CC+
CC–
–5
–5
High-level input voltage between differential inputs, V
(see Note 7)
(see Note 7)
0.025
5
–0.025
3
0.025
V
IDH
‡
‡
‡
‡
‡
‡
Low-level input voltage between differential inputs, V
IDL
–5
–3
–5
–5
–3
–5
–0.025
3
V
Common-mode input voltage, V (see Notes 7 and 8)
IC
V
Input voltage, any differential input to GND (see Note 8)
3
3
V
High-level input voltage at strobe inputs, V
2
0
5.5
2
0
5.5
V
IH(S)
Low-level input voltage at strobe inputs, V
Low-level output current, I
0.8
0.8
V
IL(S)
–16
125
–16
70
mA
°C
OL
Operating free-air temperature, T
–55
0
A
‡
The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for input voltage
levels only.
NOTES: 6. When using only one channel of the line receiver, the strobe input (G) of the unused channel should be grounded and at least one
of the differential inputs of the unused receiver should be terminated at some voltage between –3 V and 3 V.
7. The recommended combinations of input voltages fall within the shaded area in Figure 1.
8. The common-mode voltage may be as low as –4 V provided that the more positive of the two inputs is not more negative than
–3 V.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
RECOMMENDED COMBINATIONS
OF INPUT VOLTAGES
3
2
1
0
– 1
– 2
– 3
– 4
– 5
– 5 – 4 – 3
– 2
– 1
0
1
2
3
Input B to GND Voltage – V
NOTE A: Recommended input-voltage combinations are in the shaded area.
Figure 1. Recommended Combinations of Input Voltages
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
electrical characteristics over recommended free-air temperature range (unless otherwise noted)
’107A, SN75107B
SN75108A
†
PARAMETER
UNIT
TEST CONDITIONS
‡
TYP
‡
TYP
MIN
MAX
MIN
MAX
V
V
V
= MIN,
V
= 0.8 V,
IL(S)
CC±
= 25 mV,
V
V
High-level output voltage
2.4
V
I
= –400 µA,
OH
IDH
OH
= –3 V to 3 V
IC
V
V
V
= MIN,
= –25 mV,
= –3 V to 3 V
V
= 2 V,
IH(S)
CC±
IDL
IC
Low-level output voltage
0.4
0.4
V
I
= 16 mA,
OL
OL
A
B
A
B
V
V
V
V
V
= 5 V
30
30
75
75
30
30
75
75
ID
I
I
I
I
I
High-level input current
Low-level input current
V
= MAX
= MAX
µA
µA
IH
CC±
= –5 V
= –5 V
= 5 V
ID
–10
–10
40
–10
–10
40
ID
V
CC±
IL
IH
IL
IH
ID
V
V
= MAX,
= 2.4 V
µA
High-level input current into
1G or 2G
CC±
IH(G)
= MAX, V
= MAX V
1
1
mA
CC±
IH(G)
V
CC+
Low-level input current
into 1G or 2G
V
CC±
= MAX,
= 0.4 V
–1.6
–1.6
mA
IL(G)
V
CC±
V
CC±
V
CC±
V
CC±
V
CC±
= MAX,
= MAX, V
= MAX,
V
IH(S)
= 2.4 V
80
2
80
2
µA
mA
mA
µA
High-level input current into S
= MAX V
IH(S)
V
CC+
I
I
I
Low-level input current into S
High-level output current
= 0.4 V
IL(S)
–3.2
–3.2
250
IL
= MIN, V
= MAX
= MAX V
CC+
OH
OS
OH
§
Short-circuit output current
–18
–70
30
mA
Supply current from V
outputs high
,
CC+
I
V
= MAX,
= MAX,
T = 25°C
A
18
18
30
mA
mA
CCH+
CCH–
CC±
CC±
Supply current from V
outputs high
,
CC–
I
V
T
A
= 25°C
–8.4
–15
–8.4
–15
†
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at V = 5 V, V = –5 V, T = 25°C.
Not more than one output should be shorted at a time.
CC+
CC–
A
switching characteristics, V
= ±5 V, T = 25°C, R = 390 Ω (see Figure 2)
A L
±
CC
’107A, SN75107B
SN75108A
TEST
CONDITIONS
PARAMETER
UNIT
ns
MIN
TYP
MAX
MIN
TYP
MAX
25
C
C
C
C
C
C
C
C
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
17
25
Propagation delay time, low- to high-level output,
from differential inputs A and B
L
L
L
L
L
L
L
L
t
t
t
t
PLH(D)
PHL(D)
PLH(S)
PHL(S)
19
17
10
8
25
15
15
Propagation delay time, high- to low-level output,
from differential inputs A and B
ns
19
25
Propagation delay time, low- to high-level output,
from strobe input G or S
ns
13
20
Propagation delay time, high- to low-level output,
from strobe input G or S
ns
13
20
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
Output
‘107A, SN75107B
Differential
Input
V
CC–
1A
1B
1Y
C
L
50 pF
(see Note C)
50 Ω
Pulse
Generator
(see Note A)
V
ref
100 mV
(see Note D)
2A
2B
2Y
390 Ω
390 Ω
1G
S
2G
V
CC+
Output
SN75108A,
C
15 pF
L
(see Note C)
50 Ω
Strobe
Input
(see Note B)
Pulse
Generator
(see Note A)
TEST CIRCUIT
200 mV
0 V
Input A
100 mV
100 mV
t
p1
t
p2
3 V
1.5 V
Strobe Input
G or S
1.5 V
t
t
t
PHL(D)
t
PHL(S)
PLH(D)
PLH(S)
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output Y
V
OL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generators have the following characteristics: Z = 50 Ω, t = 10 ± 5 ns, t = 10 ± 5 ns, t = 500 ns, PRR ≤ 1 MHz,
pd1
O
r
f
t
= 1 µs, PRR ≤ 500 kHz.
pd2
B. Strobe input pulse is applied to Strobe 1G when inputs 1A-1B are being tested, to Strobe S when inputs 1A-1B or 2A-2B are being
tested, and to Strobe 2G when inputs 2A-2B are being tested.
C.
C includes probe and jig capacitance.
L
D. All diodes are 1N916.
Figure 2. Test Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
†
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
HIGH-LEVEL INPUT CURRENT (1A OR 2A)
vs
FREE-AIR TEMPERATURE
6
5
4
3
2
100
80
60
40
20
0
V
= ±5 V
CC±
SN75108A
Noninverting
Inputs
Inverting
Inputs
’107A,
SN75107B
V
= ±5 V
CC±
R = 400 Ω
L
1
T
A
= 25°C
0
–40 –30 –20 –10
0
10
20
30
40
–75 –50 –25
0
25
50
75
100 125
V
ID
– Differential Input Voltage – mV
T
A
– Free-Air Temperature – °C
Figure 3
Figure 4
PROPAGATION DELAY TIME
(DIFFERENTIAL INPUTS)
vs
SUPPPLY CURRENT (OUTPUTS HIGH)
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
40
35
30
25
20
15
10
5
30
25
20
15
10
5
V
C
= ±5 V
CC±
V
CC±
= ±5 V
R
L
L
= 390 Ω
= 50 pF
I
CC+
t
PLH(D)
t
PHL(D)
I
CC–
0
0
–75 –50 –25
0
25
50
75
100 125
–75 –50 –25
0
25
50
75
100 125
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 5
Figure 6
†
8
Values below 0°C and above 70°C apply to SN55107A only.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
†
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME (LOW-TO-HIGH LEVEL)
PROPAGATION DELAY TIME (LOW-TO-HIGH LEVEL)
(DIFFERENTIAL INPUTS)
vs
FREE-AIR TEMPERATURE
(DIFFERENTIAL INPUTS)
vs
FREE-AIR TEMPERATURE
40
120
100
80
V
C
= ±5 V
CC ±
= 15 pF
V
= ±5 V
CC±
= 15 pF
L
35
30
25
20
15
10
5
C
L
R
= 3900 Ω
L
R
= 390 Ω
L
60
40
20
0
R
= 1950 Ω
= 390 Ω
L
L
R
= 1950 Ω
L
R
= 3900 Ω
L
R
0
–75 –50 –25
0
25
50
75
100 125
–75 –50 –25
0
25
50
75
100 125
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 8
Figure 7
SN75108A
SN75108A
PROPAGATION DELAY TIME (STROBE INPUTS)
PROPAGATION DELAY TIME (STROBE INPUTS)
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
V
= ±5 V
= 390 Ω
= 50 pF
V
= ±5 V
= 390 Ω
= 15 pF
CC±
CC±
R
C
R
C
L
L
L
L
t
t
PLH(S)
PHL(S)
t
PHL(S)
t
PLH(S)
0
0
–75 –50 –25
0
25
50
75
100 125
–75 –50 –25
0
25
50
75
100 125
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 9
Figure 10
†
Values below 0°C and above 70°C apply to SN55107A only.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
APPLICATION INFORMATION
basic balanced-line transmission system
The ’107A, SN75107B, and SN75108A dual line devices are designed specifically for use in high-speed
data-transmission systems that utilize balanced terminated transmission lines, such as twisted-pair lines. The
system operates in the balanced mode, so noise induced on one line is also induced on the other. The noise
appears common mode at the receiver input terminals, where it is rejected. The ground connection between
the line driver and receiver is not part of the signal circuit; therefore, system performance is not affected by
circulating ground currents.
The unique driver-output circuit allows terminated transmission lines to be driven at normal line impedances.
High-speed system operation is ensured because line reflections are virtually eliminated when terminated lines
are used. Crosstalk is minimized by low signal amplitudes and low line impedances.
The typical data delay in a system is approximately 30 + 1.3 L ns, where L is the distance in feet separating the
driver and receiver. This delay includes one gate delay in both the driver and receiver.
Data is impressed on the balanced-line system by unbalancing the line voltages with the driver output current.
The driven line is selected by appropriate driver-input logic levels. The voltage difference is approximately:
V
≈ 1/2I
• R
O(on) T
DIFF
High series line resistance causes degradation of the signal. However, the receivers detect signals as low as
25 mV. For normal line resistances, data can be recovered from lines of several thousand feet in length.
Line-termination resistors (R ) are required only at the extreme ends of the line. For short lines, termination
T
resistors at the receiver only may be adequate. The signal amplitude is then approximately:
V
≈ I
• R
O(on) T
DIFF
R
R
T
T
R
R
T
T
A
B
Transmission Line Having
Characteristic Impedance Z
Data Input
Inhibit
Y
O
R
= Z /2
T
O
C
D
L
Strobes
Receiver
‘107A, SN75107B,
SN75108A
Driver
SN55110A, SN75110A,
SN75112
Figure 11. Typical Differential Data Line
data-bus or party-line system
The strobe feature of the receivers and the inhibit feature of the drivers allow these dual line devices to be used
in data-bus or party-line systems. In these applications, several drivers and receivers can share a common
transmission line. An enabled driver transmits data to all enabled receivers on the line while other drivers and
receivers are disabled. Data is time multiplexed on the transmission line. The device specifications allow widely
varying thermal and electrical environments at the various driver and receiver locations. The data-bus system
offers maximum performance at minimum cost.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
APPLICATION INFORMATION
Drivers
SN55110A, SN75110A,
SN75112
Receiver 1
Receiver 2
Receiver 4
Strobes
Y
Y
Y
Strobes
Strobes
R
R
T
T
R
R
T
T
Location 2
Driver 3
Driver 1
Driver 4
Receivers
‘107A, SN75107B,
SN75108A
A
A
B
A
Data
Input
B
B
C
C
D
C
D
Inhibit
D
Location 1
Location 3
Location 4
Figure 12. Typical Differential Party Line
unbalanced or single-line systems
These dual line circuits also can be used in unbalanced or single-line systems. Although these systems do not
offer the same performance as balanced systems for long lines, they are adequate for very short lines where
environmental noise is not severe.
The receiver threshold level is established by applying a dc reference voltage to one receiver input terminal.
The signal from the transmission line is applied to the remaining input. The reference voltage should be
optimized so that signal swing is symmetrical about it for maximum noise margin. The reference voltage should
be in the range of –3 V to 3 V. It can be provided by a voltage supply or by a voltage divider from an available
supply voltage.
A single-ended output from a driver can be used in single-line systems. Coaxial or shielded line is preferred for
minimum noise and crosstalk problems. For large signal swings, the high output current (typically 27 mA) of the
SN75112 is recommended. Drivers can be paralleled for higher current. When using only one channel of the
line drivers, the other channel should be inhibited and/or have its outputs grounded.
SN55110A, SN75110A, SN75112
‘107A, SN75107B, SN75108A
R
A
B
Output
Input
Input
V
ref
Output
C
D
Strobes
Inhibit
V
O
= –I • R
O
Figure 13. Single-Ended Operation
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
APPLICATION INFORMATION
SN75108A dot-AND output connections
The SN75108A line receiver features an open-collector-output circuit that can be connected in the dot-AND
logic configuration with other similar open-collector outputs. This allows a level of logic to be implemented
without additional logic delay.
SN75108A
SN75108A
Output
Dot-AND
Connection
SN5401/SN7401 or
Equivalent
Figure 14. Dot-AND Connection
increasing common-mode input voltage range of receiver
The common-mode voltage range (CMVR) is defined as the range of voltage applied simultaneously to both
input terminals that, if exceeded, does not allow normal operation of the receiver.
The recommended operating CMVR is ±3 V, making it useful in all but the noisiest environments. In extremely
noisy environments, common-mode voltage can easily reach ±10 V to ±15 V if some precautions are not taken
to reduce ground and power supply noise, as well as crosstalk problems. When the receiver must operate in
such conditions, input attenuators should be used to decrease the system common-mode noise to a tolerable
level at the receiver inputs. Differential noise is also reduced by the same ratio. These attenuators were omitted
intentionally from the receiver input terminals so the designer can select resistors that are compatible with his
particular application or environment. Furthermore, the use of attenuators adversely affects the input sensitivity,
the propagation delay time, the power dissipation, and in some cases (depending on the selected resistor
values) the input impedance; thereby reducing the versatility of the receiver.
The ability of the receiver to operate with approximately ±15 V common-mode voltage at the inputs has been
checked using the circuit shown in Figure 15. Resistors R1 and R2 provide a voltage-divider network. Dividers
with three different values presenting a 5-to-1 attenuation were used to operate the differential inputs at
approximately ±3 V common-mode voltage. Careful matching of the two attenuators is needed to balance the
overdrive at the input stage. The resistors used are shown in Table 1.
Table 1
Attenuator 1:
Attenuator 2:
Attenuator 3:
R1 = 2 kΩ,
R1 = 6 kΩ,
R1 = 12 kΩ,
R2 = 0.5 kΩ
R2 = 1.5 kΩ
R2 = 3 kΩ
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
APPLICATION INFORMATION
increasing common-mode input voltage range of receiver (continued)
Table 2 shows some of the typical switching results obtained under such conditions.
Table 2. Typical Propagation Delays for Receiver
With Attenuator Test Circuit Shown in Figure 15
INPUT
ATTENUATOR
TYPICAL
(NS)
DEVICE
PARAMETERS
1
2
3
1
2
3
1
2
3
1
2
3
20
32
42
22
31
33
36
47
57
29
38
41
t
t
t
t
PLH
PHL
PLH
PHL
’107A
SN75107B
SN75108A
5 V
16 V
Receiver
One Attenuator
on Each Input
R
= 390 Ω
L
or
– 14 V
R1
R2
14 V
– 16 V
5 V
15 V or –15 V
R1
R2
Figure 15. Common-Mode Circuit for Testing Input Attenuators With Results Shown in Table 2
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
Two methods of terminating a transmission line to reduce reflections are shown in Figure 16. The first method
uses the resistors as the attenuation network and line termination. The second method uses two additional
resistors for the line terminations.
APPLICATION INFORMATION
R1
(see Note A)
R1
Method 1
Method 2
R2
R3
R3
R3
R3
R3
R2
(see Note A)
R2
R2
R3
(see Note A)
R1
R3 = R1 + R2 = Z /2
R1
R1 + R2 > Z
O
O
R3 = Z /2
O
NOTE A: To minimize the loading, the values of R1 and R2 should be fairly large. Examples of possible values are shown in Table 1.
Figure 16. Termination Techniques
For party-line operation, method 2 should be used as shown in Figure 17.
Attenuation Network
Z
Z
Z
Z
O
O
O
O
R3
R3
R3
R3
2
2
2
2
Figure 17. Party-Line Termination Technique
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
APPLICATION INFORMATION
furnace control using the SN75108A
The furnace control circuit in Figure 18 is an example of the possible use of the SN75108A series in areas other
than what would normally be considered electronic systems. A description of the operation of this control
follows. When the room temperature is below the desired level, the resistance of the room temperature sensor
is high and channel 1 noninverting input is below (less positive than) the reference level set on the input
differential amplifier. This situation causes a low output, operating the heat-on relay and turning on the heat.
The channel 2 noninverting input is below the reference level when the bonnet temperature of the furnace
reaches the desired level. This causes a low output, thus operating the blower relay. Normally the furnace is
shut down when the room temperature reaches the desired level and the channel 1 output goes high, turning
the heat off. The blower remains on as long as the bonnet temperature is high, even after the heat-on relay is
off. There is also a safety switch in the bonnet that shuts down the furnace if the temperature there exceeds
desired limits. The types of temperature-sensing devices and bias-resistor values used are determined by the
particular operating conditions encountered.
5 V
Bonnet Upper
Limit Switch
Bonnet
Temp.
Room
Temp.
+ T
– T
Sensor
Sensor
Channel 1
1 Y
2 Y
To Heat-on
Relay Return
A
Room
Temp.
Setting
B
To Blower
Relay Return
2A
2B
Blower on Control
Channel 2
Figure 18. Furnace Control Using SN75108A
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
APPLICATION INFORMATION
repeaters for long lines
In some cases, the driven line may be so long that the noise level on the line reaches the common-mode limits
or the attenuation becomes too large and results in poor reception. In such a case, a simple application of a
receiver and a driver as repeaters [shown in Figure 19(a)] restores the signal level and allows an adequate
signal level at the receiving end. If multichannel operation is desired, then proper gating for each channel must
be sent through the repeater station using another repeater set as in Figure 19(b).
Repeaters
Data In
Data Out
Data Out
Driver
Driver
Driver
Receiver
Receiver
P
P
(a) SINGLE-CHANNEL LINE
Data In
Driver
Receiver
Receiver
Receiver
Receiver
P
P
P
P
Strobe
Ckt
Driver
Clock In
(b) MULTICHANNEL LINE WIDTH WITH STROBE
Figure 19. Receiver-Driver Repeaters
receiver as dual differential comparator
There are many applications for differential comparators, such as voltage comparison, threshold detection,
controlled Schmitt triggering, and pulse-width control.
As a differential comparator, a ’107A or SN75108A can be connected to compare the noninverting input terminal
with the inverting input as shown in Figure 20. The output is high or low, resulting from the A input being greater
or less than the reference. The strobe inputs allow additional control over the circuit so that either output, or both,
can be inhibited.
Strobe 1
1A
Reference 1
Output 1
1B
Strobe 1, 2
2A
Output 2
Reference 2
2B
Strobe 2
Figure 20. SN75107A Series Receiver as a Dual Differential Comparator
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
APPLICATION INFORMATION
window detector
The window detector circuit in Figure 21 has a large number of applications in test equipment and in determining
upper limits, lower limits, or both at the same time, such as detecting whether a voltage or signal has exceeded
its window limits. Illumination of the upper-limit (lower-limit) indicator shows that the input voltage is above
(below) the selected upper (lower) limit. A mode selector is provided for selecting the desired test. For window
detecting, the upper-and-lower-limits test position is used.
5 V –5 V
5 V
1 kΩ
1 kΩ
500 Ω
Upper-Limit
Indicator
Set
Upper
Limit
5 kΩ
500 Ω
Input From
Test Point
Lower-Limit
Indicator
Set
Lower
Limit
1 kΩ
4
4.7 kΩ
3
2
4.7 kΩ
4.7 kΩ
1
Mode
Selector
MODE SELECTOR LEGEND
POSITION
CONDITION
Off
1
2
3
4
Test for Upper Limit
Test for Lower Limit
Test for Upper and Lower Limits
Figure 21. Window Detector Using SN75108A
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
APPLICATION INFORMATION
temperature controller with zero-voltage switching
The circuit in Figure 22 switches an electric-resistive heater on or off by providing negative-going pulses to the
gate of a triac during the time interval when the line voltage is passing through zero. The pulse generator is the
2N5447 and four diodes. This portion of the circuit provides negative-going pulses during the short time
(approximately 100 µs) when the line voltage is near zero. These pulses are fed to the inverting input of one
channel of the SN75108A. If the room temperature is below the desired level, the resistance of the thermistor
is high and the noninverting input of channel 2 is above the reference level determined by the thermostat setting.
This provides a high-level output from channel 2. This output is ANDed with the positive-going pulses from the
output of channel 1, which are reinverted in the 2N5449.
10-V
Zener
+
5-V
250 µF
Zener
250 µF
+
V
V
CC –
CC +
1A
1B
2N5447
Channel 1
Channel 2
2A
2B
120 V to
220 V, 60 Hz
2N5449
– T
SN75108A
GND
Thermostat
Setting
Heater
Load
Figure 22. Zero-Voltage Switching Temperature Controller
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-9690301Q2A
5962-9690301QCA
5962-9690301QDA
JM38510/10401BCA
SN55107AJ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
14
14
14
14
14
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
W
J
CDIP
CDIP
SOIC
J
SN75107AD
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75107ADE4
SN75107ADG4
SN75107ADR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
D
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75107ADRE4
SN75107ADRG4
SN75107AN
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN75107ANE4
SN75107ANSR
SN75107ANSRE4
SN75107ANSRG4
SN75107BD
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
NS
NS
NS
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75107BDE4
SN75107BDG4
SN75107BDR
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75107BDRE4
SN75107BDRG4
SN75107BN
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN75107BNE4
SN75107BNSR
SN75107BNSRE4
SN75107BNSRG4
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
NS
NS
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
Orderable Device
SN75108AD
Status (1)
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
14
14
14
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75108ADE4
SN75108ADG4
SN75108ADR
SN75108ADRE4
SN75108ADRG4
SN75108AN
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
D
D
D
D
D
N
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ACTIVE
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ACTIVE
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ACTIVE
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ACTIVE
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
OBSOLETE
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SNJ55107AFK
SNJ55107AJ
SNJ55107AW
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
14
14
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN75107ADR
SN75107ANSR
SN75107BDR
SN75107BNSR
SN75108ADR
SOIC
SO
D
NS
D
14
14
14
14
14
2500
2000
2500
2000
2500
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
6.5
8.2
6.5
8.2
6.5
9.0
10.5
9.0
2.1
2.5
2.1
2.5
2.1
8.0
12.0
8.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
SOIC
SO
NS
D
10.5
9.0
12.0
8.0
SOIC
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN75107ADR
SN75107ANSR
SN75107BDR
SN75107BNSR
SN75108ADR
SOIC
SO
D
NS
D
14
14
14
14
14
2500
2000
2500
2000
2500
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
33.0
33.0
33.0
33.0
33.0
SOIC
SO
NS
D
SOIC
Pack Materials-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
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