SN75110AJ [TI]

DUAL LINE DRIVERS; 双线路驱动器
SN75110AJ
型号: SN75110AJ
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

DUAL LINE DRIVERS
双线路驱动器

线路驱动器或接收器 驱动程序和接口 接口集成电路
文件: 总18页 (文件大小:547K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
ꢀꢁꢂ ꢂ ꢃꢃ ꢄ ꢅꢆ ꢀꢁꢇ ꢂ ꢃꢃ ꢄ ꢅꢆ ꢀ ꢁꢇ ꢂꢃꢃꢈ  
ꢉꢊꢅ ꢋ ꢋ ꢌꢁꢍ ꢉ ꢎꢌ ꢏ ꢍꢎ ꢀ  
SLLS106G − DECEMBER 1975 − REVISED NOVEMBER 2004  
SN55110A . . . J OR W PACKAGE  
SN75110A . . . D, N, OR NS PACKAGE  
SN75112 . . . D OR N PACKAGE  
(TOP VIEW)  
D
Improved Stability Over Supply Voltage and  
Temperature Ranges  
D
D
D
D
D
D
D
D
D
Constant-Current Outputs  
High Speed  
1A  
1B  
V
CC+  
1Y  
1Z  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
Standard Supply Voltages  
High Output Impedance  
1C  
High Common-Mode Output Voltage Range  
. . . −3 V to 10 V  
2C  
V
CC−  
2A  
D
2B  
2Z  
2Y  
TTL-Input Compatibility  
8
GND  
Inhibitor Available for Driver Selection  
Glitch Free During Power Up/Power Down  
SN55110A . . . FK PACKAGE  
(TOP VIEW)  
SN75112 and External Circuit Meets or  
Exceeds the Requirements of CCITT  
Recommendation V.35  
3
2
1 20 19  
18  
description/ordering information  
1Z  
NC  
V
1C  
NC  
2C  
NC  
2A  
4
5
6
7
8
17  
16  
15  
14  
The SN55110A, SN75110A, and SN75112 dual  
line drivers have improved output current  
regulation with supply-voltage and temperature  
variations. In addition, the higher current of the  
SN75112 (27 mA) allows data to be transmitted  
over longer lines. These drivers offer optimum  
performance when used with the SN55107A,  
SN75107A, and SN75108A line receivers.  
CC−  
NC  
D
9 10 11 12 13  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PART NUMBER  
SN75110AN  
SN75112N  
SN75110AN  
SN75112N  
PDIP (N)  
SOIC (D)  
Tube of 25  
Tube of 50  
SN75110AD  
SN75110ADR  
SN75112D  
SN75110A  
SN75112  
Reel of 2500  
Tube of 50  
0°C to 70°C  
Reel of 2500  
Reel of 2000  
SN75112DR  
SN75110ANSR  
SN55110AJ  
SOP (NS)  
CDIP (J)  
SN75110A  
SN55110AJ  
SNJ55110AJ  
SNJ55110AW  
SNJ55110AFK  
Tube of 25  
SNJ55110AJ  
SNJ55110AW  
SNJ55110AFK  
−55°C to 125°C  
CFP (W)  
Tube of 150  
Tube of 55  
LCCC (FK)  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2004, Texas Instruments Incorporated  
ꢑ ꢕ ꢠ ꢘ ꢗꢣ ꢞꢝ ꢛꢜ ꢝꢗ ꢙꢠ ꢢꢔ ꢚꢕ ꢛ ꢛꢗ ꢪꢌ ꢋꢫ ꢐꢎ ꢬ ꢫꢭꢮꢂ ꢭꢂꢆ ꢚꢢꢢ ꢠꢚ ꢘ ꢚ ꢙꢟ ꢛꢟꢘ ꢜ ꢚ ꢘ ꢟ ꢛꢟ ꢜꢛꢟ ꢣ  
ꢛ ꢟ ꢜ ꢛꢔ ꢕꢩ ꢗꢖ ꢚ ꢢꢢ ꢠꢚ ꢘ ꢚ ꢙ ꢟ ꢛ ꢟ ꢘ ꢜ ꢤ  
ꢞ ꢕꢢ ꢟꢜꢜ ꢗ ꢛꢥꢟ ꢘ ꢧꢔ ꢜꢟ ꢕ ꢗꢛꢟ ꢣꢤ ꢑ ꢕ ꢚꢢ ꢢ ꢗ ꢛꢥꢟ ꢘ ꢠꢘ ꢗ ꢣꢞꢝ ꢛꢜ ꢆ ꢠꢘ ꢗ ꢣꢞꢝ ꢛꢔꢗ ꢕ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢂꢃꢃ ꢄꢅ ꢆ ꢀꢁ ꢇꢂ ꢃꢃ ꢄ ꢅꢆ ꢀ ꢁꢇ ꢂ ꢃꢃ ꢈ  
ꢉ ꢊꢅꢋ ꢋ ꢌ ꢁ ꢍ ꢉ ꢎꢌ ꢏ ꢍ ꢎꢀ  
SLLS106G − DECEMBER 1975 − REVISED NOVEMBER 2004  
description/ordering information (continued)  
These drivers feature independent channels with common voltage supply and ground terminals. The significant  
difference between the three drivers is in the output-current specification. The driver circuits feature a constant  
output current that is switched to either of two output terminals by the appropriate logic levels at the input  
terminals. The output current can be switched off (inhibited) by low logic levels on the enable inputs. The output  
current nominally is 12 mA for the ’110A devices and is 27 mA for the SN75112.  
The enable/inhibit feature is provided so the circuits can be used in party-line or data-bus applications. A strobe  
or inhibitor (enable D), common to both drivers, is included for increased driver-logic versatility. The output  
current in the inhibited mode, I  
, is specified so that minimum line loading is induced when the driver is used  
O(off)  
in a party-line system with other drivers. The output impedance of the driver in the inhibited mode is very high.  
The output impedance of a transistor is biased to cutoff.  
The driver outputs have a common-mode voltage range of −3 V to 10 V, allowing common-mode voltage on the  
line without affecting driver performance.  
All inputs are diode clamped and are designed to satisfy TTL-system requirements. The inputs are tested at  
2 V for high-logic-level input conditions and 0.8 V for low-logic-level input conditions. These tests ensure  
400-mV noise margin when interfaced with TTL Series 54/74 devices.  
The SN55110A is characterized for operation over the full military temperature range of −55°C to 125°C. The  
SN75110A and SN75112 are characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
(each driver)  
LOGIC  
INPUTS  
ENABLE  
INPUTS  
OUTPUTS  
A
B
X
X
X
L
C
L
D
Y
Z
X
X
L
X
L
Off  
Off  
On  
On  
Off  
Off  
Off  
Off  
Off  
On  
X
H
H
H
H
H
H
X
H
H
H = high level, L = low level, X = irrelevant  
When using only one channel of the line drivers,  
the other channel should be inhibited and/or have  
its outputs grounded.  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀꢁꢂ ꢂ ꢃꢃ ꢄ ꢅꢆ ꢀꢁ ꢇꢂ ꢃꢃ ꢄ ꢅꢆ ꢀ ꢁꢇ ꢂꢃꢃꢈ  
ꢉꢊꢅ ꢋ ꢋ ꢌꢁꢍ ꢉ ꢎꢌ ꢏ ꢍꢎ ꢀ  
SLLS106G − DECEMBER 1975 − REVISED NOVEMBER 2004  
schematic (each driver)  
14  
V
CC+  
2.2 kΩ  
NOM  
+
3, 4  
10  
C
D
To Other  
Driver  
+
2.2 kΩ  
NOM  
8, 13  
Y
9, 12  
Z
1, 5  
2, 6  
A
B
7
GND  
Common to Both Drivers  
+
11  
V
CC−  
+
. . . V  
. . . V  
Bus  
CC+  
Bus  
CC−  
To Other Driver  
Pin numbers shown are for the D, J, N, NS, and W packages.  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢂꢃꢃ ꢄꢅ ꢆ ꢀꢁ ꢇꢂ ꢃꢃ ꢄ ꢅꢆ ꢀ ꢁꢇ ꢂ ꢃꢃ ꢈ  
ꢉ ꢊꢅꢋ ꢋ ꢌ ꢁ ꢍ ꢉ ꢎꢌ ꢏ ꢍ ꢎꢀ  
SLLS106G − DECEMBER 1975 − REVISED NOVEMBER 2004  
absolute maximum ratings over operating free-air temperature (unless otherwise noted)  
Supply voltage: V  
V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V  
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −7 V  
CC+  
CC−  
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V  
I
Output voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 V to 12 V  
O
Package thermal impedance, θ (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W  
JA  
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W  
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W  
Package thermal impedance, θ (see Notes 4 and 5): FK package . . . . . . . . . . . . . . . . . . . . . . . . 13.42°C/W  
JC  
J package . . . . . . . . . . . . . . . . . . . . . . . . . 15.05°C/W  
W package . . . . . . . . . . . . . . . . . . . . . . . . 14.65°C/W  
Operating virtual junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C  
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C  
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or W package . . . . . . . . . . . . . . . . 300°C  
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. Voltage values are with respect to network ground terminal.  
2. Maximum power dissipation is a function of T (max), θ , and T . The maximum allowable power dissipation at any allowable  
J
JA  
A
ambient temperature is P = (T (max) − T )/θ . Operating at the absolute maximum T of 150°C can affect reliability.  
D
J
A
JA  
3. The package thermal impedance is calculated in accordance with JESD 51-7.  
4. Maximum power dissipation is a function of T (max), θ , and T . The maximum allowable power dissipation at any allowable case  
J
J
JC  
C
temperature is P = (T (max) − T )/θ . Operating at the absolute maximum T of 150°C can affect reliability.  
5. The package thermal impedance is calculated in accordance with MIL-STD-883.  
D
J
C
JC  
J
recommended operating conditions (see Note 6)  
SN75110A  
SN75112  
SN55110A  
MIN NOM  
UNIT  
MAX  
MIN NOM  
MAX  
V
V
+
Supply voltage  
4.5  
−4.5  
0
5
5.5  
4.75  
5
5.25  
V
V
CC  
Supply voltage  
−5  
−5.5 −4.75  
−5 −5.25  
CC−  
Positive common-mode output voltage  
Negative common-mode output voltage  
High-level input voltage  
10  
−3  
0
0
2
10  
−3  
V
0
V
V
V
2
V
IH  
Low-level output voltage  
Operating free-air temperature  
0.8  
0.8  
70  
V
IL  
T
A
−55  
125  
0
°C  
NOTE 6: When using only one channel of the line drivers, the other channel should be inhibited and/or have its outputs grounded.  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀꢁꢂ ꢂ ꢃꢃ ꢄ ꢅꢆ ꢀꢁ ꢇꢂ ꢃꢃ ꢄ ꢅꢆ ꢀ ꢁꢇ ꢂꢃꢃꢈ  
ꢉꢊꢅ ꢋ ꢋ ꢌꢁꢍ ꢉ ꢎꢌ ꢏ ꢍꢎ ꢀ  
SLLS106G − DECEMBER 1975 − REVISED NOVEMBER 2004  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
SN55110A  
SN75112  
SN75110A  
PARAMETER  
UNIT  
TEST CONDITIONS  
MIN TYP  
MAX  
−1.5  
15  
MIN TYP  
MAX  
−1.5  
40  
V
Input clamp voltage  
V
V
= MIN,  
I = −12 mA  
L
−0.9  
12  
−0.9  
27  
V
IK  
CC  
CC  
CC  
= MAX,  
V
O
= 10 V  
V
V
= MIN to MAX,  
= −1 V to 1 V, T = 25°C  
I
On-state output current  
Off-state output current  
24  
15  
28  
27  
32  
mA  
O(on)  
O
A
V
= MIN,  
= MIN,  
V
= −3 V  
= 10 V  
6.5  
12  
CC  
CC  
O
O
I
I
V
V
100  
1
100  
1
µA  
O(off)  
Input current  
at maximum  
input voltage  
A, B, or C inputs  
D input  
V
V
= MAX,  
= MAX,  
V = 5.5 V  
I
mA  
I
CC  
2
2
A, B, or C inputs  
D input  
40  
80  
−3  
−6  
40  
80  
−3  
−6  
High-level  
input current  
I
I
V = 2.4 V  
I
µA  
IH  
CC  
A, B, or C inputs  
D input  
Low-level  
input current  
V
V
= MAX,  
= MAX,  
V = 0.4 V  
I
mA  
IL  
CC  
CC  
Supply current from V  
with driver enabled  
CC  
I
I
A and B inputs at 0.4 V,  
C and D inputs at 2 V  
23  
35  
25  
40  
mA  
mA  
CC+(on)  
V
CC  
= MAX,  
Supply current from V  
with driver enabled  
CC−  
A and B inputs at 0.4 V,  
C and D inputs at 2 V  
−34  
−50  
−65 −100  
CC−(on)  
Supply current from V  
with driver inhibited  
V
= MAX,  
CC−  
CC  
A, B, C, and D inputs at 0.4 V  
I
I
21  
30  
mA  
mA  
CC+(off)  
Supply current from V  
with driver inhibited  
V
= MAX,  
CC  
CC  
A, B, C, and D inputs at 0.4 V  
−17  
−32  
CC−(off)  
For conditions shown as MIN or MAX, use appropriate value specified under recommended operating conditions.  
All typical values are at V = 5 V, V = −5 V, T = 25°C.  
CC+ CC−  
A
switching characteristics, V  
= 5 V, T = 25°C (see Figure 1)  
CC  
A
FROM  
(INPUT)  
TO  
(OUTPUT)  
§
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
ns  
PARAMETER  
t
t
t
t
9
9
15  
15  
25  
25  
PLH  
PHL  
PLH  
PHL  
A or B  
C or D  
Y or Z  
C
C
= 40 pF,  
= 40 pF,  
R
R
= 50 Ω,  
= 50 Ω,  
L
L
L
L
16  
13  
Y or Z  
ns  
§
t
t
= propagation delay time, low- to high-level output  
= propagation delay time, high- to low-level output  
PLH  
PHL  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢂꢃꢃ ꢄꢅ ꢆ ꢀꢁ ꢇꢂ ꢃꢃ ꢄ ꢅꢆ ꢀ ꢁꢇ ꢂ ꢃꢃ ꢈ  
ꢉ ꢊꢅꢋ ꢋ ꢌ ꢁ ꢍ ꢉ ꢎꢌ ꢏ ꢍ ꢎꢀ  
SLLS106G − DECEMBER 1975 − REVISED NOVEMBER 2004  
PARAMETER MEASUREMENT INFORMATION  
V
CC+  
V
CC−  
Input A or B  
50 Ω  
Output Y  
= 40 pF  
890 Ω  
890 Ω  
C
L
R
R
= 50 Ω  
L
L
(see Note A)  
Pulse  
Generator  
(See Note B)  
Output Z  
Pulse  
Generator  
(See Note B)  
C
= 40 pF  
(see Note A)  
L
= 50 Ω  
To Other Driver  
See Note C  
Input C or D  
50 Ω  
TEST CIRCUIT  
3 V  
50%  
t
50%  
Input A or B  
0 V  
w1  
t
w2  
3 V  
0 V  
50%  
t
50%  
Enable C or D  
t
t
t
PHL  
PLH  
PHL  
PLH  
Off  
On  
Output Y  
Output Z  
50%  
50%  
50%  
50%  
t
t
PLH  
PHL  
Off  
On  
50%  
50%  
VOLTAGE WAVEFORMS  
NOTES: A.  
B. The pulse generators have the following characteristics: Z = 50 , t = t = 10 5 ns, t = 500 ns, PRR 1 MHz, t  
w1 w2  
C includes probe and jig capacitance.  
L
= 1 µs,  
O
r
f
PRR 500 kHz.  
C. For simplicity, only one channel and the enable connections are shown.  
Figure 1. Test Circuit and Voltage Waveforms  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀꢁꢂ ꢂ ꢃꢃ ꢄ ꢅꢆ ꢀꢁ ꢇꢂ ꢃꢃ ꢄ ꢅꢆ ꢀ ꢁꢇ ꢂꢃꢃꢈ  
ꢉꢊꢅ ꢋ ꢋ ꢌꢁꢍ ꢉ ꢎꢌ ꢏ ꢍꢎ ꢀ  
SLLS106G − DECEMBER 1975 − REVISED NOVEMBER 2004  
TYPICAL CHARACTERISTICS  
SN75112  
ON-STATE OUTPUT CURRENT  
vs  
SN55110A, SN75110A  
ON-STATE OUTPUT CURRENT  
vs  
NEGATIVE SUPPLY VOLTAGE  
NEGATIVE SUPPLY VOLTAGE  
35  
30  
25  
20  
15  
10  
5
14  
12  
10  
8
V
V
T
= 4.5 V  
= −3 V  
= 25°C  
V
V
T
= 4.5 V  
= −3 V  
= 25°C  
CC+  
O
A
CC+  
O
A
6
4
2
0
0
−3  
−4  
−5  
−6  
−7  
−3  
−4  
−5  
−6  
−7  
V
CC−  
− Negative Supply Voltage − V  
V
CC−  
− Negative Supply Voltage − V  
Figure 2  
Figure 3  
7
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ꢀ ꢁꢂ ꢂꢃꢃ ꢄꢅ ꢆ ꢀꢁ ꢇꢂ ꢃꢃ ꢄ ꢅꢆ ꢀ ꢁꢇ ꢂ ꢃꢃ ꢈ  
ꢉ ꢊꢅꢋ ꢋ ꢌ ꢁ ꢍ ꢉ ꢎꢌ ꢏ ꢍ ꢎꢀ  
SLLS106G − DECEMBER 1975 − REVISED NOVEMBER 2004  
APPLICATION INFORMATION  
special pulse-control circuit  
Figure 4 shows a circuit that can be used as a pulse-generator output or in many other testing applications.  
OUTPUTS  
INPUT  
A
Z
Y
High  
Low  
Off On  
On Off  
5 V  
3
2
1
3
4
4
6
2
5
V
Y
5
CC+  
1
6
A
B
Input  
2.5 V  
Z
C
D
3
4
2
1/2 ’110A  
or SN75112  
5
V
CC−  
6
GND  
1
−5 V  
To Other Logic and  
Strobe Inputs  
Output  
Input Pulse  
0 V  
Switch  
Position  
1
2
3
4
5
6
Output Pulse  
0 V  
Figure 4. Pulse-Control Circuit  
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀꢁꢂ ꢂ ꢃꢃ ꢄ ꢅꢆ ꢀꢁ ꢇꢂ ꢃꢃ ꢄ ꢅꢆ ꢀ ꢁꢇ ꢂꢃꢃꢈ  
ꢉꢊꢅ ꢋ ꢋ ꢌꢁꢍ ꢉ ꢎꢌ ꢏ ꢍꢎ ꢀ  
SLLS106G − DECEMBER 1975 − REVISED NOVEMBER 2004  
APPLICATION INFORMATION  
using the SN75112 as a CCITT-recommended V.35 line driver  
The SN75112 dual line driver, the SN75107A dual line receiver, and some external resistors can be used to  
implement the data-interchange circuit of CCITT recommendation V.35 (1976) modem specification. The circuit  
of one channel is shown in Figure 5 and meets the requirement of the interface as specified by Appendix 11  
of CCITT V.35 and is summarized in Table 1 (V.35 has been replaced by ITU V.11).  
Table 1. CCITT V.35 Electrical Requirements  
GENERATOR  
MIN  
50  
MAX  
150  
165  
660  
UNIT  
Source impedance, Z  
source  
Resistance to ground, R  
135  
440  
40  
Differential output voltage, V  
mV  
ns  
OD  
10% to 90% rise time, t  
or  
r
0.01 × ui  
Common-mode output voltage, V  
−0.6  
0.6  
V
OC  
LOAD (RECEIVER)  
MIN  
90  
MAX  
110  
UNIT  
Input impedance, Z  
I
Resistance to ground, R  
135  
165  
ui = unit interval or minimum signal-element pulse duration  
5 V  
5 V  
5 V  
R3  
390 Ω  
Strobe  
100 pF  
R1  
R6  
6
1/2 SN75112  
1.3 kΩ  
50 Ω  
13 1Y  
1
1
1A  
1B  
R8  
1A  
Data In  
Data Out  
1Y  
4
5
R5  
75 Ω  
2
12  
1Z  
2
125 Ω  
1B  
10  
3
R7  
50 Ω  
Enable  
1G  
Enable  
1C  
1/2 SN75107A  
100 pF  
R4  
390 Ω  
R2  
1.3 kΩ  
5 V  
All resistors are 5%, 1/4 W.  
Figure 5. CCITT-Recommended V.35 Interface Using the SN75112 and SN75107A  
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
18-Jul-2006  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
LCCC  
CDIP  
CFP  
Drawing  
5962-87547012A  
5962-8754701CA  
5962-8754701DA  
SN55110AJ  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
FK  
J
20  
14  
14  
14  
14  
1
1
1
1
TBD  
TBD  
TBD  
TBD  
POST-PLATE N / A for Pkg Type  
A42 SNPB  
A42 SNPB  
A42 SNPB  
N / A for Pkg Type  
N / A for Pkg Type  
N / A for Pkg Type  
W
J
CDIP  
SOIC  
SN75110AD  
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN75110ADE4  
SN75110ADR  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
SOIC  
D
D
D
14  
14  
14  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN75110ADRE4  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN75110AJ  
SN75110AN  
OBSOLETE  
ACTIVE  
CDIP  
PDIP  
J
14  
14  
TBD  
Call TI  
Call TI  
N
25  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
SN75110ANE4  
SN75110ANSR  
SN75110ANSRE4  
SN75112D  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
PDIP  
SO  
N
NS  
NS  
D
14  
14  
14  
14  
14  
14  
14  
14  
14  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN75112DE4  
SN75112DR  
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN75112DRE4  
SN75112N  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
CU NIPDAU N / A for Pkg Type  
POST-PLATE N / A for Pkg Type  
SN75112NE4  
N
25  
Pb-Free  
(RoHS)  
SNJ55110AFK  
SNJ55110AJ  
SNJ55110AW  
ACTIVE  
ACTIVE  
ACTIVE  
LCCC  
CDIP  
CFP  
FK  
J
20  
14  
14  
1
1
1
TBD  
TBD  
TBD  
A42 SNPB  
A42 SNPB  
N / A for Pkg Type  
N / A for Pkg Type  
W
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
18-Jul-2006  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
MECHANICAL DATA  
MLCC006B – OCTOBER 1996  
FK (S-CQCC-N**)  
LEADLESS CERAMIC CHIP CARRIER  
28 TERMINAL SHOWN  
A
B
NO. OF  
TERMINALS  
**  
18 17 16 15 14 13 12  
MIN  
MAX  
MIN  
MAX  
0.342  
(8,69)  
0.358  
(9,09)  
0.307  
(7,80)  
0.358  
(9,09)  
19  
20  
11  
10  
9
20  
28  
44  
52  
68  
84  
0.442  
(11,23)  
0.458  
(11,63)  
0.406  
(10,31)  
0.458  
(11,63)  
21  
B SQ  
22  
0.640  
(16,26)  
0.660  
(16,76)  
0.495  
(12,58)  
0.560  
(14,22)  
8
A SQ  
23  
0.739  
(18,78)  
0.761  
(19,32)  
0.495  
(12,58)  
0.560  
(14,22)  
7
24  
25  
6
0.938  
(23,83)  
0.962  
(24,43)  
0.850  
(21,6)  
0.858  
(21,8)  
5
1.141  
(28,99)  
1.165  
(29,59)  
1.047  
(26,6)  
1.063  
(27,0)  
26 27 28  
1
2
3
4
0.080 (2,03)  
0.064 (1,63)  
0.020 (0,51)  
0.010 (0,25)  
0.020 (0,51)  
0.010 (0,25)  
0.055 (1,40)  
0.045 (1,14)  
0.045 (1,14)  
0.035 (0,89)  
0.045 (1,14)  
0.035 (0,89)  
0.028 (0,71)  
0.022 (0,54)  
0.050 (1,27)  
4040140/D 10/96  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. This package can be hermetically sealed with a metal lid.  
D. The terminals are gold plated.  
E. Falls within JEDEC MS-004  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
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