SN75163BDW [TI]

OCTAL LINE TRANSCEIVER, PDSO20;


型号：	SN75163BDW
厂家：	TEXAS INSTRUMENTS
描述：	OCTAL LINE TRANSCEIVER, PDSO20
文件：	总9页 (文件大小：155K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ

ꢈ ꢉꢊꢋꢌꢍꢎ ꢏ ꢁꢏꢐꢋꢌ ꢑꢒ ꢓꢐꢒꢈ ꢀꢏ ꢍꢔꢁ ꢊ ꢏꢐꢕꢋꢉꢏ ꢍꢇꢓ ꢀꢍꢊ ꢐꢋ ꢁꢀ ꢉꢏ ꢔ ꢖꢏ ꢐ

ꢗ

SLLS006A − D2611, OCTOBER 1985 − REVISED FEBRUARY 1993

DW OR N PACKAGE

(TOP VIEW)

• 8-Channel Bidirectional Transceivers

• Power-Up/Power-Down Protection

(Glitch Free)

20 VCC

• High-Speed Low-Power Schottky Circuitry

• Low Power Dissipation . . . 66 mW Max Per

Channel

GPIB

I/O Ports

Terminal

I/O Ports

• High-impedance PNP Inputs

• Receiver Hysteresis . . . 650 mV Typ

• Open-Collector Driver Output Option

• No Loading of Bus When Device Is

Powered Down (V

= 0)

GND

description

The SN75163B octal general-purpose interface

bus transceiver is a monolithic, high-speed, low-

power Schottky device. It is designed for two-way

NOT RECOMMENDED FOR NEW DESIGN

data communications over single-ended transmission lines. The transceiver features driver outputs that can be

operated in either the open-collector or 3-state modes. If talk enable (TE) is high, these outputs have the

characteristics of open-collector outputs when pullup enable (PE) is low and of 3-state outputs when PE is high.

Taking TE low places the outputs in the high-impedance state. The driver outputs are designed to handle loads

of up to 48 mA of sink current. Each receiver features pnp transistor inputs for high input impedance and 400 mV

of hysteresis for increased noise immunity.

Output glitches during power up and power down are eliminated by an internal circuit that disables both the bus

and receiver outputs. The outputs do not load the bus when V

= 0.

The SN75163B is characterized for operation from 0°C to 70°C.

Function Tables

EACH DRIVER

EACH RECEIVER

INPUTS

OUTPUT

H = high level, L = low level, X = irrelevant, Z = high-impedance state

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ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ

ꢝ

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2−1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ

ꢈꢉ ꢊꢋ ꢌꢍ ꢎꢏꢁ ꢏ ꢐꢋ ꢌꢑꢒ ꢓꢐꢒ ꢈ ꢀꢏ ꢍ ꢔ ꢁꢊ ꢏꢐꢕꢋꢉꢏ ꢍꢇꢓ ꢀꢍꢊ ꢐꢋ ꢁꢀꢉꢏ ꢔꢖꢏ ꢐ

ꢗ

SLLS006A − D2611, OCTOBER 1985 − REVISED FEBRUARY 1993

†

logic symbol

logic diagram (positive logic)

M1 (3S)

M2 (0C)

EN3 (XMT)

EN4 (RCV)

3(1 /2

)

Terminal

I/O Ports

GPIB

I/O

Ports

{

This symbol is in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.

Designates 3-state outputs

Designates open-collector outputs

schematics of inputs and outputs

EQUIVALENT OF ALL CONTROL INPUTS

EQUIVALENT OF ALL INPUT/OUTPUT PORTS

10 kΩ

9 kΩ

NOM

Input

GND

4 kΩ

NOM

GND

Input/Output Port

Driver output R = 30 Ω NOM

Receiver output R = 110 Ω NOM

2−2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇ

ꢈ ꢉꢊꢋꢌꢍꢎ ꢏ ꢁꢏꢐꢋꢌ ꢑꢒ ꢓꢐꢒꢈ ꢀꢏ ꢍꢔꢁ ꢊ ꢏꢐꢕꢋꢉꢏ ꢍꢇꢓ ꢀꢍꢊ ꢐꢋ ꢁꢀ ꢉꢏ ꢔ ꢖꢏ ꢐ

ꢗ

SLLS006A − D2611, OCTOBER 1985 − REVISED FEBRUARY 1993

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

Low-level driver output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

Continuous total power dissipation (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

NOTES: 1. All voltage values are with respect to network ground terminal.

DISSIPATION RATING TABLE

≤ 25°C

DERATING FACTOR

T = 70°C

POWER RATING

PACKAGE

POWER RATING

ABOVE T = 25°C

1125 mW

9.0 mW/°C

9.2 mW/°C

720 mW

1150 mW

736 mW

recommended operating conditions

MIN NOM

MAX

UNIT

Supply voltage, V

4.75

5.25

High-level input voltage, V

Low-level input voltage, V

0.8

−10

−800

Bus ports with pullups active

µA

High-level output current, I

Terminal ports

Bus ports

High-level output current, I

Terminal ports

Operating free-air temperature, T

°C

2−3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ

ꢈꢉ ꢊꢋ ꢌꢍ ꢎꢏꢁ ꢏ ꢐꢋ ꢌꢑꢒ ꢓꢐꢒ ꢈ ꢀꢏ ꢍ ꢔ ꢁꢊ ꢏꢐꢕꢋꢉꢏ ꢍꢇꢓ ꢀꢍꢊ ꢐꢋ ꢁꢀꢉꢏ ꢔꢖꢏ ꢐ

ꢗ

SLLS006A − D2611, OCTOBER 1985 − REVISED FEBRUARY 1993

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

†

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

Input clamp voltage

I = −18 mA

−0.8

0.65

3.5

−1.5

Hysteresis (V

− V

T+ T−

)

Bus

See Figure 8

0.4

2.7

2.5

hys

Terminal

Bus

= −800 µA,

= −10 mA,

= 16 mA,

= 48 mA,

= 5.5 V,

TE at 0.8 V

High-level output voltage

Low-level output voltage

PE and TE at 2 V

TE at 0.8 V

3.3

Terminal

Bus

0.3

0.5

PE and TE at 2 V

PE at 0.8 V,

0.4

High-level output current

(open-collector mode)

Bus

100

µA

D and TE at 2 V

= 2.7 V

= 0.4 V

Off-state output current

(3-state mode)

PE at 2 V,

TE at 0.8 V

µA

−20

Input current at maximum

input voltage

Terminal V = 5.5 V

0.2

0.1

100

High-level input current

Low-level input current

Terminal V = 2.7 V

µA

Terminal V = 0.5 V

−10 −100

−35 −75

Terminal

Bus

−15

−25

Short-circuit output current

−50 −125

Receivers low and enabled

Drivers low and enabled

100

Supply current

No load

Bus-port capacitance

= 5 V to 0,

V = 0 to 2 V,

I/O

f = 1 MHz

I/O(bus)

†

All typical values are at V

= 5, T = 25°C.

switching characteristics, V

= 5 V, C = 15 pF, T = 25°C (unless otherwise noted)

L A

FROM

(INPUT) (OUTPUT)

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX

UNIT

Propagation delay time, low-to-high-level output

Propagation delay time, high-to-low-level output

Propagation delay time, low-to-high-level output

Propagation delay time, high-to-low-level output

Output enable time to high level

PLH

PHL

PLH

PHL

PZH

PHZ

PZL

PLZ

PZH

PHZ

PZL

PLZ

C = 30 pF,

See Figure 1

Terminal

Bus

= 30 pF,

See Figure 2

Terminal

Output disable time from high level

Output enable time to low level

Bus

See Figure 3

Output disable time from low level

Output enable time to high level

Output disable time from high level

Output enable time to low level

Terminal

See Figure 4

See Figure 5

Output disable time from low level

Output pullup enable time

Output pullup disable time

dis

2−4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇ

ꢈ ꢉꢊꢋꢌꢍꢎ ꢏ ꢁꢏꢐꢋꢌ ꢑꢒ ꢓꢐꢒꢈ ꢀꢏ ꢍꢔꢁ ꢊ ꢏꢐꢕꢋꢉꢏ ꢍꢇꢓ ꢀꢍꢊ ꢐꢋ ꢁꢀ ꢉꢏ ꢔ ꢖꢏ ꢐ

ꢗ

SLLS006A − D2611, OCTOBER 1985 − REVISED FEBRUARY 1993

PARAMETER MEASUREMENT INFORMATION

5 V

3 V

0 V

3 V

200 Ω

D Input

1.5 V

Output

Generator

(see Note A)

PHL

PLH

2.2 V

B Output

480 Ω

1.0 V

50 Ω

= 30 pF

(see Note B)

3 V

TEST CIRCUIT

VOLTAGE WAVEFORMS

Figure 1. Terminal-to-Bus Test Circuit and Voltage Waveforms

3 V

4.3 V

B Input

1.5 V

Output

240 Ω

0 V

PLH

Generator

(see Note A)

PHL

D Output

1.5 V

3 kΩ

= 30 pF

(see Note B)

50 Ω

TEST CIRCUIT

VOLTAGE WAVEFORMS

Figure 2. Bus-to-Terminal Test Circuit and Voltage Waveforms

5 V

3 V

200 Ω

3 V

0 V

Output

TE Input

B Output

S1 to 3 V

S2 Open

1.5 V

PZH PHZ

90%

480 Ω

2 V

0.8 V

3.5 V

= 15 pF

PZL

PLZ

(see Note B)

B Output

S1 to GND

S2 Closed

1.0 V

Generator

(see Note A)

0.5 V

50 Ω

TEST CIRCUIT

VOLTAGE WAVEFORMS

Figure 3. TE-to-Bus Test Circuit and Voltage Waveforms

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t ≤ 6 ns, t ≤ 6 ns,

= 50 Ω.

B. C includes probe and jig capacitance.

2−5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ

ꢈꢉ ꢊꢋ ꢌꢍ ꢎꢏꢁ ꢏ ꢐꢋ ꢌꢑꢒ ꢓꢐꢒ ꢈ ꢀꢏ ꢍ ꢔ ꢁꢊ ꢏꢐꢕꢋꢉꢏ ꢍꢇꢓ ꢀꢍꢊ ꢐꢋ ꢁꢀꢉꢏ ꢔꢖꢏ ꢐ

ꢗ

SLLS006A − D2611, OCTOBER 1985 − REVISED FEBRUARY 1993

PARAMETER MEASUREMENT INFORMATION

4.3 V

3 V

0 V

1.5 V

50 Ω

1.5 V

Generator

(see Note A)

TE Input

PZH

PHZ

PLZ

Output

240 Ω

D Output

S1 to 3 V

S2 Open

90%

1.5 V

1.0 V

0 V

4 V

PZL

3 kΩ

= 15 pF

(see Note B)

3 V

D Output

S1 to GND

S2 Closed

0.7 V

VOLTAGE WAVEFORMS

TEST CIRCUIT

Figure 4. TE-to-Terminal Test Circuit and Voltage Waveforms

Generator

(see Note A)

3 V

PE Input

1.5 V

0 V

Output

dis

B Output

50 Ω

= 480 Ω

90%

2 V

= 0.8 V

= 15 pF

(see Note B)

3 V

VOLTAGE WAVEFORMS

TEST CIRCUIT

Figure 5. PE-to-Bus Pullup Test Circuit and Voltage Waveforms

NOTES: C. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t ≤ 6 ns, t ≤ 6 ns,

= 50 Ω.

D. C includes probe and jig capacitance.

2−6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇ

ꢈ ꢉꢊꢋꢌꢍꢎ ꢏ ꢁꢏꢐꢋꢌ ꢑꢒ ꢓꢐꢒꢈ ꢀꢏ ꢍꢔꢁ ꢊ ꢏꢐꢕꢋꢉꢏ ꢍꢇꢓ ꢀꢍꢊ ꢐꢋ ꢁꢀ ꢉꢏ ꢔ ꢖꢏ ꢐ

ꢗ

SLLS006A − D2611, OCTOBER 1985 − REVISED FEBRUARY 1993

TYPICAL CHARACTERISTICS

TERMINAL HIGH-LEVEL OUTPUT VOLTAGE

TERMINAL LOW-LEVEL OUTPUT VOLTAGE

HIGH-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT CURRENT

3.5

0.6

0.5

0.4

0.3

0.2

0.1

= 5 V

= 25°C

2.5

1.5

0.5

−5 −10 −15 −20 −25 −30 −35 −40

− Low-Level Output Current − mA

− High-Level Output Current − mA

Figure 6

Figure 7

TERMINAL OUTPUT VOLTAGE

BUS INPUT VOLTAGE

3.5

= 5 V

No Load

= 25°C

2.5

T−

T+

1.5

0.5

0.2 0.4 0.6 0.8

1.2 1.4 1.6 1.8

V − Input Voltage − V

Figure 8

2−7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ

ꢈꢉ ꢊꢋ ꢌꢍ ꢎꢏꢁ ꢏ ꢐꢋ ꢌꢑꢒ ꢓꢐꢒ ꢈ ꢀꢏ ꢍ ꢔ ꢁꢊ ꢏꢐꢕꢋꢉꢏ ꢍꢇꢓ ꢀꢍꢊ ꢐꢋ ꢁꢀꢉꢏ ꢔꢖꢏ ꢐ

ꢗ

SLLS006A − D2611, OCTOBER 1985 − REVISED FEBRUARY 1993

TYPICAL CHARACTERISTICS

BUS HIGH-LEVEL OUTPUT VOLTAGE

BUS LOW-LEVEL OUTPUT VOLTAGE

HIGH-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT CURRENT

0.6

0.5

0.4

0.3

0.2

0.1

= 5 V

T = 25°C

= 25°C

10 20 30 40 50 60 70 80 90 100

−10

−20

−30

−40

−50

−60

− Low-Level Output Current − mA

− High-Level Output Current − mA

Figure 9

Figure 10

BUS OUTPUT VOLTAGE

THERMAL INPUT VOLTAGE

= 5 V

No Load

= 25°C

0.9

1.1

1.2

1.3

1.4

1.5

1.6

1.7

V − Input Voltage − V

Figure 11

2−8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

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SN75163BDW [TI]

相关型号：

SN75163BDW-00

SN75163BDW-00R

SN75163BJ-00

SN75163BN

SN75163BN-00

SN75163BN-10

SN75164B

SN75164BDW-00R

SN75164BN

SN75164BN-00

SN75164BN-10

SN75164BN3