SN75173NE4 [TI]
QUADRUPLE DIFFERENTIAL LINE RECEVERS; 四路差动线路RECEVERS
| 型号： | SN75173NE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUADRUPLE DIFFERENTIAL LINE RECEVERS |
| 文件： | 总18页 (文件大小：474K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
SN55173 . . . J PACKAGE
SN65173, SN75173 . . . D OR N PACKAGE
(TOP VIEW)
Meet or Exceed the Requirements of
TIA/EIA-422-B, TIA/EIA-423-B, and
TIA/EIA-485-A and ITU Recommendations
V.10, V.11, X.26, and X.27
1B
1A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Designed for Multipoint Bus Transmission
on Long Bus Lines in Noisy Environments
4B
4A
4Y
G
1Y
3-State Outputs
G
2Y
Common-Mode Input Voltage Range of
–12 V to 12 V
2A
3Y
3A
3B
2B
Input Sensitivity . . . ±200 mV
Input Hysteresis . . . 50 mV Typ
High Input Impedance . . . 12 kΩ Min
Operate From Single 5-V Supply
Low Power Requirements
GND
SN55173 . . . FK PACKAGE
(TOP VIEW)
Pin-to-Pin Replacement for AM26LS32
description
3
2
1
20 19
18
4A
4Y
NC
G
1Y
G
4
5
6
7
8
17
16
15
14
The SN55173, SN65173, and SN75173 are
monolithic quadruple differential line receivers
with 3-state outputs. They are designed to meet
NC
2Y
2A
3Y
the
requirements
of
TIA/EIA-422-B,
9 10 11 12 13
TIA/EIA-423-B, TIA/EIA-485-A, and several ITU
recommendations. The standards are for
balanced multipoint bus transmission at rates up
to 10 megabits per second. The four receivers
share two OR enable inputs, one active when
high, the other active when low. These devices
feature high input impedance, input hysteresis for
increased noise immunity, and input sensitivity of
±200 mV over a common-mode input voltage
range of –12 V to 12 V. Fail-safe design specifies
thatiftheinputsareopencircuited, theoutputsare
always high. The SN65173 and SN75173 are
designed for optimum performance when used
with the SN75172 or SN75174 quad differential
line drivers.
NC–No internal connection
THE SN55173 IS NOT RECOMMENDED
FOR NEW DESIGNS.
The SN55173 is characterized over the full military temperature range of –55°C to 125°C. The SN65173 is
characterized for operation from –40°C to 85°C. The SN75173 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
AVAILABLE OPTIONS
PACKAGED DEVICES
PLASTIC
SMALL OUTLINE
(D)
PLASTIC
CHIP CARRIER
(FK)
T
A
CERAMIC DIP
(J)
PLASTIC DIP
(N)
0°C to 70°C
–40°C to 85°C
–55°C to 125°C
SN75173D
SN65173D
—
—
—
—
—
SN75173N
SN65173N
—
SN55173FK
SN55173J
The D package is available taped and reeled. Add the suffix R to the device type (e.g., SN75173DR).
FUNCTION TABLE
(each receiver)
ENABLES
DIFFERENTIAL
A–B
OUTPUT
Y
G
H
X
H
X
H
X
L
G
X
L
H
H
?
V
ID
≥ 0.2 V
X
L
–0.2 V < V < 0.2 V
ID
?
X
L
L
V
ID
≤ –0.2 V
L
X
H
L
Z
H
H
X
H
Open circuit
X
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
†
logic symbol
4
≥ 1
G
G
12
EN
2
3
1A
1B
2A
2B
3A
3B
4A
4B
1Y
1
6
5
11
13
7
2Y
3Y
4Y
10
9
14
15
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
logic diagram (positive logic)
4
G
G
12
2
1
1A
1B
3
1Y
6
7
2A
2B
5
2Y
10
9
3A
3B
11
3Y
14
15
4A
4B
13
4Y
Pin numbers shown are for the D, J, and N packages.
schematics of inputs and outputs
EQUIVALENT OF EACH A OR B INPUT
EQUIVALENT OF G OR G INPUT
TYPICAL OF ALL OUTPUTS
V
V
V
CC
CC
CC
85 Ω
NOM
8.3 kΩ
NOM
100 kΩ
NOM
A Pins Only
960 Ω
NOM
20 kΩ
NOM
Input
Input
Output
960 Ω
NOM
100 kΩ
NOM
B Pins Only
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (V or B inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
I
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
ID
Enable input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Low-level output current, I
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OL
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Case temperature for 60 seconds, T : FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential input voltage, are with respect to network ground terminal.
2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.
3. The package thermal impedance is calculated in accordance with JESD 51.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING
FACTOR
T
= 70°C
T = 125°C
A
A
A
PACKAGE
POWER RATING
POWER RATING POWER RATING
FK
J
1375 mW
11 mW/°C
11 mW/°C
880 mW
880 mW
275 mW
275 mW
1375 mW
recommended operating conditions
MIN NOM
MAX
5.5
UNIT
V
SN55173
4.5
5
5
Supply voltage, V
CC
SN65173, SN75173
4.75
5.25
±12
±12
V
Common-mode input voltage, V
IC
V
Differential input voltage, V
ID
V
High-level enable-input voltage, V
IH
2
V
Low-level enable-input voltage, V
IL
0.8
–400
16
V
High-level output current, I
µA
mA
OH
Low-level output current, I
OL
SN55173
SN65173
SN75173
–55
–40
0
125
85
Operating free-air temperature, T
°C
A
70
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
IT+
V
IT–
V
hys
V
IK
Positive-going input threshold voltage
Negative-going input threshold voltage
V
V
= 2.7 V,
= 0.5 V,
I
I
= –0.4 mA
= 16 mA
0.2
O
O
‡
–0.2
V
O
O
Hysteresis (V
IT+
– V
)
See Figure 4
I = –18 mA
50
mV
V
IT–
Enable-input clamp voltage
–1.5
I
SN55173
2.5
2.7
V
V
OH
High-level output voltage
V
ID
= 200 mV,
I
= –400 µA
SN65173,
SN75173
OH
V
I
I
= 8 mA
0.45
0.5
OL
V
Low-level output voltage
High-impedance-state output current
Line input current
V
V
= –200 mV,
See Figure 1
See Note 3
V
OL
ID
= 16 mA
OL
I
I
= 0.4 V to 2.4 V
±20
1
µA
mA
OZ
O
V = 12 V
I
Other input at 0 V,
I
V = –7 V
–0.8
20
I
I
I
High-level enable-input current
Low-level enable-input current
Input resistance
V
V
= 2.7 V
= 0.4 V
µA
µA
IH
IH
–100
IL
IL
r
12
kΩ
mA
mA
i
I
I
Short-circuit output current
Supply current
–15
–85
70
OS
Outputs disabled
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
Thealgebraicconvention, inwhichthelesspositive(morenegative)limitisdesignatedasminimum, isusedinthisdatasheetforthresholdvoltage
levels only.
NOTE 3: Refer to TIA/EIA-422-B and TIA/EIA-423-B for exact conditions.
switching characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
MIN
TYP
20
MAX
35
UNIT
ns
t
t
t
t
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Output enable time to high level
PLH
PHL
PZH
PZL
PHZ
PLZ
V
C
= –1.5 V to 1.5 V,
ID
L
= 15 pF,
See Figure 1
22
35
ns
C
C
C
C
= 15 pF,
= 15 pF,
= 5 pF,
= 5 pF,
See Figure 2
See Figure 3
See Figure 2
See Figure 3
17
22
ns
L
L
L
L
Output enable time to low level
20
25
ns
Output disable time from high level
Output disable time from low level
21
30
ns
30
40
ns
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
Generator
(see Note B)
1.5 V
[2.5 V]
†
50 Ω
Output
= 15 pF
Input
0 V
0 V
– 1.5 V
[–2.5 V]
†
C
L
t
t
PHL
PLH
(see Note A)
V
OH
OL
Output
1.3 V
1.3 V
V
2 V
VOLTAGE WAVEFORMS
TEST CIRCUIT
†
Voltage for the SN55173 only.
NOTES: A.
C includes probe and jig capacitance.
L
B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, t ≤ 6 ns, t ≤ 6 ns,
r
f
Z
O
= 50 Ω.
Figure 1. t
, t
Test Circuit and Voltage Waveforms
PLH PHL
V
CC
Output
2 kΩ
1.5 V
[2.5 V]
S1
3 V
0 V
†
Input
1.3 V
1.3 V
C
L
(see Note A)
t
t
PHZ
PZH
5 kΩ
0.5 V
(see Note C)
V
OH
Output
S1 Open
S1 Closed
1.3 V
2 V
≈1.4 V
≈0 V
Generator
(see Note B)
(see Note D)
50 Ω
VOLTAGE WAVEFORMS
TEST CIRCUIT
†
Voltage for the SN55173 only.
NOTES: A.
C includes probe and jig capacitance.
L
B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, t ≤ 6 ns, t ≤ 6 ns,
r
f
Z
= 50 Ω.
O
C. All diodes are 1N916, or equivalent.
D. To test the active-low enable G, ground G and apply an inverted input waveform to G.
Figure 2. t
, t
Test Circuit and Voltage Waveforms
PHZ PZH
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
V
CC
2 kΩ
–2.5 V
3 V
0 V
Input
1.3 V
1.3 V
C
L
(see Note A)
5 kΩ
t
t
PZL
PLZ
S2 Closed
≈ 1.4 V
(see Note C)
S2 Open
Output
1.3 V
2 V
Generator
(see Note B)
V
OL
(see Note D)
50 Ω
S2
0.5 V
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A.
C includes probe and jig capacitance.
L
B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, t ≤ 6 ns, t ≤ 6 ns,
r
f
Z
= 50 Ω.
O
C. All diodes are 1N916, or equivalent.
D. To test the active-low enable G, ground G and apply an inverted input waveform to G.
Figure 3. t
, t
Test Circuit and Voltage Waveforms
PZL PLZ
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
†
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
HIGH-LEVEL OUTPUT CURRENT
5
4.5
4
5
4.5
4
V
T
A
= 0.2 V
= 25°C
V
CC
= 5 V
I
O
= 0
T = 25°C
A
ID
V
IC
=
12 V
V
0
=
V
–12 V
=
IC
IC
3.5
3
3.5
3
V
CC
= 5.5 V
V
IT–
V
V
IT–
IT–
2.5
2
2.5
2
V
CC
= 5 V
V
IT+
V
IT+
V
IT+
1.5
1.5
1
0.5
0
1
0.5
0
V
= 4.5 V
CC
–125 –100 – 75 – 50 – 25
0
25 50 75 100 125
0
– 5 –10 –15 –20 –25 –30 –35 – 40 – 45 – 50
V
ID
– Differential Input Voltage – mV
I
– High-Level Output Current – mA
OH
Figure 4
Figure 5
†
Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
†
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATURE
0.6
0.5
0.4
0.3
0.2
0.1
0
5
4.5
4
V
T
= 5 V
= 25°C
V
V
= 5 V
= 0.2 V
= –400 µA
CC
A
CC
ID
I
OH
3.5
3
2.5
2
1.5
1
0.5
0
0
5
10
15
20
25
30
0
10
20
30 40
50
60
70
80 90
I
– Low-Level Output Current – mA
T
A
– Free-Air Temperature – °C
OL
Figure 6
Figure 7
OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
ENABLE G VOLTAGE
FREE-AIR TEMPERATURE
5
0.5
0.4
V
= 0.2 V
ID
Load = 8 kΩ to GND
V
V
I
= 5 V
= –0.2 V
= 8 mA
CC
ID
OL
4.5
T
A
= 25°C
V
V
= 5.5 V
= 5 V
CC
4
CC
3.5
V
CC
= 4.5 V
3
2.5
2
0.3
0.2
SN65173 only
1.5
1
0.5
0
0.1
0
0
0.5
1
1.5
2
2.5
3
0
10
20
30 40
50
60
70
80 90
V – Enable G Voltage – V
I
T
A
– Free-Air Temperature – °C
Figure 8
Figure 9
†
Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
INPUT CURRENT
vs
ENABLE G VOLTAGE
INPUT VOLTAGE
6
5
4
3
2
1
0
1
0.75
0.5
V
= –0.2 V
ID
Load = 1 kΩ to V
V
T
A
= 5 V
CC
= 25°C
V
= 5.5 V
= 5 V
CC
CC
T
A
= 25°C
V
CC
V
CC
= 4.5 V
0.25
0
–0.25
–0.5
The Unshaded Area
Conforms to
Figure 3.2 of
TIA/EIA-485-A
–0.75
–1
0
0.5
1
1.5
2
2.5
3
– 8 – 6 – 4 – 2
0
2
4
6
8
10 12
V – Enable G Voltage – V
I
V – Input Voltage – V
I
Figure 10
Figure 11
APPLICATION INFORMATION
1/4 SN75172
1/4 SN75175
1/4 SN75174
1/4 SN75173
Up to 32
Driver/Receiver
Pairs
1/4 SN75172 1/4 SN75173
1/4 SN75173 1/4 SN75174
NOTE A: The line should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short as
possible.
Figure 12. Typical Application Circuit
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
SOIC
SOIC
PDIP
SOIC
Drawing
SN55173J
SN65173D
SN65173DR
SN65173N
SN75173D
ACTIVE
OBSOLETE
OBSOLETE
OBSOLETE
ACTIVE
J
16
16
16
16
16
1
TBD
TBD
TBD
TBD
A42 SNPB
Call TI
N / A for Pkg Type
Call TI
D
D
N
D
Call TI
Call TI
Call TI
Call TI
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75173DE4
SN75173DR
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
D
D
D
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75173DRE4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75173J
SN75173N
OBSOLETE
ACTIVE
CDIP
PDIP
J
16
16
TBD
Call TI
Call TI
N
25
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN75173NE4
SN75173NSR
SN75173NSRE4
ACTIVE
ACTIVE
ACTIVE
PDIP
SO
N
16
16
16
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
NS
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ55173FK
SNJ55173J
ACTIVE
ACTIVE
LCCC
CDIP
FK
J
20
16
1
1
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
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