SN75176ADRG4_技术文档

SN75176A

DIFFERENTIAL BUS TRANSCEIVER

SLLS100A – JUNE 1984 – REVISED MAY 1995

D OR P PACKAGE

(TOP VIEW)

Bidirectional Transceiver

Meets or Exceeds the Requirements of

ANSI Standards EIA/TIA-422-B and ITU

Recommendation V.11

R

RE

DE

D

V

B

A

1

2

3

4

8

7

6

5

CC

Designed for Multipoint Transmission on

Long Bus Lines in Noisy Environments

GND

3-State Driver and Receiver Outputs

Individual Driver and Receiver Enables

Wide Positive and Negative Input/Output

Bus Voltage Ranges

Driver Output Capability . . . ±60 mA Max

Thermal-Shutdown Protection

Driver Positive- and Negative-Current

Limiting

Receiver Input Impedance . . . 12 kΩ Min

Receiver Input Sensitivity . . . ±200 mV

Receiver Input Hysteresis . . . 50 mV Typ

Operates From Single 5-V Supply

Low Power Requirements

description

The SN75176A differential bus transceiver is a monolithic integrated circuit designed for bidirectional data

communication on multipoint bus-transmission lines. It is designed for balanced transmission lines and meets

ANSI Standard EIA/TIA-422-B and ITU Recommendation V.11.

The SN75176A combines a 3-state differential line driver and a differential input line receiver, both of which

operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables,

respectively, that can be externally connected together to function as a direction control. The driver differential

outputs and the receiver differential inputs are connected internally to form differential input/output (I/O) bus

ports that are designed to offer minimum loading to the bus whenever the driver is disabled or V

= 0. These

CC

ports feature wide positive and negative common-mode voltage ranges making the device suitable for party-line

applications.

The driver is designed to handle loads up to 60 mA of sink or source current. The driver features positive- and

negative-current limiting and thermal shutdown for protection from line fault conditions. Thermal shutdown is

designed to occur at a junction temperature of approximately 150°C. The receiver features a minimum input

impedance of 12 kΩ, an input sensitivity of ±200 mV, and a typical input hysteresis of 50 mV.

The SN75176A can be used in transmission-line applications employing the SN75172 and SN75174 quadruple

differential line drivers and SN75173 and SN75175 quadruple differential line receivers.

The SN75176A is characterized for operation from 0°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

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SN75176A

DIFFERENTIAL BUS TRANSCEIVER

SLLS100A – JUNE 1984 – REVISED MAY 1995

Function Tables

DRIVER

OUTPUTS

INPUT

D

ENABLE

DE

A

H

L

B

L

H

L

H

L

H

Z

X

Z

RECEIVER

DIFFERENTIAL INPUTS

A – B

ENABLE

RE

OUTPUT

R

V

≥ 0.2 V

L

H

L

H

?

L

Z

?

ID

–0.2 V < V < 0.2 V

ID

V

ID

≤ –0.2 V

X

Open

H = high level, L = low level, ? = indeterminate,

X = irrelevant, Z = high impedance (off)

†

logic symbol

logic diagram (positive logic)

3

4

3

DE

D

EN1

EN2

2

RE

2

1

6

7

RE

R

A

B

4

1

6

7

A

B

D

Bus

1

R

2

†

This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.

2

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SN75176A

DIFFERENTIAL BUS TRANSCEIVER

SLLS100A – JUNE 1984 – REVISED MAY 1995

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT

TYPICAL OF A AND B I/O PORTS

TYPICAL OF RECEIVER OUTPUT

V

CC

V

CC

85 Ω

NOM

R

(eq)

960 Ω

NOM

16.8 kΩ

NOM

Input

960 Ω

NOM

Output

GND

Driver input: R

(eq)

= 3 kΩ NOM

= 8 kΩ NOM

Input/Output

Port

Enable inputs: R

(eq)

R

= equivalent resistor

(eq)

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

CC

Voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 V to 15 V

Enable input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

I

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Operating free-air temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.

DISSIPATION RATING TABLE

T

≤ 25°C

DERATING FACTOR

T

= 70 C

T = 105 C

A

PACKAGE

POWER RATING

ABOVE T = 25°C

POWER RATING POWER RATING

A

D

P

725 mW

5.8 mW/°C

8.8 mW/°C

464 mW

704 mW

261 mW

396 mW

1100 mW

3

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SN75176A

DIFFERENTIAL BUS TRANSCEIVER

SLLS100A – JUNE 1984 – REVISED MAY 1995

recommended operating conditions

MIN

4.75

–7

TYP

MAX

5.25

12

UNIT

V

Supply voltage, V

5

CC

Voltage at any bus terminal (separately or common mode), V or V

V

I

IC

High-level input voltage, V

D, DE, and RE

2

V

IH

Low-level input voltage, V

0.8

±12

–60

–400

60

V

IL

Differential input voltage, V (see Note 2)

ID

V

Driver

mA

µA

High-level output current, I

OH

Receiver

Driver

Low-level output current, I

mA

OL

Receiver

8

Operating free-air temperature, T

0

70

°C

A

NOTE 2: Differential-input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.

4

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SN75176A

DIFFERENTIAL BUS TRANSCEIVER

SLLS100A – JUNE 1984 – REVISED MAY 1995

DRIVER SECTION

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

†

TYP

PARAMETER

Input clamp voltage

TEST CONDITIONS

MIN

MAX

UNIT

V

I = –18 mA

–1.5

V

IK

I

V

= 2 V,

= –33 mA

V

= 0.8 V,

IH

IL

High-level output voltage

3.7

1.1

V

OH

I

OH

V

= 2 V,

= 33 mA

IH

IL

V

OL

Low-level output voltage

Differential output voltage

V

I

OH

|V

|

I

O

= 0

2V

OD2

OD1

OD2

R

= 100 Ω,

= 54 Ω,

See Figure 1

2

2.7

2.4

L

1.5

‡

∆|V

±0.2

V

Change in magnitude of differential output voltage

OD|

R

= 54 Ω or 100 Ω,

L

§

V

OC

Common-mode output voltage

3

See Figure 1

Change in magnitude of common-mode output

voltage

∆|V

|

±0.2

V

OC

‡

V

= 12 V

= – 7 V

1

–0.8

20

Output disabled,

See Note 3

O

I

Output current

mA

O

I

High-level input current

Low-level input current

V = 2.4 V

I

µA

IH

V = 0.4 V

I

–400

–250

250

500

50

IL

V

O

V

O

V

O

= –7 V

I

Short-circuit output current

= V

CC

= 12 V

mA

OS

Outputs enabled

Outputs disabled

35

26

Supply current (total package)

No load

CC

40

†

‡

All typical values are at V

= 5 V and T = 25°C.

A

CC

∆|V

level.

| and ∆|V

| are the changes in magnitude of V

OC OD

and V

respectively, that occur when the input is changed from a high level to a low

OC

OD

§

In ANSI Standard EIA/TIA-422-B, V , which is the average of the two output voltages with respect to GND, is called output offset voltage, V

.

OC OS

NOTE 3: This applies for both power on and off; refer to ANSI Standard EIA/TIA-422-B for exact conditions.

switching characteristics, V

= 5 V, T = 25°C

A

CC

PARAMETER

TEST CONDITIONS

MIN

TYP

40

MAX

60

UNIT

t

Differential-output delay time

ns

d(OD)

t(OD)

PZH

PZL

R

= 60 Ω,

See Figure 3

L

Differential-output transition time

Output enable time to high level

Output enable time to low level

Output disable time from high level

Output disable time from low level

65

95

R

= 110 Ω,

See Figure 4

See Figure 5

See Figure 4

See Figure 5

55

90

L

30

50

85

130

40

PHZ

PLZ

20

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN75176A

DIFFERENTIAL BUS TRANSCEIVER

SLLS100A – JUNE 1984 – REVISED MAY 1995

RECEIVER SECTION

electrical characteristics over recommended ranges of common-mode input voltage, supply

voltage, and operating free-air temperature (unless otherwise noted)

†

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

V

IT+

V

IT–

V

hys

V

IK

Positive-going input threshold voltage

Negative-going input threshold voltage

V

= 2.7 V,

= 0.5 V,

I

= –0.4 mA

= 8 mA

0.2

O

‡

–0.2

I

V

O

Input hysteresis voltage (V

Enable clamp voltage

– V

)

IT–

50

mV

V

IT+

I = –18 mA

I

–1.5

V

= 200 mV,

I

= –400 µA,

ID

See Figure 2

OH

V

OH

V

OL

High-level output voltage

Low-level output voltage

2.7

V

= –200 mV,

= 8 mA,

ID

See Figure 2

OL

0.45

V

I

High-impedance-state output current

Line input current

V

= 0.4 V to 2.4 V

±20

1

µA

mA

OZ

O

V = 12 V

Other input = 0 V,

See Note 3

I

V = –7 V

I

–0.8

20

I

High-level enable input current

Low-level enable input current

Input resistance

V

= 2.7 V

= 0.4 V

µA

kΩ

mA

IH

–100

IL

r

12

i

I

Short-circuit output current

–15

–85

50

OS

Outputs enabled

Outputs disabled

35

26

I

Supply current (total package)

No load

mA

CC

40

†

‡

All typical values are at V

= 5 V, T = 25°C.

A

CC

The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for common-mode

input voltage and threshold voltage levels only.

NOTE 3: This applies for both power on and power off. Refer to ANSI Standard EIA/TIA-422-B for exact conditions.

switching characteristics, V

= 5 V, C = 15 pF, T = 25°C

L A

CC

PARAMETER

TEST CONDITIONS

MIN

TYP

21

MAX

35

UNIT

ns

t

Propagation delay time, low-to-high-level output

PLH

PHL

PZH

PZL

PHZ

PLZ

V

ID

= –1.5 V to 1.5 V, See Figure 6

Propagation delay time, high-to-low-level output

Output enable time to high level

23

35

ns

10

30

ns

See Figure 7

Output enable time to low level

12

30

ns

Output disable time from high level

Output disable time from low level

20

35

ns

17

25

ns

6

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SN75176A

DIFFERENTIAL BUS TRANSCEIVER

SLLS100A – JUNE 1984 – REVISED MAY 1995

PARAMETER MEASUREMENT INFORMATION

R

L

V

ID

2

V

OH

V

OD2

+I

OL

R

–I

OH

L

V

OC

V

OL

0 V

2

Figure 1. Driver V

and V

Figure 2. Receiver V

and V

OL

OD

OC

OH

3 V

0 V

Input

1.5 V

C

= 50 pF

L

(see Note B)

R

= 60 Ω

L

t

d(OD)

Generator

(see Note A)

d(OD)

Output

50 Ω

≈ 2.5 V

90%

Output

t

50%

10%

50%

10%

3 V

C

≈ – 2.5 V

t(OD)

L

t

t(OD)

TEST CIRCUIT

VOLTAGE WAVEFORMS

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, t ≤ 6 ns, t ≤ 6 ns,

r

f

Z

C

= 50 Ω.

O

L

B.

includes probe and jig capacitance.

Figure 3. Driver Test Circuit and Voltage Waveforms

Output

3 V

0 V

S1

Input

1.5 V 1.5 V

0 or 3 V

0.5 V

t

PZH

C

= 50 pF

R

= 110 Ω

L

V

OH

(see Note B)

Generator

(see Note A)

Output

50 Ω

2.3 V

V

off

≈ 0 V

t

PHZ

TEST CIRCUIT

VOLTAGE WAVEFORMS

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, t ≤ 6 ns, t ≤ 6 ns,

r

f

Z

C

= 50 Ω.

O

L

B.

includes probe and jig capacitance.

Figure 4. Driver Test Circuit and Voltage Waveforms

7

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SN75176A

DIFFERENTIAL BUS TRANSCEIVER

SLLS100A – JUNE 1984 – REVISED MAY 1995

5 V

3 V

0 V

Input

1.5 V

R

= 110 Ω

L

S1

Output

3 V or 0

t

PZL

t

PLZ

C

= 50 pF

L

5 V

0.5 V

(see Note B)

Generator

(see Note A)

50 Ω

2.3 V

Output

V

OL

TEST CIRCUIT

VOLTAGE WAVEFORMS

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, t ≤ 6 ns, t ≤ 6 ns,

r

f

Z

C

= 50 Ω.

O

L

B.

includes probe and jig capacitance.

Figure 5. Driver Test Circuit and Voltage Waveforms

3 V

0 V

Input

1.5 V

Output

Generator

(see Note A)

51 Ω

1.5 V

0 V

C

= 15 pF

(see Note B)

L

t

PHL

PLH

V

OH

Output

1.3 V

V

OL

TEST CIRCUIT

VOLTAGE WAVEFORMS

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, t ≤ 6 ns, t ≤ 6 ns,

r

f

Z

C

= 50 Ω.

O

L

B.

includes probe and jig capacitance.

Figure 6. Receiver Test Circuit and Voltage Waveforms

8

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SN75176A

DIFFERENTIAL BUS TRANSCEIVER

SLLS100A – JUNE 1984 – REVISED MAY 1995

S1

1.5 V

S2

2 kΩ

–1.5 V

5 V

1N916 or Equivalent

5 kΩ

CL = 15 pF

(see Note B)

Generator

(see Note A)

50 Ω

S3

TEST CIRCUIT

3 V

Input

1.5 V

S1 to 1.5 V

S1 to –1.5 V

0 V S2 Closed

S3 Open

S2 Open

S3 Closed

0 V

t

PZH

t

PZL

V

OH

≈ 4.5 V

1.5 V

Output

Input

Output

Input

1.5 V

3 V

0 V

V

OL

3 V

S1 to 1.5 V

S2 Closed

S3 Closed

S1 to –1.5 V

S2 Closed

S3 Closed

1.5 V

0 V

t

PHZ

t

PLZ

V

OH

≈ 1.3 V

0.5 V

Output

0.5 V

Output

V

OL

≈ 1.3 V

VOLTAGE WAVEFORMS

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, t ≤ 6 ns, t ≤ 6 ns,

r

f

Z

C

= 50 Ω.

O

L

B.

includes probe and jig capacitance.

Figure 7. Receiver Test Circuit and Voltage Waveforms

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN75176A

DIFFERENTIAL BUS TRANSCEIVER

SLLS100A – JUNE 1984 – REVISED MAY 1995

TYPICAL CHARACTERISTICS

DRIVER

HIGH-LEVEL OUTPUT VOLTAGE

vs

DRIVER

LOW-LEVEL OUTPUT VOLTAGE

vs

HIGH-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT CURRENT

5

4.5

4

5

4.5

4

V

= 5 V

V

= 5 V

CC

T

A

= 25°C

T

= 25°C

A

3.5

3

3.5

3

2.5

2

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

20

40

60

80

100

120

0

–20

OH

–40

–60

–80

–100 –120

I

– High-Level Output Current – mA

I

– Low-Level Output Current – mA

OL

Figure 8

Figure 9

RECEIVER

DRIVER

LOW-LEVEL OUTPUT VOLTAGE

vs

LOW-LEVEL OUTPUT CURRENT

DIFFERENTIAL OUTPUT VOLTAGE

vs

OUTPUT CURRENT

0.6

4

3.5

3

V

T

A

= 5 V

= 25°C

CC

V

T

= 5 V

CC

= 25°C

A

0.5

0.4

0.3

0.2

0.1

0

2.5

2

1.5

1

0.5

0

10 20 30 40 50 60 70 80 90 100

0

5

10

15

20

25

30

I

– Low Level Output Current – mA

I

O

– Output Current – mA

OL

Figure 10

Figure 11

10

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SN75176A

DIFFERENTIAL BUS TRANSCEIVER

SLLS100A – JUNE 1984 – REVISED MAY 1995

TYPICAL CHARACTERISTICS

RECEIVER

LOW-LEVEL OUTPUT VOLTAGE

vs

RECEIVER

OUTPUT VOLTAGE

vs

FREE-AIR TEMPERATURE

ENABLE VOLTAGE

5

4

0.5

0.4

0.3

V

= 5 V

= –0.2 V

= 8 mA

CC

ID

V

= 0.2 V

ID

Load = 8 kΩ to GND

I

OL

T

A

= 25°C

V

= 5.25 V

= 4.75 V

CC

V

CC

= 5 V

3

2

1

0

V

CC

0.2

0.1

0

0.5

1

1.5

2

2.5

3

0

10

20

30

40

50

60

70

80

T

A

– Free-Air Temperature – °C

V – Enable Voltage – V

I

Figure 12

Figure 13

RECEIVER

OUTPUT VOLTAGE

vs

ENABLE VOLTAGE

6

V

= 0.2 V

ID

Load = 1 kΩ to V

V

CC

= 5.25 V

CC

5

4

3

2

1

0

T

= 25°C

A

V

CC

= 4.75 V

V

= 5 V

CC

0

0.5

1

1.5

2

2.5

3

V – Enable Voltage – V

I

Figure 14

11

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SN75176A

DIFFERENTIAL BUS TRANSCEIVER

SLLS100A – JUNE 1984 – REVISED MAY 1995

APPLICATION INFORMATION

SN65176A

R

T

Up to 32

Transceivers

NOTE A: The line should be terminated at both ends in its characteristic impedance (R = Z ). Stub lengths off the main line should be kept

T

O

as short as possible.

Figure 15. Typical Application Circuit

12

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE OPTION ADDENDUM

www.ti.com

23-Apr-2007

PACKAGING INFORMATION

Orderable Device

SN75176AD

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

8

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN75176ADE4

SN75176ADG4

SN75176ADR

SN75176ADRE4

SN75176ADRG4

SN75176AP

SOIC

PDIP

D

P

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

50

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

SN75176APE4

50

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Oct-2007

TAPE AND REEL BOX INFORMATION

Device

Package Pins

Site

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) (mm) Quadrant

(mm)

SN75176ADR

D

8

SITE 27

330

12

6.4

5.2

2.1

8

12

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Oct-2007

Device

Package

Pins

Site

Length (mm) Width (mm) Height (mm)

SN75176ADR

D

8

SITE 27

342.9

336.6

20.64

Pack Materials-Page 2

MECHANICAL DATA

MPDI001A – JANUARY 1995 – REVISED JUNE 1999

P (R-PDIP-T8)

PLASTIC DUAL-IN-LINE

0.400 (10,60)

0.355 (9,02)

8

5

0.260 (6,60)

0.240 (6,10)

1

4

0.070 (1,78) MAX

0.325 (8,26)

0.300 (7,62)

0.020 (0,51) MIN

0.015 (0,38)

Gage Plane

0.200 (5,08) MAX

Seating Plane

0.010 (0,25) NOM

0.125 (3,18) MIN

0.100 (2,54)

0.021 (0,53)

0.430 (10,92)

MAX

0.010 (0,25)

M

0.015 (0,38)

4040082/D 05/98

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001

For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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