SN75176BD [TI]

DIFFERENTIAL BUS TRANSCEIVERS; 差分总线收发器
SN75176BD
型号: SN75176BD
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

DIFFERENTIAL BUS TRANSCEIVERS
差分总线收发器

总线收发器 线路驱动器或接收器 驱动程序和接口 接口集成电路 光电二极管 输出元件 PC
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中文:  中文翻译
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SN65176B, SN75176B  
DIFFERENTIAL BUS TRANSCEIVERS  
SLLS101D – JULY 1985 – REVISED APRIL 2003  
SN65176B . . . D OR P PACKAGE  
SN75176B . . . D, P, OR PS PACKAGE  
(TOP VIEW)  
Bidirectional Transceivers  
Meet or Exceed the Requirements of ANSI  
Standards TIA/EIA-422-B and TIA/EIA-485-A  
and ITU Recommendations V.11 and X.27  
R
RE  
DE  
D
V
B
A
1
2
3
4
8
7
6
5
CC  
Designed for Multipoint Transmission on  
Long Bus Lines in Noisy Environments  
GND  
3-State Driver and Receiver Outputs  
Individual Driver and Receiver Enables  
Wide Positive and Negative Input/Output  
Bus Voltage Ranges  
Driver Output Capability . . . ±60 mA Max  
Thermal Shutdown Protection  
Driver Positive and Negative Current  
Limiting  
Receiver Input Impedance . . . 12 kMin  
Receiver Input Sensitivity . . . ±200 mV  
Receiver Input Hysteresis . . . 50 mV Typ  
Operate From Single 5-V Supply  
description/ordering information  
The SN65176B and SN75176B differential bus transceivers are integrated circuits designed for bidirectional  
data communication on multipoint bus transmission lines. They are designed for balanced transmission lines  
and meet ANSI Standards TIA/EIA-422-B and TIA/EIA-485-A and ITU Recommendations V.11 and X.27.  
The SN65176B and SN75176B combine a 3-state differential line driver and a differential input line receiver,  
both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low  
enables, respectively, that can be connected together externally to function as a direction control. The driver  
differential outputs and the receiver differential inputs are connected internally to form differential input/output  
(I/O) bus ports that are designed to offer minimum loading to the bus when the driver is disabled or V  
= 0.  
CC  
These ports feature wide positive and negative common-mode voltage ranges, making the device suitable for  
party-line applications.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP (P)  
SOIC (D)  
Tube of 50  
Tube of 75  
Reel of 2500  
Reel of 2000  
Tube of 50  
Tube of 75  
Reel of 2500  
SN75176BP  
SN75176BP  
SN75176BD  
SN75176BDR  
SN75176BPSR  
SN65176BP  
SN65176BD  
SN65176BDR  
0°C to 70°C  
75176B  
SOP (PS)  
PDIP (P)  
A176B  
SN65176BP  
–40°C to 105°C  
SOIC (D)  
65176B  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN65176B, SN75176B  
DIFFERENTIAL BUS TRANSCEIVERS  
SLLS101D JULY 1985 REVISED APRIL 2003  
description/ordering information (continued)  
The driver is designed for up to 60 mA of sink or source current. The driver features positive and negative current  
limiting and thermal shutdown for protection from line-fault conditions. Thermal shutdown is designed to occur  
at a junction temperature of approximately 150°C. The receiver features a minimum input impedance of 12 k,  
an input sensitivity of ±200 mV, and a typical input hysteresis of 50 mV.  
The SN65176B and SN75176B can be used in transmission-line applications employing the SN75172 and  
SN75174 quadruple differential line drivers and SN75173 and SN75175 quadruple differential line receivers.  
Function Tables  
DRIVER  
OUTPUTS  
INPUT  
D
ENABLE  
DE  
A
H
L
B
L
H
L
H
H
L
H
Z
X
Z
RECEIVER  
DIFFERENTIAL INPUTS  
ENABLE  
RE  
OUTPUT  
R
AB  
V
0.2 V  
L
L
L
H
L
H
?
L
Z
?
ID  
0.2 V < V < 0.2 V  
ID  
V
ID  
0.2 V  
X
Open  
H = high level, L = low level, ? = indeterminate,  
X = irrelevant, Z = high impedance (off)  
logic diagram (positive logic)  
3
DE  
4
D
2
RE  
6
A
B
1
7
Bus  
R
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN65176B, SN75176B  
DIFFERENTIAL BUS TRANSCEIVERS  
SLLS101D JULY 1985 REVISED APRIL 2003  
schematics of inputs and outputs  
EQUIVALENT OF EACH INPUT  
TYPICAL OF A AND B I/O PORTS  
TYPICAL OF RECEIVER OUTPUT  
V
V
CC  
CC  
V
CC  
85 Ω  
NOM  
R
(eq)  
960 Ω  
NOM  
16.8 kΩ  
NOM  
Input  
960 Ω  
NOM  
Output  
GND  
Driver input: R  
= 3 kNOM  
)= 8 kNOM  
Input/Output  
Port  
(eq)  
Enable inputs: R  
(eq  
R
= Equivalent Resistor  
(eq)  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage, V  
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V  
CC  
Voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V to 15 V  
Enable input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V  
I
Package thermal impedance, θ (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W  
JA  
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85°C/W  
PS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 95°C/W  
Operating virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C  
J
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C  
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C  
stg  
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.  
2. Maximum power dissipation is a function of T (max), θ , and T . The maximum allowable power dissipation at any allowable  
J
JA  
A
ambient temperature is P = (T (max) T )/θ . Operating at the absolute maximum T of 150°C can affect reliability.  
D
J
A
JA  
J
3. The package thermal impedance is calculated in accordance with JESD 51-7.  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN65176B, SN75176B  
DIFFERENTIAL BUS TRANSCEIVERS  
SLLS101D JULY 1985 REVISED APRIL 2003  
recommended operating conditions  
MIN  
TYP  
MAX  
5.25  
12  
UNIT  
V
CC  
Supply voltage  
4.75  
5
V
V or V  
I
Voltage at any bus terminal (separately or common mode)  
V
IC  
7  
V
V
V
High-level input voltage  
D, DE, and RE  
D, DE, and RE  
2
V
V
IH  
Low-level input voltage  
0.8  
±12  
60  
400  
60  
IL  
Differential input voltage (see Note 4)  
V
ID  
Driver  
mA  
µA  
I
I
High-level output current  
Low-level output current  
Operating free-air temperature  
OH  
Receiver  
Driver  
mA  
OL  
Receiver  
SN65176B  
SN75176B  
8
40  
105  
70  
T
A
°C  
0
NOTE 4: Differential input/output bus voltage is measured at the noninverting terminal A, with respect to the inverting terminal B.  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN65176B, SN75176B  
DIFFERENTIAL BUS TRANSCEIVERS  
SLLS101D JULY 1985 REVISED APRIL 2003  
DRIVER SECTION  
electrical characteristics over recommended ranges of supply voltage and operating free-air  
temperature (unless otherwise noted)  
PARAMETER  
Input clamp voltage  
TEST CONDITIONS  
MIN  
TYP  
MAX  
1.5  
6
UNIT  
V
V
I = 18 mA  
V
V
V
IK  
I
Output voltage  
I
= 0  
= 0  
0
O
O
O
|V  
|
|
Differential output voltage  
I
1.5  
3.6  
2.5  
6
OD1  
OD2  
OD3  
1/2 V  
OD1  
R
= 100 Ω,  
= 54 Ω,  
See Figure 1  
See Figure 1  
L
L
or 2  
|V  
Differential output voltage  
Differential output voltage  
V
R
1.5  
1.5  
5
5
V
See Note 5  
V
V
Change in magnitude  
of differential output voltage  
|V  
|
|
R
R
R
= 54 or 100 , See Figure 1  
= 54 or 100 , See Figure 1  
= 54 or 100 , See Figure 1  
±0.2  
OD  
OC  
L
L
L
§
+3  
1  
V
OC  
Common-mode output voltage  
V
V
Change in magnitude  
of common-modeoutput voltage  
|V  
±0.2  
§
V
V
= 12 V  
1
0.8  
20  
Output disabled,  
See Note 6  
O
I
Output current  
mA  
O
= 7 V  
O
I
I
High-level input current  
Low-level input current  
V = 2.4 V  
I
µA  
µA  
IH  
V = 0.4 V  
I
400  
250  
150  
250  
250  
70  
IL  
V
O
V
O
V
O
V
O
= 7 V  
= 0  
I
Short-circuit output current  
mA  
mA  
OS  
CC  
= V  
CC  
= 12 V  
Outputs enabled  
Outputs disabled  
42  
26  
I
Supply current (total package)  
No load  
35  
Thepower-off measurement in ANSI Standard TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs.  
§
All typical values are at V  
= 5 V and T = 25°C.  
CC  
A
|V  
OD  
level.  
| and |V  
| are the changes in magnitude of V  
and V  
, respectively, that occur when the input is changed from a high level to a low  
OC  
OD  
OC  
The minimum V  
with a 100-load is either 1/2 V  
OD1  
or 2 V, whichever is greater.  
OD2  
NOTES: 5. See ANSI Standard TIA/EIA-485-A, Figure 3.5, Test Termination Measurement 2.  
6. This applies for both power on and off; refer to ANSI Standard TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does  
not apply for a combined driver and receiver terminal.  
switching characteristics, V  
= 5 V, R = 110 , T = 25°C (unless otherwise noted)  
CC  
L
A
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
15  
MAX  
22  
UNIT  
ns  
t
t
t
t
t
t
Differential-output delay time  
R
R
= 54 ,  
See Figure 3  
See Figure 3  
d(OD)  
t(OD)  
PZH  
PZL  
L
L
Differential-output transition time  
Output enable time to high level  
Output enable time to low level  
Output disable time from high level  
Output disable time from low level  
= 54 ,  
20  
30  
ns  
See Figure 4  
See Figure 5  
See Figure 4  
See Figure 5  
85  
120  
60  
ns  
40  
ns  
150  
20  
250  
30  
ns  
PHZ  
PLZ  
ns  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN65176B, SN75176B  
DIFFERENTIAL BUS TRANSCEIVERS  
SLLS101D JULY 1985 REVISED APRIL 2003  
SYMBOL EQUIVALENTS  
TIA/EIA-422-B  
DATA-SHEET PARAMETER  
TIA/EIA-485-A  
V
O
V
V
V V  
oa, ob  
oa, ob  
|V  
|V  
|
|
V
V
o
OD1  
o
V (R = 100 )  
V (R = 54 )  
t L  
OD2  
t
L
V (test termination  
t
measurement 2)  
|V  
|
OD3  
|V  
|
|
| |V | |V | |  
| |V |V | |  
t t  
OD  
t
t
V
OC  
|V  
os  
|
|V |  
os  
|V  
|V V  
os os  
|
|V V |  
os os  
OC  
I
|I |, |I  
|
|
OS  
sa sb  
I
O
|I |, |I  
xa xb  
I , I  
ia ib  
RECEIVER SECTION  
electrical characteristics over recommended ranges of common-mode input voltage, supply  
voltage, and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN TYP  
MAX  
UNIT  
V
V
IT+  
V
IT–  
V
hys  
V
IK  
Positive-going input threshold voltage  
Negative-going input threshold voltage  
V
V
= 2.7 V,  
= 0.5 V,  
I
I
= 0.4 mA  
0.2  
O
O
0.2  
= 8 mA  
V
O
O
Input hysteresis voltage (V  
IT+  
V  
)
50  
mV  
V
IT–  
Enable Input clamp voltage  
I = 18 mA  
I
1.5  
V
= 200 mV,  
I
I
= 400 µA,  
ID  
See Figure 2  
OH  
V
OH  
V
OL  
High-level output voltage  
2.7  
V
V
= 200 mV,  
= 8 mA,  
ID  
See Figure 2  
OL  
Low-level output voltage  
0.45  
V
I
High-impedance-state output current  
Line input current  
V
= 0.4 V to 2.4 V  
±20  
µA  
mA  
OZ  
O
V = 12 V  
Other input = 0 V,  
See Note 7  
I
1
0.8  
I
I
V = 7 V  
I
I
I
High-level enable input current  
Low-level enable input current  
Input resistance  
V
V
= 2.7 V  
= 0.4 V  
20  
µA  
µA  
kΩ  
mA  
IH  
IH  
100  
IL  
IL  
r
V = 12 V  
I
12  
I
I
Short-circuit output current  
15  
85  
55  
OS  
Outputs enabled  
Outputs disabled  
42  
26  
I
Supply current (total package)  
No load  
mA  
CC  
35  
All typical values are at V  
= 5 V, T = 25°C.  
A
CC  
The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode  
input voltage and threshold voltage levels only.  
NOTE 7: This applies for both power on and power off. Refer to EIA Standard TIA/EIA-485-A for exact conditions.  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN65176B, SN75176B  
DIFFERENTIAL BUS TRANSCEIVERS  
SLLS101D JULY 1985 REVISED APRIL 2003  
switching characteristics, V  
= 5 V, C = 15 pF, T = 25°C  
L A  
CC  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
21  
MAX  
35  
UNIT  
t
t
t
t
t
t
Propagation delay time, low- to high-level output  
Propagation delay time, high- to low-level output  
Output enable time to high level  
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
V
ID  
= 0 to 3 V, See Figure 6  
ns  
23  
35  
10  
20  
See Figure 7  
See Figure 7  
ns  
ns  
Output enable time to low level  
12  
20  
Output disable time from high level  
Output disable time from low level  
20  
35  
17  
25  
PARAMETER MEASUREMENT INFORMATION  
V
ID  
R
L
V
OH  
2
V
OD2  
+I  
I  
OH  
OL  
R
V
OL  
L
V
OC  
2
Figure 1. Driver V  
and V  
Figure 2. Receiver V  
and V  
OL  
OD  
OC  
OH  
3 V  
0 V  
Input  
1.5 V  
1.5 V  
C
= 50 pF  
L
(see Note A)  
t
t
d(OD)  
d(OD)  
R
= 54 Ω  
L
Generator  
(see Note B)  
Output  
50 Ω  
2.5 V  
90%  
Output  
50%  
10%  
50%  
10%  
2.5 V  
t(OD)  
3 V  
t
t
t(OD)  
TEST CIRCUIT  
VOLTAGE WAVEFORMS  
NOTES: A.  
C
includes probe and jig capacitance.  
L
B. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, t 6 ns, t 6 ns,  
r
f
Z
O
= 50 .  
Figure 3. Driver Test Circuit and Voltage Waveforms  
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN65176B, SN75176B  
DIFFERENTIAL BUS TRANSCEIVERS  
SLLS101D JULY 1985 REVISED APRIL 2003  
PARAMETER MEASUREMENT INFORMATION  
Output  
3 V  
0 V  
S1  
Input  
t
1.5 V 1.5 V  
0 V or 3 V  
0.5 V  
C
= 50 pF  
L
PZH  
R
= 110 Ω  
L
(see Note A)  
V
OH  
0 V  
Generator  
(see Note B)  
Output  
50 Ω  
2.3 V  
V
t
off  
PHZ  
TEST CIRCUIT  
VOLTAGE WAVEFORMS  
NOTES: A.  
C includes probe and jig capacitance.  
L
B. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, t 6 ns, t 6 ns,  
r
f
Z
O
= 50 .  
Figure 4. Driver Test Circuit and Voltage Waveforms  
5 V  
3 V  
0 V  
R
= 110 Ω  
Input  
t
L
1.5 V  
1.5 V  
S1  
Output  
3 V or 0 V  
C
= 50 pF  
(see Note A)  
t
L
PZL  
PLZ  
Generator  
(see Note B)  
5 V  
0.5 V  
50 Ω  
2.3 V  
Output  
V
OL  
TEST CIRCUIT  
VOLTAGE WAVEFORMS  
NOTES: A.  
C includes probe and jig capacitance.  
L
B. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, t 6 ns, t 6 ns,  
r
f
Z
O
= 50 .  
Figure 5. Driver Test Circuit and Voltage Waveforms  
3 V  
0 V  
Input  
1.5 V  
1.5 V  
Output  
= 15 pF  
Generator  
(see Note B)  
51 Ω  
t
t
PHL  
PLH  
1.5 V  
0 V  
C
L
V
OH  
OL  
(see Note A)  
Output  
1.3 V  
1.3 V  
V
TEST CIRCUIT  
VOLTAGE WAVEFORMS  
NOTES: A.  
C includes probe and jig capacitance.  
L
B. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, t 6 ns, t 6 ns,  
r
f
Z
O
= 50 .  
Figure 6. Receiver Test Circuit and Voltage Waveforms  
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN65176B, SN75176B  
DIFFERENTIAL BUS TRANSCEIVERS  
SLLS101D JULY 1985 REVISED APRIL 2003  
PARAMETER MEASUREMENT INFORMATION  
S1  
1.5 V  
S2  
2 kΩ  
1.5 V  
5 V  
C
= 15 pF  
L
(see Note A)  
1N916 or Equivalent  
5 kΩ  
Generator  
(see Note B)  
50 Ω  
S3  
TEST CIRCUIT  
3 V  
3 V  
Input  
Input  
1.5 V  
1.5 V  
S1 to 1.5 V  
S2 Open  
S3 Closed  
S1 to 1.5 V  
0 V  
0 V S2 Closed  
t
S3 Open  
PZH  
t
PZL  
V
OH  
4.5 V  
1.5 V  
Output  
Input  
Output  
Input  
1.5 V  
0 V  
3 V  
0 V  
V
OL  
3 V  
0 V  
S1 to 1.5 V  
S2 Closed  
S3 Closed  
S1 to 1.5 V  
S2 Closed  
S3 Closed  
1.5 V  
1.5 V  
t
PHZ  
t
PLZ  
V
OH  
1.3 V  
0.5 V  
Output  
Output  
0.5 V  
1.3 V  
V
OL  
VOLTAGE WAVEFORMS  
NOTES: A.  
C includes probe and jig capacitance.  
L
B. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, t 6 ns, t 6 ns,  
r
f
Z
O
= 50 .  
Figure 7. Receiver Test Circuit and Voltage Waveforms  
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN65176B, SN75176B  
DIFFERENTIAL BUS TRANSCEIVERS  
SLLS101D JULY 1985 REVISED APRIL 2003  
TYPICAL CHARACTERISTICS  
DRIVER  
HIGH-LEVEL OUTPUT VOLTAGE  
vs  
DRIVER  
LOW-LEVEL OUTPUT VOLTAGE  
vs  
HIGH-LEVEL OUTPUT CURRENT  
LOW-LEVEL OUTPUT CURRENT  
5
4.5  
4
5
4.5  
4
V
= 5 V  
V
= 5 V  
CC  
CC  
T
A
= 25°C  
T
A
= 25°C  
3.5  
3
3.5  
3
2.5  
2
2.5  
2
1.5  
1
1.5  
1
0.5  
0
0.5  
0
0
20  
40  
60  
80  
100  
120  
0
20  
40  
60  
80  
100 120  
I
High-Level Output Current mA  
I
Low-Level Output Current mA  
OH  
OL  
Figure 8  
Figure 9  
DRIVER  
DIFFERENTIAL OUTPUT VOLTAGE  
vs  
OUTPUT CURRENT  
4
3.5  
3
V
T
A
= 5 V  
CC  
= 25°C  
2.5  
2
1.5  
1
0.5  
0
0
10 20 30 40 50 60 70 80 90 100  
I
O
Output Current mA  
Figure 10  
10  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN65176B, SN75176B  
DIFFERENTIAL BUS TRANSCEIVERS  
SLLS101D JULY 1985 REVISED APRIL 2003  
TYPICAL CHARACTERISTICS  
RECEIVER  
HIGH-LEVEL OUTPUT VOLTAGE  
vs  
RECEIVER  
HIGH-LEVEL OUTPUT VOLTAGE  
vs  
FREE-AIR TEMPERATURE  
5
HIGH-LEVEL OUTPUT CURRENT  
V
V
I
= 5 V  
= 200 mV  
CC  
5
4.5  
ID  
V
T
= 0.2 V  
= 25°C  
ID  
A
= 440 µA  
OH  
4.5  
4
4
3.5  
3.5  
3
2.5  
3
2.5  
2
V
CC  
= 5.25 V  
2
1.5  
V
CC  
= 5 V  
1.5  
1
V
CC  
= 4.75 V  
0.5  
1
0.5  
0
40 20  
0
20  
40  
60  
80  
100 120  
0
T
A
Free-Air Temperature °C  
0
5 10 15 20 25 30 35 40 45 50  
Only the 0°C to 70°C portion of the curve applies to the  
SN75176B.  
I
High-Level Output Current mA  
OH  
Figure 11  
Figure 12  
RECEIVER  
LOW-LEVEL OUTPUT VOLTAGE  
vs  
RECEIVER  
LOW-LEVEL OUTPUT VOLTAGE  
vs  
LOW-LEVEL OUTPUT CURRENT  
FREE-AIR TEMPERATURE  
0.6  
0.6  
V
T
= 5 V  
= 25°C  
V
V
I
= 5 V  
= 200 mV  
= 8 mA  
CC  
A
CC  
ID  
OL  
0.5  
0.4  
0.3  
0.2  
0.1  
0
0.5  
0.4  
0.3  
0.2  
0.1  
0
0
5
10  
15  
20  
25  
30  
40 20  
0
20  
40  
60  
80  
100 120  
I
Low-Level Output Current mA  
T
A
Free-Air Temperature °C  
OL  
Figure 13  
Figure 14  
11  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN65176B, SN75176B  
DIFFERENTIAL BUS TRANSCEIVERS  
SLLS101D JULY 1985 REVISED APRIL 2003  
TYPICAL CHARACTERISTICS  
RECEIVER  
OUTPUT VOLTAGE  
vs  
RECEIVER  
OUTPUT VOLTAGE  
vs  
ENABLE VOLTAGE  
ENABLE VOLTAGE  
5
4
3
2
1
0
6
5
4
3
2
1
0
V
= 0.2 V  
V
= 0.2 V  
ID  
Load = 1 kto V  
ID  
Load = 8 kto GND  
= 25°C  
V
= 5.25 V  
= 4.75 V  
CC  
CC  
T
A
T
A
= 25°C  
V
= 5.25 V  
CC  
V
CC  
V
= 5 V  
CC  
V
CC  
= 5 V  
V
CC  
= 4.75 V  
0
0.5  
1
1.5  
2
2.5  
3
0
0.5  
1
1.5  
2
2.5  
3
V Enable Voltage V  
I
V Enable Voltage V  
I
Figure 15  
Figure 16  
APPLICATION INFORMATION  
SN65176B  
SN75176B  
SN65176B  
SN75176B  
R
R
T
T
Up to 32  
Transceivers  
NOTE A: The line should be terminated at both ends in its characteristic impedance (R = Z ). Stub lengths off the main line should be kept  
T
O
as short as possible.  
Figure 17. Typical Application Circuit  
12  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
17-Oct-2005  
PACKAGING INFORMATION  
Orderable Device  
SN65176BD  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SOIC  
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR  
no Sb/Br)  
SN65176BDE4  
SN65176BDG4  
SN65176BDR  
SN65176BDRE4  
SN65176BDRG4  
SN65176BP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
SO  
D
D
75 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR  
no Sb/Br)  
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
P
50  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
SN65176BPE4  
SN75176BD  
P
50  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
D
75 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR  
no Sb/Br)  
SN75176BDE4  
SN75176BDG4  
SN75176BDR  
SN75176BDRE4  
SN75176BDRG4  
SN75176BP  
D
75 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR  
no Sb/Br)  
D
75 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR  
no Sb/Br)  
P
50  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
SN75176BPE4  
SN75176BPSR  
SN75176BPSRG4  
P
50  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
PS  
PS  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
17-Oct-2005  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
MECHANICAL DATA  
MPDI001A – JANUARY 1995 – REVISED JUNE 1999  
P (R-PDIP-T8)  
PLASTIC DUAL-IN-LINE  
0.400 (10,60)  
0.355 (9,02)  
8
5
0.260 (6,60)  
0.240 (6,10)  
1
4
0.070 (1,78) MAX  
0.325 (8,26)  
0.300 (7,62)  
0.020 (0,51) MIN  
0.015 (0,38)  
Gage Plane  
0.200 (5,08) MAX  
Seating Plane  
0.010 (0,25) NOM  
0.125 (3,18) MIN  
0.100 (2,54)  
0.021 (0,53)  
0.430 (10,92)  
MAX  
0.010 (0,25)  
M
0.015 (0,38)  
4040082/D 05/98  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MS-001  
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
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accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
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www.ti.com/digitalcontrol  
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Copyright 2005, Texas Instruments Incorporated  

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