SN75374D-00R [TI]
0.5A 4 CHANNEL, NAND GATE BASED MOSFET DRIVER, PDSO16;
| 型号： | SN75374D-00R |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 0.5A 4 CHANNEL, NAND GATE BASED MOSFET DRIVER, PDSO16 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总18页 (文件大小：519K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004
D OR N PACKAGE
(TOP VIEW)
D Quadruple Circuits Capable of Driving
High-Capacitance Loads at High Speeds
D Output Supply Voltage Range From 5 V
V
V
1
2
3
4
5
6
7
8
16
15
14
13
CC1
CC2
1Y
to 24 V
4Y
D Low Standby Power Dissipation
4A
1A
1E1
1E2
2A
D V
Supply Maximizes Output Source
Voltage
2E2
CC3
12 2E1
11
10
9
3A
3Y
V
description/ordering information
2Y
GND
CC3
The SN75374 is a quadruple NAND interface
circuit designed to drive power MOSFETs from
TTL inputs. It provides the high current and
voltage necessary to drive large capacitive loads
at high speeds.
The outputs can be switched very close to the V
supply rail when V
is about 3 V higher than V . V
CC2 CC3
CC2
CC3
also can be tied directly to V
when the source voltage requirements are lower.
CC2
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP (N)
SOIC (D)
Tube of 25
Tube of 40
Reel of 2500
SN75374N
SN75374D
SN75374DR
SN75374N
0°C to 70°C
SN75374
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
logic diagram (positive logic)
4
1E1
1E2
5
12
2E1
13
3
2E2
1A
2
7
6
2A
3A
4A
10
15
11
14
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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ꢜ ꢠ ꢝ ꢜꢕ ꢖꢪ ꢘꢗ ꢛ ꢣꢣ ꢡꢛ ꢙ ꢛ ꢚ ꢠ ꢜ ꢠ ꢙ ꢝ ꢥ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004
schematic (each driver)
V
CC1
V
CC3
V
CC2
To Other Drivers
Input A
Enable E1
Output Y
Enable E2
GND
To Other Drivers
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range (see Note 1):V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 25 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 30 V
CC1
CC2
CC3
V
V
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
I
Peak output current, I (t < 10 ms, duty cycle < 50%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
I
w
Package thermal impedance, θ (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Operating virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. Maximum power dissipation is a function of T (max), θ , and T . The maximum allowable power dissipation at any allowable
J
JA
A
ambient temperature is P = (T (max) − T )/θ . Operating at the absolute maximum T of 150°C can affect reliability.
D
J
A
JA
J
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN NOM
MAX
5.25
24
UNIT
V
V
V
V
V
V
V
Supply voltage
4.75
4.75
5
20
24
4
CC1
CC2
CC3
Supply voltage
V
Supply voltage
V
28
V
CC2
0
− V
Voltage difference between supply voltages
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
10
V
CC3 CC2
2
V
IH
IL
0.8
−10
40
V
I
I
mA
mA
°C
OH
OL
T
A
0
70
2
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SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004
electrical characteristics over recommended ranges of V
temperature (unless otherwise noted)
, V
, V
, and operating free-air
CC1 CC2 CC3
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
V
Input clamp voltage
I = −12 mA
−1.5
V
IK
I
−
V
V
V
V
V
V
= V
= V
= V
= V
+ 3 V,
+ 3 V,
V
V
V
V
= 0.8 V,
= 0.8 V,
= 0.8 V,
= 0.8 V,
= 10 mA
= 2 V,
I
I
I
I
= −100 µA
= −10 mA
= −50 µA
= −10 mA
V
V
− 0.3
− 1.3
V
0.1
− 0.9
− 0.7
− 1.8
0.15
CC3
CC3
CC3
CC3
CC2
CC2
CC2
CC2
IL
OH
OH
OH
OH
CC2
CC2
CC2
CC2
CC2
V
V
V
IL
CC2
High-level output voltage
V
OH
,
,
V
− 1
IL
CC2
V
CC2
− 2.5
IL
= 2 V,
I
0.3
0.5
IH
OL
V
V
Low-level output voltage
V
V
OL
= 15 V to 28 V,
V
IH
I
= 40 mA
0.25
CC2
OL
Output clamp-diode
forward voltage
V = 0,
I
I
F
= 20 mA
1.5
1
F
Input current at
maximum input voltage
I
I
V = 5.5 V
I
mA
µA
Any A
Any E
Any A
Any E
40
80
High-level
input current
I
IH
V = 2.4 V
I
−1
−2
−1.6
−3.2
Low-level
input current
I
I
I
I
I
I
I
V = 0.4 V
I
mA
IL
Supply current from
, all outputs high
4
−2.2
2.2
8
0.25
3.5
47
CC1(H)
CC2(H)
CC3(H)
CC1(L)
CC2(L)
CC3(L)
V
CC1
Supply current from
, all outputs high
V
= 5.25 V,
V
= 24 V,
V
V
= 28 V,
CC1
All inputs at 0 V,
CC2
No load
CC3
CC3
mA
V
CC2
Supply current from
, all outputs high
V
CC3
Supply current from
, all outputs low
31
V
CC1
Supply current from
, all outputs low
V
= 5.25 V,
V
= 24 V,
= 28 V,
CC1
All inputs at 5 V,
CC2
No load
2
mA
V
CC2
Supply current from
, all outputs low
16
27
V
CC1
Supply current from
, all outputs high
I
I
0.25
0.5
CC2(H)
V
CC2
Supply current from
, all outputs high
V
= 5.25 V,
V
= 24 V,
V
V
= 24 V,
= 24 V,
CC1
All inputs at 0 V,
CC2
No load
CC3
CC3
mA
mA
CC3(H)
V
CC3
Supply current from
, standby condition
I
I
0.25
0.5
CC2(S)
V
CC2
Supply current from
, standby condition
V
= 0,
V
= 24 V,
CC1
All inputs at 0 V,
CC2
No load
CC3(S)
V
CC3
†
All typical values are at V
conditions.
= 5 V, V
CC2
= 20 V, V
CC3
= 24 V, and T = 25°C, except for V
OH
for which V
and V
are as stated under test
CC1
A
CC2
CC3
switching characteristics, V
= 5 V, V
= 20 V, V
= 24 V, T = 25°C
CC1
CC2
CC3
A
PARAMETER
Delay time, low- to high-level output
Delay time, high- to low-level output
TEST CONDITIONS
MIN
TYP
MAX
30
UNIT
ns
t
t
t
t
t
t
20
10
40
30
20
20
DLH
DHL
PLH
PHL
TLH
THL
20
ns
C
R
= 200 pF,
= 24 Ω,
L
D
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
Transition time, low- to high-level output
10
10
60
ns
50
ns
See Figure 1
30
ns
Transition time, high- to low-level output
30
ns
3
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SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
24 V
20 V
5 V
Input
2.4 V
V
CC1
V
V
CC2
CC3
R
D
Pulse
Generator
(see Note A)
Output
= 200 pF
(see Note B)
C
L
GND
TEST CIRCUIT
≤10 ns
≤10 ns
3 V
0 V
90%
1.5 V
90%
Input
1.5 V
0.5 µs
t
10%
10%
PHL
t
DHL
t
PLH
t
TLH
t
THL
V
V
OH
V
CC2
− 2 V
V
CC2
− 2 V
t
DLH
Output
2 V
2 V
OL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: PRR = 1 MHz, Z ≈ 50 Ω.
O
B.
C includes probe and jig capacitance.
L
Figure 1. Test Circuit and Voltage Waveforms, Each Driver
4
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SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
V
V
CC2
CC2
V
V
= 5 V
= V
CC3
CC1
CC2
= 20 V
V1 = 0.8 V
− 0.5
−0.5
T
= 70°C
= 0°C
A
− 1
− 1.5
− 2
−1
−1.5
−2
T
A
T
= 25°C
A
T
A
= 70°C
T
A
= 0°C
V
V
V
= 5 V
= 20 V
= 24 V
CC1
CC2
CC3
− 2.5
− 3
−2.5
−3
V = 0.8 V
I
− 0.01
− 0.1
− 1
− 10
− 100
−0.01
−0.1
−1
−10
−100
I
− High-Level Output Current − mA
I
− High-Level Output Current − mA
OH
OH
Figure 2
Figure 3
LOW-LEVEL OUTPUT VOLTAGE
vs
VOLTAGE TRANSFER CHARACTERISTICS
LOW-LEVEL OUTPUT CURRENT
0.5
0.4
0.3
0.2
0.1
0
24
20
16
12
8
V
V
V
= 5 V
= 20 V
= 24 V
CC1
CC2
CC3
V = 2 V
I
T
A
= 70°C
T
A
= 0°C
V
V
V
= 5 V
= 20 V
= 24 V
CC1
CC2
CC3
4
T
= 25°C
A
No Load
0
0
0
20
40
60
80
100
0.5
1
1.5
2
2.5
I
− Low-Level Output Current − mA
V − Input Voltage − V
I
OL
Figure 4
Figure 5
5
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SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
LOW- TO HIGH-LEVEL OUTPUT
vs
PROPAGATION DELAY TIME
HIGH- TO LOW-LEVEL OUTPUT
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
250
225
200
175
150
125
100
75
250
225
200
175
150
125
100
75
C
= 4000 pF
L
V
V
V
= 5 V
= 20 V
= 24 V
C
= 4000 pF
= 2000 pF
CC1
CC2
CC3
L
V
V
V
= 5V
= 20V
= 24V
R
= 24 Ω
CC1
CC2
CC3
D
See Figure 1
C
C
= 2000 pF
= 1000 pF
L
L
R = 24 Ω
See Figure 1
D
C
C
L
L
= 1000 pF
= 200 pF
50
50
C
C
= 200 pF
= 50 pF
C
L
L
L
25
0
25
0
C
= 50 pF
L
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 6
Figure 7
PROPAGATION DELAY TIME
PROPAGATION DELAY TIME
LOW-TO HIGH-LEVEL OUTPUT
vs
HIGH- TO LOW-LEVEL OUTPUT
vs
V
SUPPLY VOLTAGE
V
SUPPLY VOLTAGE
CC2
CC2
250
250
225
200
175
150
125
100
75
V
= 5 V
= V
= 24 Ω
= 25°C
CC1
V
V
= 5 V
CC1
V
R
+ 4 V
225
200
175
150
125
100
75
CC3 CC2
= V
+ 4 V
CC3 CC2
C
= 4000 pF
L
D
C = 4000 pF
L
R
T
A
= 24 Ω
= 25°C
D
T
A
See Figure 1
See Figure 1
C
= 2000 pF
C = 2000 pF
L
L
C
= 1000 pF
= 200 pF
L
C
= 1000 pF
L
50
50
C
C
= 50 pF
C
= 200 pF
L
C
= 50 pF
5
L
L
L
25
0
25
0
0
5
10
15
20
25
0
10
15
20
25
V
CC2
− Supply Voltage − V
V
CC2
− Supply Voltage − V
Figure 8
Figure 9
6
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SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
LOW- TO HIGH-LEVEL OUTPUT
vs
PROPAGATION DELAY TIME
HIGH- TO LOW-LEVEL OUTPUT
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
250
225
200
175
150
125
100
75
250
225
200
175
150
125
100
75
V
V
V
T
= 5 V
= 20 V
= 24 V
V
V
V
T
= 5 V
= 20 V
= 24 V
CC1
CC2
CC3
CC1
CC2
CC3
= 25°C
= 25°C
A
A
See Figure 1
See Figure 1
R
R
= 24 Ω
= 10 Ω
R
R
= 24 Ω
= 10 Ω
D
D
D
D
R
= 0
R
= 0
D
D
50
50
25
25
0
0
0
1000
2000
3000
4000
0
1000
C
2000
− Load Capacitance − pF
L
3000
4000
C
− Load Capacitance − pF
L
Figure 10
Figure 11
POWER DISSIPATION (ALL DRIVERS)
vs
FREQUENCY
V
CC1
V
CC2
V
CC3
= 5 V
= 20 V
= 24 V
Input: 3-V Square Wave
(50% duty cycle)
2000
1800
1600
T
= 25°C
A
C
= 600 pF
L
1400
1200
C
= 1000 pF
L
C
= 2000 pF
L
1000
800
600
400
C
= 4000 pF
L
C
= 400 pF
400
L
200
0
10
20
40
70 100
200
1000
f − Frequency − kHz
Figure 12
NOTE: For R = 0, operation with C > 2000 pF violates absolute maximum current rating.
D
L
7
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SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004
THERMAL INFORMATION
power-dissipation precautions
Significant power may be dissipated in the SN75374 driver when charging and discharging high-capacitance
loads over a wide voltage range at high frequencies. Figure 12 shows the power dissipated in a typical SN75374
as a function of frequency and load capacitance. Average power dissipated by this driver is derived from the
equation:
P
= P
+ P
+ P
T(AV)
DC(AV)
C(AV) S(AV)
where P
is the steady-state power dissipation with the output high or low, P
is the power level during
DC(AV)
C(AV)
charging or discharging of the load capacitance, and P
is the power dissipation during switching between
S(AV)
the low and high levels. None of these include energy transferred to the load, and all are averaged over a full
cycle.
The power components per driver channel are:
(
PHtH ) PLtL
+
)
PDC(AV)
T
f
C(AV) [ CV2
c
P
(
PLHtLH ) PHLtHL
+
)
PS(AV)
T
where the times are as defined in Figure 15.
t
LH
t
HL
t
H
t
L
T = 1/f
Figure 13. Output-Voltage Waveform
8
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ꢆ ꢇꢈꢉꢊ ꢇꢋꢌ ꢍ ꢎ ꢏꢀ ꢐꢍꢑ ꢉ ꢊꢒ ꢓ ꢍꢊ
SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004
THERMAL INFORMATION
power-dissipation precautions (continued)
P , P , P , and P are the respective instantaneous levels of power dissipation, and C is the load capacitance.
L
H
LH
HL
V is the voltage across the load capacitance during the charge cycle shown by the equation:
C
V = V
− V
OL
C
OH
P
may be ignored for power calculations at low frequencies.
S(AV)
In the following power calculation, all four channels are operating under identical conditions: f = 0.2 MHz,
= 19.9 V and V = 0.15 V with V = 5 V, V = 20 V, V = 24 V, V = 19.75 V, C = 1000 pF, and the
V
OH
OL
CC1
CC2
S(AV)
CC3
C
duty cycle = 60%. At 0.2 MHz for C < 2000 pF, P
is low, I
is negligible and can be ignored. When the output voltage
L
is negligible and can be ignored.
CC2
On a per-channel basis using data-sheet values,
ǒ4 mAǓ ) 20 Vǒ−2.2 mAǓ ) 24 Vǒ2.2 mA
Ǔ
ƫ
0.6 )
+ ƪ
P
5 V
DC(AV)
4
4
4
ǒ31 mAǓ ) 20 Vǒ0 mAǓ ) 24 Vǒ16 mA
Ǔ
ƫ
0.4
ƪ
5 V
4
4
4
P
= 58.2 mW per channel
DC(AV)
Power during the charging time of the load capacitance is
2
P
= (1000 pF)(19.75 V) (0.2 MHz) = 78 mW per channel
C(AV)
Total power for each driver is:
= 58.2 mW + 78 mW = 136.2 mW
P
T(AV)
The total package power is:
= (136.2)(4) = 544.8 mW
P
T(AV)
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢆꢇ ꢈ ꢉꢊ ꢇ ꢋꢌ ꢍ ꢎ ꢏꢀ ꢐꢍ ꢑ ꢉꢊ ꢒ ꢓꢍ ꢊ
SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
driving power MOSFETs
The drive requirements of power MOSFETs are much lower than comparable bipolar power transistors. The
input impedance of an FET consists of a reverse-biased PN junction that can be described as a large
capacitance in parallel with a very high resistance. For this reason, the commonly used open-collector driver
with a pullup resistor is not satisfactory for high-speed applications. In Figure 14a, an IRF151 power MOSFET
switching an inductive load is driven by an open-collector transistor driver with a 470-Ω pullup resistor. The input
capacitance (C ) specification for an IRF151 is 4000 pF maximum. The resulting long turn-on time, due to the
ISS
product of input capacitance and the pullup resistor, is shown in Figure 14b.
48 V
5 V
M
4
470 Ω
3
2
4
8
IRF151
7
3
5
TLC555
1
0
6
2
1
1/2 SN75447
0
0.5
1
1.5
2
2.5
3
t − Time − µs
(a)
(b)
Figure 14. Power MOSFET Drive Using SN75447
A faster, more efficient drive circuit uses an active pullup, as well as an active pulldown output configuration,
referred to as a totem-pole output. The SN75374 driver provides the high-speed totem-pole drive desired in an
application of this type (see Figure 15a). The resulting faster switching speeds are shown in Figure 15b.
48 V
5 V
M
4
3
2
1
0
4
8
7
3
5
TLC555
IRF151
6
1/4 SN75374
2
1
0
0.5
1
1.5
2
2.5
3
t − Time − µs
(a)
(b)
Figure 15. Power MOSFET Drive Using SN75374
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢂꢅ
ꢆ ꢇꢈꢉꢊ ꢇꢋꢌ ꢍ ꢎ ꢏꢀ ꢐꢍꢑ ꢉ ꢊꢒ ꢓ ꢍꢊ
SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
driving power MOSFETs (continued)
Power MOSFET drivers must be capable of supplying high peak currents to achieve fast switching speeds as
shown by the equation:
VC
+
I
PK
t
r
where C is the capacitive load and t is the desired rise time. V is the voltage that the capacitance is charged
r
to. In the circuit shown in Figure 14a, V is found by the equation:
V = V
− V
OL
OH
Peak current required to maintain a rise time of 100 ns in the circuit of Figure 14a is:
−9
(3 * 0)4(10 )
I
+
+ 120 mA
PK
−9
100(10 )
Circuit capacitance can be ignored because it is very small compared to the input capacitance of the IRF151.
With a V of 5 V and assuming worst-case conditions, the gate drive voltage is 3 V.
CC
For applications in which the full voltage of V
must be supplied to the MOSFET gate, V
should be at least
CC2
CC3
3 V higher than V
.
CC2
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2007
PACKAGING INFORMATION
Orderable Device
SN75374D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75374DE4
SN75374DG4
SN75374DR
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
D
D
D
D
N
N
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75374DRE4
SN75374DRG4
SN75374N
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN75374NE4
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN75374DR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC 16
SPQ
Length (mm) Width (mm) Height (mm)
333.2 345.9 28.6
SN75374DR
D
2500
Pack Materials-Page 2
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