SN75518N-10 [TI]

VACUUM FLUOR DISPLAY DRIVER, PDIP40;
SN75518N-10
型号: SN75518N-10
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

VACUUM FLUOR DISPLAY DRIVER, PDIP40

驱动 信息通信管理 光电二极管 接口集成电路
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ꢀꢁ ꢂꢃ ꢃ ꢄ ꢅ ꢆ ꢇ ꢀꢁ ꢈꢃ ꢃꢄꢅ  
ꢉꢊꢋꢌ ꢌꢍꢇ ꢎ ꢏꢌ ꢐꢑ ꢒꢀꢋꢒ ꢁꢓ ꢇꢔ ꢕꢀꢖꢏ ꢊꢗꢇ ꢔꢑ ꢕ ꢉꢒ ꢑ ꢀ  
SLDS004B − MARCH 1983 − REVISED MAY 1990  
N PACKAGE  
(TOP VIEW)  
Each Device Drives 32 Lines  
60-V Output Voltage Swing Capability  
25-mA Output Source Current Capability  
High-Speed Serially Shifted Data Input  
Latches on All Driver Outputs  
V
V
CC1  
DATA IN  
Q1  
1
40  
39  
38  
37  
36  
CC2  
SERIAL OUT  
Q32  
2
3
Q31  
Q2  
4
description  
Q30  
Q3  
5
Q29  
6
35 Q4  
The SN65518 and SN75518 are monolithic  
BIDFET integrated circuits designed to drive a  
dot matrix or segmented vacuum fluorescent  
display.  
7
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
Q28  
Q5  
8
Q27  
Q6  
9
Q26  
Q7  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
Q25  
Q8  
Each device consists of a 32-bit shift register, 32  
latches, and 32 output AND gates. Serial data is  
entered into the shift register on the low-to-high  
transition of CLOCK. While LATCH ENABLE is  
high, parallel data is transferred to the output  
buffers through a 32-bit latch. Data present in the  
latch during the high-to-low transition of LATCH  
ENABLE is latched. When STROBE is low, all Q  
outputs are enabled. When STROBE is high, all Q  
outputs are low.  
Q24  
Q9  
Q23  
Q10  
Q22  
Q11  
Q21  
Q12  
Q20  
Q13  
Q19  
Q14  
Q18  
Q15  
Q17  
Q16  
STROBE  
GND  
LATCH ENABLE  
CLOCK  
Serial data output from the shift register may be  
used to cascade additional devices. This output is  
not affected by LATCH ENABLE or STROBE.  
FN PACKAGE  
(TOP VIEW)  
The SN65518 is characterized for operation from  
−40°C to 85°C. The SN75518 is characterized for  
operation from 0°C to 70°C.  
6 5  
4
3
2 1 44 43 42 41 40  
Q4  
39  
Q29  
Q28  
Q27  
Q26  
Q25  
Q24  
Q23  
Q22  
Q21  
Q20  
Q19  
7
Q5  
38  
Q6  
37  
8
9
Q7  
36  
10  
11  
12  
13  
14  
15  
16  
17  
Q8  
35  
Q9  
34  
33  
Q10  
32 Q11  
31  
30  
29  
Q12  
Q13  
NC  
18 19 20 21 22 23 24 25 26 27 28  
NC − No internal connection  
BIDFET − Bipolar, double-diffused, N-channel and P-channel MOS transistors on same chip. This is a patented process.  
ꢓꢤ  
Copyright 1990, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
ꢟꢝ  
4−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
ꢀꢁ ꢂ ꢃꢃ ꢄ ꢅ ꢆꢇ ꢀ ꢁꢈ ꢃꢃ ꢄ ꢅ  
ꢉꢊ ꢋ ꢌꢌ ꢍ ꢇꢎ ꢏ ꢌꢐ ꢑꢒ ꢀꢋ ꢒ ꢁꢓ ꢇ ꢔꢕ ꢀꢖ ꢏ ꢊꢗꢇꢔ ꢑꢕꢉ ꢒꢑꢀ  
SLDS004B − MARCH 1983 − REVISED MAY 1990  
logic symbol  
CMOS/VAC  
FLUOR DISP  
19  
EN3  
STROBE  
C2  
LATCH 22  
ENABLE  
SRG32  
C1/→  
21  
CLOCK  
39  
38  
37  
2D  
2D  
3
3
Q1  
Q2  
DATA IN  
23  
18  
Q16  
Q17  
2D  
2D  
3
3
4
Q31  
Q32  
2D  
2D  
3
3
3
2
SERIAL OUT  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Pin numbers shown are for the N package.  
logic diagram (positive logic)  
STROBE  
LATCH  
ENABLE  
Shift  
Register  
Latches  
C2  
DATA IN  
CLOCK  
1D  
C1  
R1  
Q1  
LC1  
2D  
1D  
C1  
C2  
2D  
R2  
R31  
R32  
Q2  
28 Stages  
(Q3 thru Q30)  
Not Shown  
LC2  
1D  
C1  
C2  
2D  
Q31  
LC31  
LC32  
1D  
C1  
C2  
2D  
Q32  
SERIAL OUT  
4−2  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
ꢀꢁꢂ ꢃ ꢃ ꢄ ꢅ ꢆꢇ ꢀ ꢁꢈ ꢃꢃ ꢄꢅ  
ꢉꢊꢋꢌ ꢌꢍꢇ ꢎ ꢏꢌ ꢐꢑ ꢒꢀꢋꢒ ꢁꢓ ꢇꢔ ꢕꢀꢖꢏ ꢊꢗꢇ ꢔꢑ ꢕ ꢉꢒ ꢑ ꢀ  
SLDS004B − MARCH 1983 − REVISED MAY 1990  
FUNCTION TABLE  
CONTROL INPUTS  
LATCH  
OUTPUTS  
SHIFT REGISTERS  
R1 THRU R32  
LATCHES  
LC1 THRU LC32  
FUNCTION  
CLOCK  
STROBE  
SERIAL  
R32  
Q1 THRU Q32  
Determined by STROBE  
Determined by STROBE  
ENABLE  
X
X
X
X
Load and shift  
Determined by  
LATCH ENABLE  
Load  
Latch  
Strobe  
No ↑  
No change  
X
X
L
H
X
X
As determined  
above  
Stored data  
New data  
R32  
X
X
X
X
H
L
As determined  
above  
Determined by  
LATCH ENABLE  
All L  
R32  
LC1 thru LC32, respectively  
H = high level, L = low level, X = irrelevant,  
R32 and the serial output take on the state of R31, R31 takes on the state of R30, ... R2 takes on the state of R1, and R1 takes on the state of  
= low-to-high-level transition.  
the data input.  
New data enter the latches while LATCH ENABLE is high. These data are stored while LATCH ENABLE is low.  
typical operating sequence  
CLOCK  
DATA IN  
Valid  
Irrelevant  
Valid  
SR  
Contents  
Invalid  
LATCH  
ENABLE  
Latch  
Contents  
Previously Stored Data  
New Data Valid  
STROBE  
Valid  
Q Outputs  
4−3  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
ꢀꢁ ꢂ ꢃꢃ ꢄ ꢅ ꢆꢇ ꢀ ꢁꢈ ꢃꢃ ꢄ ꢅ  
ꢉꢊ ꢋ ꢌꢌ ꢍ ꢇꢎ ꢏ ꢌꢐ ꢑꢒ ꢀꢋ ꢒ ꢁꢓ ꢇ ꢔꢕ ꢀꢖ ꢏ ꢊꢗꢇꢔ ꢑꢕꢉ ꢒꢑꢀ  
SLDS004B − MARCH 1983 − REVISED MAY 1990  
schematic of inputs and outputs  
EQUIVALENT OF EACH INPUT  
TYPICAL OF ALL Q OUTPUTS  
TYPICAL OF SERIAL OUTPUT  
V
CC1  
V
CC2  
V
CC1  
Input  
Output  
Output  
GND  
GND  
GND  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage, V  
Supply voltage, V  
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 V  
CC1  
CC2  
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V  
I
CC1  
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table  
Operating free-air temperature range, T : SN65518 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C  
A
SN75518 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C  
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
stg  
Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C  
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . . . . . . . . . . . . 260°C  
NOTE 1: Voltage values are with respect to network ground terminal.  
DISSIPATION RATING TABLE  
T
25°C  
DERATING FACTOR  
T
= 70°C  
T = 85°C  
A
A
A
PACKAGE  
POWER RATING  
ABOVE T = 25°C  
POWER RATING POWER RATING  
A
FN  
N
1700 mW  
13.6 mW/°C  
10.0 mW/°C  
1088 mW  
800 mW  
884 mW  
650 mW  
1250 mW  
4−4  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
ꢀꢁꢂ ꢃ ꢃ ꢄ ꢅ ꢆꢇ ꢀ ꢁꢈ ꢃꢃ ꢄꢅ  
ꢉꢊꢋꢌ ꢌꢍꢇ ꢎ ꢏꢌ ꢐꢑ ꢒꢀꢋꢒ ꢁꢓ ꢇꢔ ꢕꢀꢖꢏ ꢊꢗꢇ ꢔꢑ ꢕ ꢉꢒ ꢑ ꢀ  
SLDS004B − MARCH 1983 − REVISED MAY 1990  
recommended operating conditions, T = 25°C (unless otherwise noted)  
A
MIN  
4.5  
0
MAX  
15  
UNIT  
V
Supply voltage, V  
Supply voltage, V  
CC1  
60  
V
CC2  
V
V
= 4.5 V  
= 15 V  
3.5  
12  
CC1  
High-level input voltage, V  
IH  
(see Figure 1)  
V
CC1  
Low-level input voltage, V (see Figure 1)  
IL  
0.3  
0.8  
25  
2
V
High-level output current, I  
mA  
mA  
OH  
OL  
Low-level output current, I  
V
V
V
V
V
V
V
V
V
V
= 10 V to 15 V  
= 4.5 V  
0
0
5
CC1  
CC1  
CC1  
CC1  
CC1  
CC1  
CC1  
CC1  
CC1  
CC1  
Clock frequency, f  
clock  
(see Figure 2)  
MHz  
ns  
1
= 10 V to 15 V  
= 4.5 V  
100  
500  
100  
500  
75  
Pulse duration, CLOCK high, t  
w(CKH)  
= 10 V to 15 V  
= 4.5 V  
Pulse duration, CLOCK low, t  
ns  
w(CKL)  
= 10 V to 15 V  
= 4.5 V  
Setup time, DATA IN before CLOCK, t  
su  
ns  
150  
75  
= 10 V to 15 V  
= 4.5 V  
Hold time, DATA IN after CLOCK, t  
ns  
h
150  
40  
0
SN65518  
SN75518  
85  
70  
Operating free-air temperature, T  
°C  
A
electrical characteristics over recommended ranges of operating free-air temperature and V  
CC2  
,
CC1  
V
= 60 V (unless otherwise noted)  
PARAMETER  
Input clamp voltage  
Q outputs  
TEST CONDITIONS  
MIN TYP  
MAX  
UNIT  
V
IK  
I = 12 mA  
1.5  
V
I
I
= 25 mA  
57.5  
4.5  
58  
OH  
V
OH  
High-level output voltage  
V
V
SERIAL OUT  
V
CC1  
= 5 V,  
I
= − 20 µA  
4.9  
5
5
OH  
Q outputs  
I
= 1 mA  
OL  
OL  
V
OL  
Low-level output voltage  
SERIAL OUT  
I
= 20 µA  
0.06  
0.1  
0.1  
1.8  
2
0.8  
1
I
I
High-level input current  
Low-level input current  
V
CC1  
V
CC1  
V
CC1  
V
CC1  
= 15 V,  
= 15 V,  
= 4.5 V  
= 15 V  
V = 15 V  
µA  
µA  
IH  
I
V = 0 V  
I
−1  
4
IL  
I
Supply current  
mA  
CC1  
5
SN65518  
Outputs high,  
Outputs high,  
Outputs low  
T
= 40°C  
12  
10  
0.5  
A
I
Supply current  
T = 0°C to MAX  
A
7
mA  
CC2  
SN65518,  
SN75518  
0.01  
All typical values are at T = 25°C.  
A
4−5  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
ꢀꢁ ꢂ ꢃꢃ ꢄ ꢅ ꢆꢇ ꢀ ꢁꢈ ꢃꢃ ꢄ ꢅ  
ꢉꢊ ꢋ ꢌꢌ ꢍ ꢇꢎ ꢏ ꢌꢐ ꢑꢒ ꢀꢋ ꢒ ꢁꢓ ꢇ ꢔꢕ ꢀꢖ ꢏ ꢊꢗꢇꢔ ꢑꢕꢉ ꢒꢑꢀ  
SLDS004B − MARCH 1983 − REVISED MAY 1990  
switching characteristics, V  
= 60 V, C = 50 pF, T = 25°C (unless otherwise noted)  
CC2  
L
A
PARAMETER  
TEST CONDITIONS  
MIN  
MAX  
600  
150  
1.5  
1
UNIT  
V
V
= 4.5 V  
= 15 V  
CC1  
C = 15 pF,  
L
See Figure 4  
t
d
Delay time, CLOCK to DATA OUT  
ns  
CC1  
From LATCH ENABLE  
From STROBE  
See Figure 5  
See Figure 6  
See Figure 5  
See Figure 6  
See Figure 5  
See Figure 6  
See Figure 5  
See Figure 6  
V
V
V
V
= 4.5 V  
= 15 V  
= 4.5 V  
= 15 V  
CC1  
CC1  
CC1  
CC1  
t
Delay time, high-to-low-level Q output  
Delay time, low-to-high-level Q output  
µs  
DHL  
From LATCH ENABLE  
From STROBE  
0.5  
0.5  
1.5  
1
From LATCH ENABLE  
From STROBE  
t
µs  
DLH  
From LATCH ENABLE  
From STROBE  
0.25  
0.25  
3
V
V
V
V
= 4.5 V  
= 15 V  
= 4.5 V  
= 15 V  
CC1  
CC1  
CC1  
CC1  
t
t
Transition time, high-to-low-level Q output  
Transition time, low-to-high-level Q output  
See Figure 6  
See Figure 6  
µs  
µs  
THL  
1.5  
2.5  
0.75  
TLH  
RECOMMENDED OPERATING CONDITIONS  
INPUT VOLTAGE  
vs  
MAXIMUM CLOCK FREQUENCY  
vs  
SUPPLY VOLTAGE V  
SUPPLY VOLTAGE V  
CC1  
CC1  
12  
10  
8
6
5
4
3
2
T
A
= Full Range  
T
A
= Full Range  
Minimum V  
IH  
6
4
2
1
Maximum V  
IL  
0
0
3
5
7
9
11  
13  
15  
4
6
8
10  
12  
14  
16  
Supply Voltage, V  
− V  
Supply Voltage, V  
− V  
CC1  
CC1  
Figure 1  
Figure 2  
4−6  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
ꢀꢁꢂ ꢃ ꢃ ꢄ ꢅ ꢆꢇ ꢀ ꢁꢈ ꢃꢃ ꢄꢅ  
ꢉꢊꢋꢌ ꢌꢍꢇ ꢎ ꢏꢌ ꢐꢑ ꢒꢀꢋꢒ ꢁꢓ ꢇꢔ ꢕꢀꢖꢏ ꢊꢗꢇ ꢔꢑ ꢕ ꢉꢒ ꢑ ꢀ  
SLDS004B − MARCH 1983 − REVISED MAY 1990  
PARAMETER MEASUREMENT INFORMATION  
t
w(CKH)  
t
w(CKH)  
V
IH  
V
IH  
50%  
CLOCK  
CLOCK  
50%  
50%  
V
IL  
V
IL  
t
w(CKL)  
t
d
t
t
h
su  
V
OH  
V
IH  
DATA  
OUTPUT  
50%  
DATA IN  
Valid  
V
OL  
V
IL  
Figure 3. Input Timing Waveforms  
Figure 4. Data Output Switching Times  
3.5 V  
3.5 V  
0 V  
1.75 V  
STROBE  
LATCH  
ENABLE  
50%  
0 V  
or  
t
t
t
t
DHL  
DLH  
DLH  
DHL  
V
V
OH  
OH  
OL  
90%  
10%  
Q Outputs  
90%  
10%  
Q Output  
V
OL  
V
t
THL  
t
TLH  
Figure 5. Q Output Switching Times  
Figure 6. Switching Time Voltage Waveforms  
For testing purposes, all input pulses have maximum rise and fall times of 30 ns.  
4−7  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
4−8  
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