SN75ALS085DWG4 [TI]
LAN Access Unit Interface Dual Driver/Receiver 24-SOIC 0 to 70;
| 型号： | SN75ALS085DWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LAN Access Unit Interface Dual Driver/Receiver 24-SOIC 0 to 70 局域网 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总19页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054D – APRIL 1989 – REVISED OCTOBER 2001
DW OR NT PACKAGE
Meets or Exceeds the Requirements of IOS
8802.3:1989 and ANSI/IEEE Std 802.3-1988
(TOP VIEW)
Interdevice Loopback Paths for System
Testing
TXI1
TXEN1
LOOP1
GND
TXO1
TXO1
1
24
23
22
21
20
2
Squelch Function Implemented on the
Receiver Inputs
V
3
CC
RXI1
RXI1
4
RXEN1
RXO1
RXO2
RXEN2
GND
5
Drives a Balanced 78-Ω Load
6
19 GND
Transformer Coupling Not Required in
System
7
18
17
16
15
14
13
GND
RXI2
RXI2
8
Power-Up/Power-Down Protection (Glitch
Free)
9
10
11
12
LOOP2
TXEN2
TXI2
V
CC
Isolated Ground Pins for Reduced Noise
Coupling
TXO2
TXO2
Fault-Condition Protection Built Into the
Device
Driver Inputs Are Level-Shifted ECL
Compatible
Package Options Include Plastic
Small-Outline (DW) Package and Standard
Plastic (NT) DIP
description
The SN75ALS085 is a high-speed, advanced low-power Schottky, dual-channel driver/receiver device
designed for use in the AUI of ANSI/IEEE Std 802.3-1988. The two drivers on the device drive a 78-Ω balanced,
terminated twisted-pair transmission line up to a maximum length of 50 meters. In the off (idle) state, the drivers
maintain minimal differential output voltage on the twisted-pair line and, at the same time, remain within the
required output common-mode range.
With the driver enable (TXEN) high, upon receiving the first falling edge into the driver input, the differential
outputs rise to full-amplitude output levels within 25 ns. The output amplitude is maintained for the remainder
of the packet. After the last positive packet edge is transmitted into the driver, the driver maintains a minimum
of 70% full differential output for a minimum of 200 ns, then decays to a minimum level for the reset (idle)
condition within 8 µs. Disabling the driver by taking the driver enable low also forces the output into the idle
conditionafterthenormal8-µstimeout. Whileoperating, thedriversareabletowithstandasetoffaultconditions
and not suffer damage due to the faults being applied. The drivers power up in the idle state to ensure that no
activity is placed on the twisted-pair cable, which could be interpreted as network traffic.
The line receiver squelch function interfaces to a differential twisted-pair line terminated external to the device.
The receiver squelch circuit allows differential receive signals to pass through, as long as the input amplitude
and pulse duration are greater than the minimum squelch threshold. This ensures a good signal-to-noise ratio
while the data path is active and prevents system noise from causing false data transitions during line shutdown
and line-idle conditions. The receiver outputs (RXO) default to a high level and the receiver-enable (RXEN)
outputs default to a low level while the squelch function is blocking the data path through the receiver (idle). The
linereceiversquelchbecomesactivewithin50nswhentheinputsquelchthresholdisexceeded. RXENisdriven
high when the squelch circuit allows data to pass through the receiver. The receiver squelch circuit also can
withstand a set of fault conditions while operating, without causing permanent damage to the device.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054D – APRIL 1989 – REVISED OCTOBER 2001
description (continued)
The purpose of the loop functions is to provide a means by which system data-path verification can be done
to isolate faulty interfaces and assist in network diagnosis. The LOOP pins are TTL compatible and must be
held high for normal operation. When LOOP1 is taken low, the output of driver 1 (TXO1) immediately goes into
the idle state. Also, the input to receiver 1 is ignored, and a path from a transmit input (TXI1) to RXO1 is
established. When LOOP1 is taken back high, driver 1 and receiver 1 revert back to their normal operation.
When LOOP2 is taken low, a similar data path is established between TXI1 and RXO2. TXEN1 must be high
for the loop functions to operate, and TXEN1 can be used to gate the loop function if desired. During loop
operation, the respective RXEN reflects the status of TXEN1.
The SN75ALS085 is characterized for operation from 0°C to 70°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
PLASTIC
SMALL OUTLINE
(DW)
T
A
PLASTIC DIP
(NT)
0°C to 70°C
SN75ALS085DW
SN75ALS085NT
The DW package is available taped and reeled. Add the suffix R
to device type (e.g., SN75ALS085DWR).
Function Tables
RECEIVER (LOOP = H)
OUTPUTS
PREVIOUS
RXEN
RXI
RXEN
RXO
H
V
ID
V
ID
V
ID
V
ID
= 1315 mV to –175 mV,
= –275 mV to –1315 mV
= 318 mV to 1315 mV,
= 318 mV to 1315 mV,
t
w
t
w
t
w
t
w
< 25 ns
> 50 ns
< 142 ns
> 187 ns
L
X
H
X
L
H
H
L
L
H
H
H = high level, L = low level, X = don’t care
DRIVER (LOOP = H)
PREVIOUS
OUTPUT
TXI
TXEN
TXO
TXO
Idle
Idle
L
L
L
Idle
H
L
H
Idle
↓
Idle
L
H
Active
Active
Active
Active
Active
Active
Active
Active
L
H < 260 µs
H > 8 µs
L
H
H
H
Idle
Idle
Idle
H
L > 8 µs
L > 8 µs
L < 260 ns
L < 260 ns
L < 260 ns
H < 260 ns
H < 260 ns
H > 8 µs
L
Idle
L
H = V ≥ V max, L = V ≤ V min
I
T
I
T
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054D – APRIL 1989 – REVISED OCTOBER 2001
Function Tables (continued)
LOOP
INPUTS
TXEN1
OUTPUTS
LOOP1
LOOP2
TXI1
RXI1
RXI2
RXO1
RXO2
RXEN1
RXEN2
TXO1
Idle
L
L
L
L
L
H
X
X
L
L
H
H
H
H
X
X
X
X
H
H
H
H
H
L
H
L
Idle
L
L
X
L
Idle
L
H
H
H
L
L
H
X
Normal
Normal
Normal
X
L
Normal
Normal
Normal
L
H
Normal
Normal
Normal
H
Idle
L
H
H
X
H
H
Idle
L
X
L
X
H
L
Idle
H
H
H
H
L
H
H
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Idle
L
H
L
X
H
H
Idle
L
X
X
H
L
Idle
H
Normal
Normal
Normal
Normal
Normal
Normal
H = high level, L = low level, X = don’t care
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054D – APRIL 1989 – REVISED OCTOBER 2001
logic diagram (positive logic)
20
RXI1
RXI1
Noise
Filter
21
5
6
RXEN1
+
–
150 ns
225 mV
RXO1
3
LOOP1
24
23
1
2
TXO1
TXO1
TXI1
ECL/TTL
250 ns
1
1
TXEN1
X1
4 µS
10
LOOP2
7
8
RXO2
17
16
150 ns
RXI2
RXI2
Noise
Filter
RXEN2
+
–
225 mV
14
13
12
TXO2
TXO2
ECL/TTL
TXI2
250 ns
11
1
1
4 µS
TXEN2
X1
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054D – APRIL 1989 – REVISED OCTOBER 2001
schematics of inputs and outputs
RXI and RXI Inputs
LOOP and TXEN Inputs
VCC
V
CC
20 kΩ
4 kΩ
4 kΩ
4 kΩ
4 kΩ
4 kΩ
LOOP,
TXEN
RXI
RXI
ESD
ESD
3 kΩ
ESD
+
1 kΩ
–
TXI Inputs
RXO and RXEN Outputs
V
CC
V
CC
50 Ω
200 Ω
50 kΩ
TXI
ESD
RXO,
5 kΩ
RXEN
ESD
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054D – APRIL 1989 – REVISED OCTOBER 2001
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
CC
TXI and LOOP input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
TXO and TXO output voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V
RXI and RXI input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V
RXO and RXEN output voltage, V
I
O
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
O
Package thermal impedance, θ (see Notes 2 and 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
JA
(see Notes 2 and 4): NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. Maximum power dissipation is a function of T (max), θ , and T . The maximum allowable power dissipation at any allowable
J
JA
A
ambient temperature is P = (T (max) – T )/θ . Operating at the absolute maximum T of 150°C can affect reliability.
D
J
A
JA
J
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-3.
recommended operating conditions
MIN NOM
MAX
5.25
UNIT
V
V
V
V
V
V
Supply voltage
4.75
1
5
CC
Common-mode voltage at RXI inputs
4.2
V
IC
Differential voltage between RXI inputs
±318
2
±1315
mV
V
ID
High-level input voltage, LOOP and TXEN
Low-level input voltage, LOOP and TXEN
IH
0.8
– 0.4
16
V
IL
I
I
t
t
t
t
t
High-level output current, RXO and RXEN
Low-level output voltage, RXO and RXEN
Setup time, driver mode, TXEN high before TXI↓ (see Figure 7)
Setup time, loop mode, LOOP low before TXEN↑ (see Figure 9)
Setup time, loop mode, TXEN high before TXI↓ (see Figure 9)
Hold time, loop mode, TXEN high after TXI↑ (see Figure 8)
Hold time, loop mode, LOOP low after TXEN↓ (see Figure 8)
Operating free-air temperature
mA
mA
ns
ns
ns
ns
ns
°C
OH
OL
su1
su2
su3
h1
10
15
10
10
15
0
h2
T
A
70
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054D – APRIL 1989 – REVISED OCTOBER 2001
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
Clamp voltage at all inputs
TEST CONDITIONS
I = –18 mA
MIN
MAX
UNIT
V
IK
–1.5
V
I
V
V
V
V
V
V
V
V
V
= 4.75 V
= 5 V
3.202 3.752
3.389 3.998
3.577 4.244
3.213 3.797
3.400 4.043
3.588 4.289
3.239 3.849
3.426 4.095
3.614 4.341
–275
CC
CC
CC
CC
CC
CC
CC
CC
CC
T
= 0°C
A
= 5.25 V
= 4.75 V
= 5 V
V
Driver input (TXI) threshold voltage
T
A
= 25°C
= 70°C
V
(TO)
= 5.25 V
= 4.75 V
= 5 V
T
A
= 5.25 V
Receiver differential input threshold voltage
Driver output (TXO) common-mode voltage
mV
V
TXEN at 0.8 V,
LOOP2 at 2 V,
LOOP1 at 2 V,
See Figure 1
Idle
1
4.2
TXEN at 2 V,
LOOP2 at 2 V,
See Figure 1
LOOP1 at 2 V,
TXI at 3.2 V,
Active
1
4.2
V
OC
TXEN at 2 V,
LOOP2 at 2 V,
See Figure 1
LOOP1 at 2 V,
TXI at 4.4 V,
Active
Idle
1
4.2
±40
TXEN at 0.8 V,
LOOP2 at 2 V,
LOOP1 at 2 V,
See Figure 1
TXEN at 2 V,
LOOP2 at 2 V,
See Figure 1
LOOP1 at 2 V,
TXI at 3.2 V,
Active
– 600
1315
V
OD
Driver output (TXO) differential voltage
mV
TXEN at 2 V,
LOOP2 at 2 V,
See Figure 1
LOOP1 at 2 V,
TXI at 4.4 V,
Active
600
2.4
1315
V
V
High-level output voltage
Low-level output voltage
RXO, RXEN
RXO, RXEN
TXEN, LOOP
TXI
I
I
= –0.4 mA
V
V
OH
OH
= 16 mA
0.5
20
OL
OL
V = 2 V
I
I
IH
High-level input current
V = 4.5 V
I
400
µA
RXI, RXI
V
= –0.5 V,
V
V
= 1 V to 4.2 V
= 1 V to 4.2 V
1000
–200
100
ID
V = 0.8 V
IC
TXEN, LOOP
I
V = 3.1 V
I
I
IL
Low-level input current
TXI
µA
V = 0.3 V
I
4
10
RXI, RXI
Idle
V
ID
= 0.5 V,
1000
IC
TXEN at 0.8 V,
LOOP2 at 2 V,
LOOP1 at 2 V,
See Figure 2
I
I
I
Driver differential output current
±4
mA
mA
mA
OD
OS
CC
V
at 0 V,
RXI at 3 V,
O
†
Short-circuit output current
Supply current
RXO, RXEN
– 40 – 150
RXI at 2 V
LOOP2 at 2 V,
TXI at 4.5 V,
TXEN at 2 V,
Outputs open
225
†
Not more than one output should be shorted at a time, and the duration of the test should not exceed 1 second.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054D – APRIL 1989 – REVISED OCTOBER 2001
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
MAX
150
150
150
150
150
150
150
10
UNIT
TXO shorted to TXO, Current measured in short
TXO at 0 V,
TXO is open,
TXO at 0 V,
TXO at 16 V,
TXO is open,
TXO at 16 V,
RXI shorted to RXI,
RXI at 0 V,
TXO is open,
TXO at 0,
Current measured at TXO
Current measured at TXO
‡
Driver fault condition current
TXO at 0 V,
TXO is open,
TXO at 16 V,
TXO at 16 V,
Current measured at TXO and TXO
Current measured at TXO
mA
Current measured at TXO
Current measured at TXO and TXO
Current measured in short
RXI is open,
RXI at 0 V,
RXI at 0 V,
RXI at open,
RXI at 16 V,
RXI at 16 V,
Current measured at RXI
3
RXI is open,
RXI at 0 V,
Current measured at RXI
3
‡
Receiver fault condition current
Current measured at RXI and RXI
Current measured at RXI
3
mA
RXI at 16 V,
RXI at open,
RXI at 16 V,
10
Current measured at RXI
10
Current measured at RXI and RXI
10
‡
Fault conditions should be measured on only one channel at a time.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
driver
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
MAX
15
UNIT
ns
Propagation delay time,
low-to-high level output
t
t
t
t
t
TXI
TXI
TXO, TXO TXEN at 2 V,
TXO, TXO TXEN at 2 V,
TXO, TXO TXEN at 2 V,
TXO, TXO TXI at 3.2 V,
TXO, TXO TXEN at 2 V,
TXO, TXO TXEN at 2 V,
TXO, TXO TXEN at 2 V,
See Figure 3
See Figure 3
See Figure 4
See Figure 5
See Figure 6
See Figure 6
See Figure 3
PLH
PHL
PIL
PIL
w
Propagation delay time,
high-to-low level output
15
ns
Propagation delay time,
idle-to-low level output
TXI
25
ns
Propagation delay time,
idle-to-low level output
TXEN
25
ns
Output pulse duration, from
low-to-high level to 70% output level
260
8000
–100
±3
ns
Driver output differential
undershoot voltage
V
TXI
TXI
mV
ns
OD(U)
Driver caused signal skew
t
sk
t
– t
PLH PHL
t
t
Rise time, TXO, TXO
Fall time, TXO, TXO
TXEN at 2 V,
TXEN at 2 V,
See Figure 3
See Figure 3
1
1
5
5
ns
ns
r
f
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054D – APRIL 1989 – REVISED OCTOBER 2001
receiver
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
MAX
15
UNIT
ns
Propagation delay time,
low-to-high level output
t
t
t
t
t
t
t
t
t
t
RXI, RXI
RXO
RXO
V
= 1 V to 4.2 V, See Figure 10
= 1 V to 4.2 V, See Figure 10
PLH
PHL
PLH
PHL
sk
IC
Propagation delay time,
high-to-low level output
RXI, RXI
RXI, RXI
RXI, RXI
RXI, RXI
V
V
15
ns
IC
Start-up delay time,
low-to-high level output
= 1 V to 4.2 V,
See Figure 12
V
ID
V
ID
V
ID
V
ID
V
ID
V
ID
V
ID
V
ID
V
ID
= –500 mV,
= 500 mV,
= 500 mV,
= –175 mV,
= –275 mV,
= ±500 mV,
= ±500 mV,
= ±500 mV,
= ±500 V,
IC
RXEN
RXEN
RXO
55
ns
Shutdown delay time,
high-to-low level output
V
= 1 V to 4.2 V,
IC
See Figure 12
142
25
181
±3
ns
Receiver caused signal
V
= 1 V to 4.2 V,
IC
See Figure 10
ns
skew (t
– t )
PLH PHL
Pulse duration at RXI and RXI
(to not activate squelch)
V
= 1 V to 4.2 V,
IC
See Figure 11
ns
w
Pulse duration at RXI and RXI
(to activate squelch)
V
= 1 V to 4.2 V,
IC
See Figure 11
50
8
ns
w
V
= 1 V to 4.2 V,
IC
See Figure 10
Rise time, RXO
Rise time, RXEN
Fall time, RXO
1
1
1
ns
r1
V
= 1 V to 4.2 V,
IC
See Figure 12
8
ns
r2
V
= 1 V to 4.2 V,
IC
See Figure 10
8
ns
f1
V
IC
= 2.5 V,
See Figure 12
t
t
Fall time, RXEN
1
8
ns
ns
f2
RXO valid after RXEN high
See Figure 10
–10
15
v
loop
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
MAX
30
UNIT
ns
Propagation delay time,
low-to-high level output
LOOP at 0.8 V,
TXEN at 2 V,
TXEN at 2 V,
t
t
t
t
TXI
TXI
RXO
RXO
PLH
PHL
PLH
PHL
See Figure 13
Propagation delay time,
high-to-low level output
LOOP at 0.8 V,
See Figure 13
30
ns
Propagation delay time,
low-to-high level output
TXEN
TXEN
RXEN
RXEN
LOOP at 0.8 V,
LOOP at 0.8 V,
See Figure 14
See Figure 14
50
ns
Propagation delay time,
high-to-low level output
50
ns
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054D – APRIL 1989 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
V
TXO
TXO
TXO
39 Ω
V
OD
TXI
39 Ω
V
OC
V
TXO
Figure 1. Driver Test Circuit
TXO
I
OD
TXI
TXO
Figure 2. Driver Test Circuit
TXO
TXO
39 Ω
0.01 µF
25 pF
V
OD
3 kΩ
3 kΩ
†
TXI
39 Ω
25 pF
TEST CIRCUIT
4.5 V
3 V
TXI
50%
50%
t
t
PHL
PLH
V
OD+
90%
90%
TXO
0 V
0 V
10%
10%
V
OD–
t
t
f
r
VOLTAGE WAVEFORMS
†
Transformer specifications:
Turns ratio
1:1
Magnetizing inductance
Winding resistance
Rise time 10% to 90%
Interwinding capacitance
Leakage inductance
Inductive Q
26 to 30 µH
0.6 Ω Max
5 ns Max
25 pF
0.25 µH Max
1250 Min
Figure 3. Test Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054D – APRIL 1989 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
TXO
39 Ω
0.01 µF
25 pF
3 kΩ
3 kΩ
V
OD
†
TXI
39 Ω
TXO
25 pF
TEST CIRCUIT
†
See Figure 3
4.5 V
3 V
50%
TXI
t
PIL
IDLE
TXO
90%
V
OD–
VOLTAGE WAVEFORMS
NOTE A: Input t ≤ 5 ns; t ≤ 5 ns
r
f
Figure 4. Test Circuit and Voltage Waveforms
TXEN
TXI
TXO
39 Ω
0.01 µF
25 pF
V
3 kΩ
3 kΩ
OD
†
39 Ω
TXO
25 pF
TEST CIRCUIT
†
See Figure 3
2 V
TXEN
50%
90%
0.8 V
t
PIL
Idle
TXO
V
OD–
VOLTAGE WAVEFORMS
Figure 5. Test Circuit and Voltage Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054D – APRIL 1989 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
TXO
39 Ω
25 pF
V
OD
3 kΩ
3 kΩ
†
TXI
0.01 µF
39 Ω
TXO
25 pF
TEST CIRCUIT
†
See Figure 3
V
OH
70%
TXO
50%
V
OD(U)
V
OL
t
w
VOLTAGE WAVEFORMS
Figure 6. Test Circuit and Voltage Waveforms
2 V
TXEN
50%
0.8 V
t
su1
4.5 V
3 V
50%
TXI
NOTE A: Input t ≤ 5 ns; t ≤ 5 ns
r
f
Figure 7
4.5 V
3 V
TXI
50%
t
h1
2 V
50%
TXEN
0.8 V
t
h2
2 V
LOOP
50%
0.8 V
NOTE A: Input t ≤ 5 ns; t ≤ 5 ns
r
f
Figure 8
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054D – APRIL 1989 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
2 V
50%
LOOP
TXEN
0.8 V
2 V
t
su2
50%
0.8 V
t
su3
4.5 V
3 V
TXI
50%
NOTE A: Input t ≤ 5 ns; t ≤ 5 ns
r
f
Figure 9
RXEN
6 kΩ
20 pF
RXI
RXI
RXO
20 pF
6 kΩ
TEST CIRCUIT
1 V
RXI
0 V
–1 V
V
OH
RXEN
90%
V
IL
t
PHL
t
PLH
t
t
v
t
f1
r1
V
V
OH
90%
10%
VOLTAGE WAVEFORMS
90%
10%
1.3 V
1.3 V
1.3 V
RXO
OL
NOTE A: Input t ≤ 5 ns; t ≤ 5 ns
r
f
Figure 10. Test Circuit and Voltage Waveforms
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054D – APRIL 1989 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
RXEN
6 kΩ
20 pF
RXI
RXO
RXI
TEST CIRCUIT
0 V
–40 mV
–40 mV
RXI
V
IO
t
w
V
OH
OL
RXEN
V
VOLTAGE WAVEFORMS
NOTE A: Input t ≤ 5 ns; t ≤ 5 ns
r
f
Figure 11. Test Circuit and Voltage Waveforms
RXEN
6 kΩ
20 pF
RXI
RXO
RXI
TEST CIRCUIT
1 V
RXI
0
–40 mV
–1 V
t
PLH
t
PHL
90%
V
V
OH
90%
RXEN
10%
10%
OL
t
t
f2
r2
VOLTAGE WAVEFORMS
NOTE A: Input t ≤ 5 ns; t ≤ 5 ns
r
f
Figure 12. Test Circuit and Voltage Waveforms
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054D – APRIL 1989 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
4.5 V
50%
50%
TXI
3 V
t
t
PLH
PHL
V
OH
OL
1.3 V
1.3 V
RXO
V
NOTE A: Input t ≤ 5 ns; t ≤ 5 ns
r
f
Figure 13
2 V
TXEN
RXEN
50%
50%
0.8 V
t
PLH
t
PHL
V
V
OH
1.3 V
1.3 V
OL
NOTE A: Input t ≤ 5 ns; t ≤ 5 ns
r
f
Figure 14
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
SN75ALS085DW
SN75ALS085DWG4
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
NRND
SOIC
SOIC
DW
24
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
75ALS085
75ALS085
NRND
DW
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
Medical
Logic
Security
www.ti.com/security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense
Video and Imaging
www.ti.com/space-avionics-defense
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/omap
OMAP Applications Processors
Wireless Connectivity
TI E2E Community
e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2014, Texas Instruments Incorporated
相关型号：
UL1042
UL1042 - Uk砤d zr體nowa縪nego mieszacza iloczynowegoWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
ZXFV201
QUAD VIDEO AMPLIFIERWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ZETEX
ZXFV201N14
IC-SM-VIDEO AMPWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ZETEX
ZXFV201N14TA
QUAD VIDEO AMPLIFIERWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ZETEX
ZXFV201N14TC
QUAD VIDEO AMPLIFIERWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ZETEX
Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
ZXFV302N16
IC-SM-4:1 MUX SWITCHWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
ZXFV4089
VIDEO AMPLIFIER WITH DC RESTORATIONWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ZETEX
Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ZETEX
©2020 ICPDF网 联系我们和版权申明