SN75DP139RSBT [TI]
3.4Gbps DP++ 转 HDMI 1.4b 重定时器 | RSB | 40 | 0 to 85;
| 型号： | SN75DP139RSBT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.4Gbps DP++ 转 HDMI 1.4b 重定时器 | RSB | 40 | 0 to 85 消费电路 商用集成电路 |
| 文件： | 总32页 (文件大小：952K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN75DP139
www.ti.com...................................................................................................................................................................................................... SLLS977–APRIL 2009
DisplayPort to TMDS Translator
1
FEATURES
APPLICATIONS
•
Personal Computer Market
•
DisplayPort Physical Layer Input Port to TMDS
Physical Layer Output Port
–
–
–
–
–
DP/TMDS Dongle
Desktop PC
Notebook PC
Docking Station
Standalone Video Card
•
Integrated TMDS level translator with Receiver
Equalization
•
•
Supports Data Rates up to 2.5Gbps
Integrated I2C Logic Block for DVI/HDMI
Connector Recognition
•
•
•
Integrated Active I2C Buffer
Enhanced ESD: 10KV on all pins
Enhanced Commercial Temperature Range:
0°C to 85°C
•
48 Pin 7 × 7 QFN Package
DESCRIPTION
The SN75DP139 is a Dual-Mode DisplayPort input to Transition-Minimized Differential Signaling (TMDS) output.
The TMDS output has a built in level translator supporting Digital Video Interface (DVI) 1.0 and High Definition
Multimedia Interface (HDMI) 1.3 standards. The SN75DP139 is specified up to a maximum data rate of 2.5Gbps,
supporting resolutions greater then 1920x1200 or HDTV 12 bit color depth at 1080p (progressive scan).
An integrated Active I2C buffer isolates the capacitive loading of the source system from that of the sink and
interconnecting cable. This isolation improves overall signal integrity of the system and allows for considerable
design margin within the source system for DVI / HDMI compliance testing.
A logic block was designed into the SN75DP139 in order to assist with TMDS connector identification. Through
the use of the I2C_EN pin, this logic block can be enabled to indicate the translated port is an HDMI port;
therefore legally supporting HDMI content.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN75DP139
SLLS977–APRIL 2009...................................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive
foam during storage or handling to prevent electrostatic damage to the MOS gates.
TYPICAL APPLICATION
DP++
SN75DP139 TMDS
TMDS Buffer
DVI or HDMI
Compliant
GPU
Monitor or HDTV
Dongle
Computer Notebook
Docking Station
GPU - Graphics Processing Unit
DP++ - Dual-Mode DisplayPort
TMDS - Transition-Minimized Differential Signaling
DVI - Digital Visual Interface
HDMI - High Definition Multimedia Interface
GPU
DP++
TMDS
DVI
Graphics Processing Unit
Dual-Mode DisplayPort
Transition-Minimized Differential Signaling
Digital Visual Interface
HDMI
High Definition Multimedia Interface
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DATA FLOW BLOCK DIAGRAM
Vsadj, SRC, OE_N
GND
GND
SN75DP139
I2C
Slave
IN_D1-
IN_D1+
VCC
OUT_D1-
OUT_D1+
VCC
OVS,
DDC_EN
I2C_EN
IN_D2-
IN_D2+
OUT_D2-
OUT_D2+
GND
130kohm
GND
IN_D3-
OUT_D3-
IN_D3+
VCC
OUT_D3+
VCC
HPDINV
IN_D4-
IN_D4+
OUT_D4-
OUT_D4+
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DEVICE INFORMATION
RGZ PACKAGE
36 35 34 33 32 31 30 29 28 27 26 25
37
GND
24
23
22
21
20
19
18
17
16
15
14
13
GND
IN_D1-
IN_D1+
VCC
38
39
40
41
42
43
44
OUT_D1-
OUT_D1+
VCC
IN_D2-
IN_D2+
OUT_D2-
OUT_D2+
GND
DP139
TOP VIEW
GND
IN_D3-
OUT_D3-
IN_D3+
VCC
45
46
OUT_D3+
VCC
IN_D4-
IN_D4+
47
OUT_D4-
OUT_D4+
48
1
2
3
4
5
6
7
8
9 10 11 12
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PIN FUNCTIONS
PIN
I/O
DESCRIPTION
SIGNAL
NO.
MAIN LINK INPUT PINS
IN_D1
38, 39
41, 42
44, 45
47, 48
I
I
I
I
DisplayPort Main Link Channel 0 Differential Input
DisplayPort Main Link Channel 1 Differential Input
DisplayPort Main Link Channel 2 Differential Input
DisplayPort Main Link Channel 3 Differential Input
MAIN LINK PORT B OUTPUT PINS
TMDS Data 2 Differential Output
IN_D2
IN_D3
IN_D4
OUT_D1
OUT_D2
OUT_D3
OUT_D4
23, 22
20, 19
17, 16
14, 13
O
O
O
O
TMDS Data 1 Differential Output
TMDS Data 0 Differential Output
TMDS Data Clock Differential Output
HOT PLUG DETECT PINS
HPD_SOURCE
HPD_SINK
7
O
I
Hot Plug Detect Output
30
Hot Plug Detect Input
AUXILIARY DATA PINS
SDA_SOURCE,
SCL_SOURCE
8, 9
I/O Source Side Bidirectional DisplayPort Auxiliary Data Line
I/O TMDS Port Bidirectional DDC Data Lines
CONTROL PINS
SDA_SINK,
SCL_SINK
29, 28
OE_N
NC
25
10
35
32
34
6
I
Output Enable and power saving function for High Speed Differential level shifter path.
No Connect
OVS
I
I
I
I
I
I
DDC I2C buffer offset select
DDC_EN
HPDINV
VSadj
SRC
Enables or Disables the DDC I2C buffer
HPD_SOURCE Logic and Level Select
TMDS Compliant Voltage Swing Control
TMDS outputs rise and fall time select
Internal I2C register enable, used for HDMI / DVI connector differentiation
SUPPLY AND GROUND PINS
3
I2C_EN
4
VCC
GND
2, 11, 15, 21,
26,
33, 40, 46
3.3V Supply
1, 5, 12, 18, 24,
27, 31, 36, 37,
43
Ground
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Input/Output Equivalent Circuits
VTERM
VTERM
VCC
50 W
50 W
–
+
Figure 1. DisplayPort Input Stage
Y
Z
10 mA
Figure 2. TMDS Output Stage
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OE_N
I2C_EN
HPDINV
SRC
OVS
DDC_EN
HPD_SINK
Figure 3. HPD and Control Input Stage
VCC
HPD_OUT
Figure 4. HPD Output Stage
400 W
SCL
SDA
AUX+/–
VOL
Figure 5. I2C Input and Output Stage
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Table 1. Control Pin Lookup Table
SIGNAL
LEVEL(1)
STATE
DESCRIPTION
OE_N
H
Power Saving
Mode
Main Link is disabled. IN_Dx termination = 50 Ω with common mode voltage set to
0V.
OUT_Dx outputs = high impedance
L
Normal Mode
HDMI
IN_Dx termination = 50 Ω
OUT_Dx outputs = active
I2C_EN
H
The Internal I2C register is active and readable when the TMDS port is selected
indicating that the connector being used is HDMI.
This mode selects the fastest rise and fall time for the TMDS differential output
signals
L
DVI
The Internal I2C register is disabled and not readable when the TMDS port is
selected indicating that the connector being used is DVI.
This mode selects a slower rise and fall time for the TMDS differential output signals
See DVI Application Section.
VSadj
4.02 kΩ
±5%
Output Voltage Driver output voltage swing precision control to aid with system compliance
Swing Contol
HPDINV
H
L
HPD Inversion
HPD_SOURCE VOH =0.9V (typical) and HPD logic is inverted
HPD_SOURCE VOH =3.2V (typical) and HPD logic is non-inverted
HPD
non-inversion
SRC
H
L
Edge Rate:
Slowest
SRC helps to slow down the rise and fall time. SRC =High adds ~60ps to the rise
and fall time of the TMDS differential output signals in addition to the I2C_EN pin
selection
Edge Rate: Slow SRC helps to slow down the rise and fall time. SRC =Low adds ~30ps to the rise
and fall time of the TMDS differential output signals in addition to the I2C_EN pin
selection
Hi-Z
Edge Rate
Leaving the SRC pin High Z, will keep the default rise and fall time of the TMDS
differential output signals as selected by the I2C_EN pin.
It is recommended that an external resistor-divider (less than 100 kΩ) is used so
that voltage on this pin = VCC/2, if Hi-Z logic level is intended on this pin.
OVS
H
L
Offset 1
Offset 2
Offset 3
DDC source side VOL and VIL offset range 1
DDC source side VOL and VIL offset range 2
Hi-Z
DDC source side VOL and VIL offset range 3
It is recommended that an external resistor-divider (less than 100 kΩ) is used so
that voltage on this pin = VCC/2, if Hi-Z logic level is intended on this pin.
DDC_EN
H
L
DDC Buffer
enabled
DDC Buffer is enabled
DDC buffer
disabled
DDC Buffer is disabled
(1) (H) Logic High; (L) Logic Low; (Z) High Z
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SN75DP139
www.ti.com...................................................................................................................................................................................................... SLLS977–APRIL 2009
ORDERING INFORMATION(1)
PART NUMBER
SN75DP139RGZR
SN75DP139RGZT
PART MARKING
DP139
PACKAGE
48-pin QFN Reel (large)
48-pin QFN Reel (small)
DP139
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
–0.3 to 3.6
1.56
UNIT
Supply voltage range(2)
Voltage range
VCC
V
V
V
V
V
Main Link Input (IN_Dx) differential voltage
TMDS Outputs (OUT_Dx)
HPD I/O (HPD_SOURCE, HPD_SINK)
–0.3 to 4
–0.3 to 5.5
–0.3 to 5.5
Auxiliary I/O (SCL_SOURCE, SDA_SOURCE, SCL_SINK,
SDA_SINK)
Control I/O (OE_N, DDC_EN, SRC, OVS, HPDINV)
Human body model(3)
Charged-device model(4)
–0.3 to 5.5
V
V
V
V
±10000
Electrostatic discharge
±1500
±200
Machine model(5)
Continuous power dissipation
See Dissipation Rating Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B
(4) Tested in accordance with JEDEC Standard 22, Test Method C101-A
(5) Tested in accordance with JEDEC Standard 22, Test Method A115-A
DISSIPATION RATINGS
PACKAGE
PCB JEDEC
STANDARD
TA ≤ 25°C
DERATING FACTOR(1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
Low-K
High-K
1426.8 mW
3125 mW
14.28 mW/°C
31.25 mW/°C
570 mW
48-pin QFN (RGZ)
1250 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
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THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
9
MAX(1)
UNIT
°C/W
°C/W
RθJB
RθJC
Junction-to-board thermal resistance
Junction-to-case thermal resistance
22
HDMI Mode: OE_N = 0V, DDC_EN = 5V, VCC = 3.6V,
ML: VID_PP = 1200mV, 2.5Gbps TMDS pattern
AUX: VI = 3.3V, 100 kHz PRBS
PD1
Device power dissipation(2)
Device power dissipation(2)
270+146(2) 396+146(2)
214+146(2) 306+146(2)
mW
mW
HPD: HPD_SINK = 5V, I2C_EN = 5V, SRC = Hi-Z
DVI Mode: OE_N = 0V, DDC_EN = 5V, VCC = 3.6V,
ML: VID_PP = 1200mV, 2.5Gbps TMDS pattern
AUX: VI = 3.3V, 100 kHz PRBS
PD2
HPD: HPD_SINK= 5V, I2C_EN = 0V, SRC = Hi-Z
Device power dissipation under low
power with
HPDINV = LOW
OE_N = 5V, DDC_EN = 0V, HPDINV = 0V,
HPD_SINK = 0V
PSD1
PSD2
PSD3
PSD4
18
1.7
54
3
µW
mW
mW
mW
Device power dissipation under low
power with
HPDINV =HIGH
OE_N = 5V, DDC_EN = 0V, HPDINV = 5V
OE_N = 5V, DDC_EN = 5V, HPDINV = 5V
OE_N = 5V, DDC_EN = 5V, HPDINV = 0V
Device power dissipation under low
power with DDC enabled with
HPDINV = HIGH
16.5
15
29
26
Device power dissipation under low
power with DDC enabled with
HPDINV = LOW
(1) The maximum rating is simulated under 3.6V VCC unless otherwise noted.
(2) Power dissipation is the sum of the power consumption from the VCC pins, plus the 146 mW of power from the AVCC (HDMI/DVI
Receiver Termination Supply).
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX UNIT
VCC
TA
Supply Voltage
3
0
3.3
3.6
85
V
Operating free-air temperature
°C
MAIN LINK DIFFERENTIAL INPUT PINS
VID_PP Peak-to-peak AC input differential voltage
dR
trise fall time
VPRE
0.15
0.25
75
1.2
V
Data rate
2.5 Gbps
ps
Input Signal Rise and Fall time (20%-80%)
Pre-emphasis on the Input Signal at IN_Dx pins
0
0
0
db
TMDS DIFFERENTIAL OUTPUT PINS
AVCC
dR
TMDS output termination voltage
3
0.25
45
3.3
3.6
V
Data rate
2.5 Gbps
RT
Termination resistance
TMDS output swing voltage bias resistor(1)
50
55
Ω
RVsadj
3.65
4.02
kΩ
AUXILIARY AND I2C PINS
VI
Input voltage
I2C data rate
0
5.5
V
dR(I2C)
100
kHz
(1) RVsadj resistor controls the SN75DP139 Driver output voltage swing and thus helps in meeting system compliance. It is recommended
that RVsadj resistor should be above the MIN value as indicated in the RECOMMENDED OPERATING CONDITIONS table, however for
NOM and MAX value, Figure 24 could be used as reference. It is important to note that system level losses, AVCC and RT variation
affect RVsadj resistor selection. Worse case variation on system level losses, AVCC, RT could make RVsadj resistor value of 4.02 kΩ ±5%
result in non-compliant TMDS output voltage swing. In such cases Figure 24 could be used as reference.
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RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX UNIT
HPD_SINK, HPDINV, OE_N, DDC_EN, I2C_EN
VIH
High-level input voltage
Low-level input voltage
2
0
5.5
0.8
V
V
VIL
SRC, OVS
VIH_SRC_OVS
VIL_SRC_OVS
High-level input voltage
Low-level input voltage
3
0
5.5
0.5
V
V
DEVICE POWER
The SN75DP139 is designed to operate off of one supply voltage VCC.
The SN75DP139 offers features to enable or disable different functionality based on the status of the output
enable (OE_N) and DDC Enable (DDC_EN) inputs.
•
OE_N affects only the High Speed Differential channels (Main Link/TMDS link). OE_N has no influence on the HPD_SINK input,
HPD_SOURCE output, or the DDC buffer.
•
DDC_EN affects only the DDC channel. The DDC_EN should never change state during the I2C operation. Disabling DDC_EN during a
bus operation will hang the bus, while enabling the DDC_EN during bus traffic will corrupt the I2C bus operation. DDC_EN should only
be toggled while the bus is idle.
•
TMDS output edge rate control has impact on the SN75DP139 Active power. See Figure 20. TMDS output edge rate can be controlled
by SRC pin. Slower output Edge Rate Setting helps in reducing the Active power consumption.
HPD_SINK
HPDINV
OE_N
DDC_EN
IN_Dx
OUT_Dx
DDC
HPD_SOURCE
MODE
Input = H or L
L
L
L
50 Ω termination
Enabled
High-
Output = non inverted, Active
active
impedance follows HPD_SINK
Input = H or L
Input = H or L
L
L
L
H
L
50 Ω termination
active
Enabled
High-
enabled
Output = non inverted, Active
follows HPD_SINK
H
50 Ω termination
active:
High-
Output = non inverted, Low Power
impedance impedance follows HPD_SINK
Terminations
connected to
common Mode
Voltage = 0V.
Input = H or L
L
H
H
50 Ω termination
active:
High-
impedance
enabled
Output = non inverted, Low Power
follows HPD_SINK
with
Terminations
connected to
common Mode
Voltage = 0V.
DDC channel
enabled
Input = H or L
Input = H or L
Input = H or L
H
H
H
L
L
L
H
L
50 Ω termination
active
Enabled
Enabled
High-
High-
Output = inverted,
Active
impedance follows HPD_SINK
50 Ω termination
active
enabled
Output = inverted,
follows HPD_SINK
Active
H
50 Ω termination
active:
High-
Output = inverted,
Low Power
impedance impedance follows HPD_SINK
Terminations
connected to
common Mode
Voltage = 0V.
Input = H or L
H
H
H
50 Ω termination
active:
High-
impedance
enabled
Output = inverted,
follows HPD_SINK
Low Power
with
Terminations
connected to
common Mode
Voltage = 0V.
DDC channel
enabled
L = LOW, H = HIGH
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
Supply current (HDMI Mode)
HDMI Mode: OE_N = 0V, DDC_EN = 5V, VCC
=
82
110
mA
3.6V,
ML: VID_PP = 1200mV, 2.5Gbps TMDS pattern
AUX: VI = 3.3V, 100 kHz PRBS
HPD: HPD_SINK = 5V, I2C_EN = 5V, SRC = Hi-Z
ICC2
Supply Current (DVI Mode)
DVI Mode: OE_N = 0V, DDC_EN = 5V, VCC = 3.6V,
ML: VID_PP = 1200mV, 2.5Gbps TMDS pattern
AUX: VI = 3.3V, 100 kHz PRBS
65
85
15
mA
HPD: HPD_SINK= 5V, I2C_EN = 0V, SRC = Hi-Z
ISD1
ISD2
ISD3
Shutdown current with
HPDINV = LOW
OE_N = 5V, DDC_EN = 0V, HPDINV = 0V,
HPD_SINK = 0V
5.5
µA
Shutdown current with
HPDINV = HIGH
0.5
5
0.8
8
mA
mA
OE_N = 5V, DDC_EN = 0V, HPDINV = 5V
Shutdown current with DDC enabled
with
OE_N = 5V, DDC_EN = 5V, HPDINV = 5V
HPDINV = HIGH
ISD4
Shutdown current with DDC enabled
4.5
7.2
mA
with
OE_N = 5V, DDC_EN = 5V, HPDINV = 0V
HPDINV = LOW
Hot Plug Detect
The SN75DP139 has a built in level shifter for the HPD outputs. The output voltage level of the HPD pin is
defined by the voltage level of the VCC pin. The HPD input or HPD_SINK side has 130kohm of pull down
resistor integrated.
The logic of the HPD_SOURCE output always follows the logic state of the HPD_SINK input based on the
HPDINV pin logic, regardless of whether the device is in Active or Low Power Mode
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VOH3.3
VOH1.1
High-level output voltage
IOH = –100 µA, VCC = 3.3 V ±10%,
HPDINV = LOW
2.8
3.6
V
High-level output voltage
IOH = –100 µA, VCC = 3.3 V ±10%,
0.8
1.1
V
HPDINV = HIGH
VOL
IIH
Low-level output voltage
IOH = 100 µA
0
–30
–30
110
0.1
30
V
High-level input current
VIH = 2.0 V, VCC = 3.6 V
VIL = 0.8 V, VCC = 3.6 V
µA
µA
kΩ
IIL
Low-level input current
30
RINTHPD
Input pull down on HPD_SINK (HPD Input)
130
160
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
30 ns
tPD(HPD)
Propagation delay
VCC = 3.6 V
2
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1.1 V
HPD Output/HPD_source
HPD Input/HPD_sink
10 kW
HPD Input/HPD_sink
Dp139
DP139
HPD Output/HPD_source
130 kW
100 kW
100 kW
130 kW
130 kW Pull down
resistor on the sink side
is integrated
130 kW Pull down
resistor is integrated
Figure 6. HPD Test Circuit (HPDINV = LOW)
Figure 7. HPD Test Circuit (VOH =1.1), HPDINV=HIGH
5 V
0 V
HPD_SINK
50%
5 V
50%
HPD_SINK
0 V
t
PD(HPD)
t
PD(HPD)
V
CC
1.1 V
HPD_SOURCE
50%
HPD_SOURCE
50%
0 V
0 V
Figure 8. HPD Timing Diagram (HPDINV = LOW)
Figure 9. HPD Timing Diagram (HPDINV = HIGH)
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AUX / I2C pins
The SN75DP139 utilizes an active I2C repeater. The repeater is designed to isolate the parasitic effects of the
system in order to aid with system level compliance.
In addition to the I2C repeater, the SN75DP139 also supports the connector detection I2C register. This register
is enabled via the I2C_EN pin. When active an internal memory register is readable via the AUX_I2C I/O. The
functionality of this register block is described in the APPLICATION INFORMATION section.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
Low input current
TEST CONDITIONS
VCC = 3.6 V, VI = 0 V
MIN TYP MAX
UNIT
µA
IL
–10
–10
10
10
Ilkg(AUX)
Input leakage current
AUX_I2C pins
VCC = 3.6V, VI = 3.6 V
µA
(SCL_SOURCE,
SDA_SOURCE)
CIO(AUX)
VIH(AUX)
VIL1(AUX)
VOL1(AUX)
VIL2(AUX)
VOL2(AUX)
VIL3(AUX)
VOL3(AUX)
Ilkg(I2C)
Input/Output capacitance
High-level input voltage
Low-level input voltage
Low-level output voltage
Low-level input voltage
Low-level output voltage
Low-level input voltage
Low-level output voltage
Input leakage current
AUX_I2C pins
(SCL_SOURCE,
SDA_SOURCE)
AUX_I2C pins
(SCL_SOURCE,
SDA_SOURCE)
AUX_I2C pins
(SCL_SOURCE,
SDA_SOURCE)
AUX_I2C pins
(SCL_SOURCE,
SDA_SOURCE)
AUX_I2C pins
(SCL_SOURCE,
SDA_SOURCE)
AUX_I2C pins
(SCL_SOURCE,
SDA_SOURCE)
AUX_I2C pins
(SCL_SOURCE,
SDA_SOURCE)
AUX_I2C pins
(SCL_SOURCE,
SDA_SOURCE)
I2C SDA/SCL pins VCC = 3.6 V, VI = 4.95 V
(SCL_SINK,
SDA_SINK)
I2C SDA/SCL pins DC bias = 2.5 V, AC = 3.5Vp-p, f = 100
(SCL_SINK,
SDA_SINK)
I2C SDA/SCL pins
(SCL_SINK,
SDA_SINK)
I2C SDA/SCL pins
(SCL_SINK,
SDA_SINK)
DC bias = 1.65 V, AC = 2.1Vp-p, f = 100
kHz
15
5.5
0.4
0.7
0.4
0.6
0.3
0.5
10
pF
V
1.6
–0.2
0.6
OVS = HIGH
V
IO = 3 mA, OVS = HIGH
OVS = Hi-Z
V
–0.2
0.5
V
IO = 3 mA, OVS = Hi-Z
OVS = Low
V
–0.2
0.4
V
IO = 3 mA, OVS = Low
V
–10
µA
pF
V
CIO(I2C)
Input/Output capacitance
High-level input voltage
Low-level input voltage
Low-level output voltage
15
kHz
VIH(I2C)
2.1
5.5
1.5
0.2
VIL(I2C)
–0.2
V
VOL(I2C)
I2C SDA/SCL pins IO = 3mA
(SCL_SINK,
V
SDA_SINK)
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SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Source to Sink
MIN
204
35
TYP
MAX UNIT
tPLH1
tPHL1
tPLH2
tPHL2
tf1
Propagation delay time, low to high
Propagation delay time, high to low
Propagation delay time, low to high
Propagation delay time, high to low
Output signal fall time
600
200
251
200
72
ns
ns
ns
ns
ns
ns
kHz
µs
µs
ns
µs
µs
µs
µs
µs
Source to Sink
Sink to Source
Sink to Source
Sink Side
80
35
20
tf2
Output signal fall time
Source Side
Source Side
Source Side
Source Side
Source Side
Source Side
20
72
fSCL
tW(L)
tW(H)
tSU1
th(1)
SCL clock frequency for internal register
Clock LOW period for I2C register
Clock HIGH period for internal register
Internal register setup time, SDA to SCL
Internal register hold time, SCL to SDA
100
4.7
4.0
250
0
T(buf)
tsu(2)
th(2)
Internal register bus free time between STOP and START Source Side
4.7
4.7
4.0
4.0
Internal register setup time, SCL to START
Internal register hold time, START to SCL
Internal register hold time, SCL to STOP
Source Side
Source Side
Source Side
tsu(3)
3.3 V
V
CC
R
= 2 kW
L
PULSE
GENERATOR
D.U.T.
C
= 100 pF
L
R
V
T
IN
V
OUT
Figure 10. Source Side Test Circuit (SCL_SOURCE, SDA_SOURCE)
5 V
V
CC
R
= 2 kW
L
PULSE
GENERATOR
D.U.T.
C
= 400 pF
L
R
V
T
IN
V
OUT
Figure 11. Sink Side Test Circuit (SCL_SINK,SDA_SINK)
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5 V
SCL_SINK
SDA_SINK
Input
1.6 V
0.1 V
t
t
PHL2
PLH2
3.3 V
80%
SCL_SOURCE
SDA_SOURCE
Output
1.6 V
20%
V
OL
t
f2
Figure 12. Source Side Output AC Measurements
3.3 V
SCL_SOURCE
SDA_SOURCE
Input
1.6 V
0.1 V
t
PHL1
5 V
80%
SCL_SINK
SDA_SINK
Output
1.6 V
20%
V
OL
t
f1
Figure 13. Sink Side Output AC Measurements
3.3 V
SCL_SOURCE
SDA_SOURCE
Input
VOL
5 V
t
PLH1
SCL_SINK
SDA_SINK
Output
1.6 V
Figure 14. Sink Side Output AC Measurements Continued
TMDS and Main link pins
The main link inputs are designed to support DisplayPort 1.1 specification. The TMDS outputs of the
SN75DP139 are designed to support the Digital Video Interface (DVI) 1.0 and High Definition Multimedia
Interface (HDMI) 1.3 specifications. The differential output voltage swing can be fine tuned with the RVsadj
resistor.
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ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
AVCC–10
AVCC–600
400
TYP
MAX UNIT
VOH
Single-ended HIGH level output voltage AVCC = 3.3 V, RT = 50 Ω,
Single-ended LOW level output voltage
AVCC+10
mV
mV
mV
mV
VOL
AVCC-400
VSWING
VOC(SS)
Single-ended output voltage swing
600
5
Change in steady-state common-mode
output voltage between logic states
–5
VOD(PP)
V(O)SBY
Peak-to-Peak output differential voltage
800
1200
mV
mV
Single-ended standby output voltage
AVCC = 3.3 V, RT = 50 Ω, OE_N =
AVCC–10
AVCC+10
High
I(O)OFF
Single-ended power down output
current
0V ≤ VCC ≤ 1.5 V, AVCC = 3.3 V,
RT = 50Ω
–10
10
µA
IOS
Short circuit output current
Input termination impedance
Input termination voltage
See Figure 19
–15
40
1
15
60
2
mA
Ω
RINT
Vterm
50
V
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
tPLH
tPHL
tR1
Propagation delay time
250
250
60
350
350
85
600
600
120
120
150
150
180
180
150
150
220
220
180
180
15
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Propagation delay time
Rise Time (I2C_EN = HI, SRC = Hi-Z)
Fall Time (I2C_EN = HI, SRC = Hi-Z)
Rise Time (I2C_EN = Low, SRC = Hi-Z)
Fall Time (I2C_EN = Low, SRC = Hi-Z)
Rise Time (I2C_EN = HI, SRC = HI)
Fall Time (I2C_EN = HI, SRC = HI)
Rise Time (I2C_EN = HI, SRC = Low)
Fall Time (I2C_EN = HI, SRC = Low)
Rise Time (I2C_EN = Low, SRC = HI)
Fall Time (I2C_EN = Low, SRC = HI)
Rise Time (I2C_EN = Low, SRC = Low)
Fall Time (I2C_EN = Low, SRC = Low)
Pulse skew
tF1
60
85
tR2
115
115
150
150
115
115
175
175
150
150
8
tF2
tR3
tF3
AVCC=3.3 V, RT = 50 Ω, f = 1MHz,
RVsadj = 4.02 kΩ
tR4
tF4
tR5
tF5
tR6
tF6
tSK(P)
tSK(D)
tSK(O)
tJITD(PP)
Intra-pair skew
20
65
Inter-pair skew
20
100
50
Peak-to-peak output residual data jitter
AVCC = 3.3 V, RT = 50Ω, dR=2.5Gbps,
TMDS output slew rate (default).
14
RVsadj = 4.02 kΩ (refer to Figure 18)
tJITC(PP)
Peak-to-peak output residual clock jitter
AVCC = 3.3 V, RT = 50Ω, f = 250 MHz
TMDS output slew rate (default).
RVsadj= 4.02 kΩ (refer to Figure 18)
8
30
ps
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V
TERM
3.3V
50Ω
50Ω
50Ω
50Ω
0.5 pF
D+
D-
Y
Z
100 pF
100 pF
Receiver
= V - V
V
Driver
ID
V
D+
V
Y
V
= V - V
Y Z
V
V
OD
D-
ID
D+
D-
V
Z
V
= (V + V )
Y Z
V
= (V + V )
D+ D-
OC
ICM
2
2
Figure 15. TMDS Main Link Test Circuit
2.2 V
1.8 V
V
V
ID
TERM
V
ID+
V
0 V
ID(pp)
V
ID-
t
t
PHL
PLH
80%
80%
V
OD
V
OD(pp)
0 V
20%
20%
t
t
r
f
Figure 16. TMDS Main Link Timing Measurements
V
OC
ΔV
OC SS)
(
Figure 17. TMDS Main Link Common Mode Measurements
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(4)
Avcc
(5)
(8)
R
T
R
T
SMA
SMA
SMA
SMA
Data +
Data -
Coax
Coax
Coax
Coax
RX
Parallel
BERT
OUT
+EQ
Jitter Test
(2,3)
600, 800 mV
VPP Differential
Instrument
(1)
FR4 PCB trace
AC coupling Caps
&
SN75DP139
FR4 PCB trace
AVcc
[No Pre-emphasis]
R
T
R
T
SMA
SMA
SMA
SMA
Coax
Coax
Coax
Coax
Clk+
RX
OUT
+EQ
Clk-
(6)(7)
Jitter Test
(2,3)
Instrument
TTP 4
TTP 1
TTP 2
TTP 3
1. The FR4 trace between TTP1 and TTP2 is designed to emulate 1-8" of FR4, AC coupling cap, connector and another 1-8" of FR4. Trace width - 4 mils.
2. All Jitter is measured at a BER of 10-9
3. Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP1
4. AVCC = 3.3V
5. RT = 50Ω,
6. Jitter data is taken with SN75DP139 configured in the fastest slew rate setting(default)
7. Rvsadj = 4.02kΩ
8. The input signal from parallel BERT does not have any pre-emphasis. Refer to recommended operating conditions
Figure 18. TMDS Jitter Measurements
50 W
I
OS
Driver
50 W
+
0 V or 3.6 V
-
Figure 19. TMDS Main Link Short Circuit Output Circuit
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TYPICAL CHARACTERISTICS
AVCC = 3.3 V, RT = 50Ω, RVsadj = 4.02 kΩ
POWER DISSIPATION
RESIDUAL JITTER OF 2.5 Gbps
vs
vs
DATA RATE
SUPPLY VOLTAGE
420
400
380
60
55
50
45
25°C Slowest Edge Rate
85°C
0°C
0°C Slowest Edge Rate
85°C Slowest Edge Rate
25°C
40
35
85°C Slowest Edge Rate
0°C Slowest Edge Rate
360
340
320
300
85°C
30
25
20
15
25°C
25°C Slowest Edge Rate
0°C
0
0.5
1
1.5
2
2.5
3
3
3.3
- Supply Voltage - V
3.6
V
Data Rate - Gbps
CC
Figure 20.
Figure 21.
RESIDUAL JITTER
vs
GAIN
vs
FREQUENCY
DATA RATE
50
45
40
35
30
25
20
15
10
5
20
VID(PP) = 600 mV
VID(PP) = 800 mV
(Slowest Edge Rate)
15
10
(Slowest Edge Rate)
VID(PP) = 1000 mV
(Slowest Edge Rate)
−5
VID(PP) = 600 mV
−0
−5
VID(PP) = 800 mV
VID(PP) = 1000 mV
−10
−15
0
0.25
10
100
1000
10000
0.75
1.25
1.75
2.25
f − Frequency − MHz
Data Rate - Gbps
Figure 22.
Figure 23.
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TYPICAL CHARACTERISTICS (continued)
AVCC = 3.3 V, RT = 50Ω
VOD
vs
Vsadj
1300
VCC = 3.6 V
1200
VCC = 3.3 V
1100
1000
900
VCC = 3.0 V
800
700
600
3.5
4
4.5
5
5.5
6
6.5
VSadj Resistance − kΩ
Figure 24.
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APPLICATION INFORMATION
DVI APPLICATION
In DVI application case, it is recommended that between the SN75DP139 TMDS outputs (OUT_Dx) and a
through hole DVI connector a series resistor placeholder is incorporated. This could help in case if there are
signal integrity issues as well as help pass system level compliance.
I2C INTERFACE NOTES
The I2C interface can be used to access the internal memory of the SN75DP139. I2C is a two-wire serial
interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus
consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and
SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins,
SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The
master is responsible for generating the SCL signal and device addresses. The master also generates specific
conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on
the bus under control of the master device. The SN75DP139 works as a slave and supports the standard mode
transfer (100 kbps) as defined in the I2C-Bus Specification.
The basic I2C start and stop access cycles are shown in Figure 25.
The basic access cycle consists of the following:
•
•
•
•
A start condition
A slave address cycle
Any number of data cycles
A stop condition
SDA
SCL
SDA
SCL
Start
Condition
Stop
Condition
Figure 25. I2C Start and Stop Conditions
GENERAL I2C PROTOCOL
•
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 27. All I2C-compatible devices should
recognize a start condition.
•
The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 26). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave
device with a matching address generates an acknowledge (see Figure 27) by pulling the SDA line low during
the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a
communication link with a slave has been established.
•
The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from
the slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. So
an acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long
as necessary (See Figure 28 ).
•
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 28). This releases the bus and stops the communication link
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with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address.
SDA
SCL
Data Line
Stable;
Data Valid
Change of Data Allowed
Figure 26. I2C Bit Transfer
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
Clock Pulse for
Acknowledgement
START
Condition
Figure 27. I2C Acknowledge
SCL
SDA
Acknowledge
Acknowledge
Data
Slave Address
Figure 28. I2C Address and Data Cycles
During a read cycle, the slave receiver will acknowledge the initial address byte if it decodes the address as its
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before
it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 29 and Figure 30.
See Example – Reading from the SN75DP139 section for more information.
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Figure 29. I2C Read Cycle
Figure 30. Multiple Byte Read Transfer
SLAVE ADDRESS
Both SDA and SCL must be connected to a positive supply voltage via a pull-up resistor. These resistors should
comply with the I2C specification that ranges from 2kΩ to 19kΩ. When the bus is free, both lines are high. The
address byte is the first byte received following the START condition from the master device. The 7 bit address is
factory preset to 1000000. Table 2 lists the calls that the SN75DP139 will respond to.
Table 2. SN75DP139 Slave Address
Fixed Address
Bit 4
Read/Write Bit
Bit 7
Bit 6
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
(MSB)
(R/W)
1
0
0
0
0
0
0
1
Sink Port Selection Register and Source Plug-In Status Register Description (Sub-Address)
The SN75DP139 operates using a multiple byte transfer protocol similar to Figure 30. The internal memory of the
SN75DP139 contains the phrase “DP-HDMI ADAPTOR<EOT>” converted to ASCII characters. The internal
memory address registers and the value of each can be found in Table 3.
During a read cycle, the SN75DP139 will send the data in its selected sub-address in a single transfer to the
master device requesting the information. See the Example – Reading from the SN75DP139 section of this
document for the proper procedure on reading from the SN75DP139.
Table 3. SN75DP139 Sink Port and Source Plug-In Status Registers Selection
Address
Data
0x00
44
0x01
50
0x02
2D
0x03
48
0x04
44
0x05
4D
0x06
49
0x07
20
0x08
41
0x09
44
0x0A
41
0x0B
50
0x0C
54
0x0D
4F
0x0E
52
0x0F
04
0x10
FF
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EXAMPLE – READING FROM THE SN75DP139:
The read operation consists of several steps. The I2C master begins the communication with the transmission of
the start sequence followed by the slave address of the SN75DP139 and logic address of 00h. The SN75DP139
will acknowledge it’s presence to the master and begin to transmit the contents of the memory registers. After
each byte is transferred the SN75DP139 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK)
from the master. If an ACK is received the next byte of data will be transmitted. If a NACK is received the data
transmission sequence is expected to end and the master should send the stop command.
The SN75DP139 will continue to send data as long as the master continues to acknowledge each byte
transmission. If an ACK is received after the transmission of byte 0x0F the SN75DP139 will transmit byte 0x10
and continue to transmit byte 0x10 for all further ACK’s until a NACK is received.
The SN75DP139 also supports an accelerated read mode where steps 1–6 can be skipped.
SN75DP139 Read Phase
Step 1
0
I2C Start (Master)
S
Step 2
7
6
5
4
3
2
1
0
I2C General Address Write (Master)
1
0
0
0
0
0
0
0
Step 3
9
I2C Acknowledge (Slave)
A
Step 4
7
6
5
4
3
2
1
0
I2C Logic Address (Master)
0
0
0
0
0
0
0
0
Step 5
9
I2C Acknowledge (Slave)
A
Step 6
0
I2C Stop (Master)
P
Step 7
0
I2C Start (Master)
S
Step 8
7
6
5
4
3
2
1
0
I2C General Address Read (Master)
1
0
0
0
0
0
0
1
Step 9
9
I2C Acknowledge (Slave)
A
Step 10
7
6
5
4
3
2
1
0
I2C Read Data (Slave)
Data
Data
Data
Data
Data
Data
Data
Data
Where Data is determined by the Logic values Contained in the Sink Port Register
Step 11
9
I2C Not-Acknowledge (Master)
X
Where X is an A (Acknowledge) or A (Not-Acknowledge)
An A causes the pointer to increment and step 10 is repeated.
An A causes the slave to stop transmitting and proceeds to step 12.
Step 12
0
I2C Stop (Master)
P
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PACKAGE OPTION ADDENDUM
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14-Apr-2009
PACKAGING INFORMATION
Orderable Device
SN75DP139RGZR
SN75DP139RGZT
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RGZ
48
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
QFN
RGZ
48
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jul-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN75DP139RGZR
SN75DP139RGZT
QFN
QFN
RGZ
RGZ
48
48
2500
250
330.0
180.0
16.4
16.4
7.3
7.3
7.3
7.3
1.5
1.5
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jul-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN75DP139RGZR
SN75DP139RGZT
QFN
QFN
RGZ
RGZ
48
48
2500
250
346.0
190.5
346.0
212.7
33.0
31.8
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
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TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
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TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Military
Optical Networking
Security
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
www.ti.com/audio
Data Converters
DLP® Products
DSP
Clocks and Timers
Interface
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Logic
Power Mgmt
Microcontrollers
RFID
Telephony
Video & Imaging
Wireless
RF/IF and ZigBee® Solutions www.ti.com/lprf
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2009, Texas Instruments Incorporated
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