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SN65DP159, SN75DP159

ZHCSE15F –JULY 2015–REVISED MAY 2018

SNx5DP159 6Gbps 交流耦合 TMDS™ 转 HDMI™ 电平转换器重定时器

1 特性

3 说明

1

•

交流耦合 TMDS 或 DisplayPort 双模物理电平输入

到 HDMI2.0a TMDS 物理电平输出支持高达 6Gbps

的数据速率且与 HDMI2.0a 电气参数兼容

SNx5DP159 器件是一款双模[1] DisplayPort 转最小化

传输差分信号 (TMDS) 重定时器，支持数字视频接口

(DVI) 1.0 以及高清多媒体接口 (HDMI) 1.4b 和 2.0 输

出信号。SNx5DP159 器件通过 DDC 链路或 AUX 通

道支持双模标准版本 1.1 的 1 类和 2 类应用。

SNx5DP159 器件的每条数据信道支持的数据速率高达

6Gbps，可支持超高清 (4K × 2K/60Hz) 8 位彩色高分

辨率视频和 1080p 16 位色深的高清电视 (1920 ×

1080/60Hz)。SNx5DP159 器件在数据速率低于

1Gbps 时可自动配置为转接驱动器，在超过该数据速

率后可自动配置为重定时器。此特性可通过 I²C[4] 编

程来关闭。

•

支持 DisplayPort 双模标准版本 1.1

高达 16.5dB 的自适应接收器均衡器和可编程固定

均衡器

•

高速通道控制、预加重和发送摆幅以及转换率控制

I²C 或引脚搭接可编程

支持 2 类 I2C-over-AUX 转 DDC 电桥

集成了 TMDS 电平转换器和时钟和数据恢复

(CDR) 功能

有源 I²C[4] 缓冲器

主信道输入交换

低功耗

•

为确保信号完整性，SNx5DP159 器件实现了多个特

性。SNx5DP159 接收器支持自适应和固定均衡，以便

消除电路板走线或电缆因带宽受限而引起的码间串扰

(ISI) 抖动或损耗。用作重定时器时，内置的时钟数据

恢复 (CDR) 功能可清除输入端高频和视频源的随机抖

动。发送器提供多种功能不仅有利于达到合规要求，

还能够减少系统设计问题，例如去加重功能可补偿驱动

长电缆或高损耗电路板走线时的衰减。SNx5DP159 器

件还包含使用 Vsadj 引脚上的外部电阻器实现的

TMDS 输出幅值调节功能，以及源端选择功能和输出

转换速率控制功能。器件的运行和配置可通过引脚设置

或 I²C[4] 编程。

低功耗

–

6Gbps 时的工作功耗为 435mW，关断状态下的

功耗为 10mW

•

面向商业和工业应用的扩展温度器件选项

采用 40 引脚、0.4mm 间距、5mm x 5mm WQFN

封装，与 TPD158 转接驱动器引脚兼容

•

40 引脚、0.5mm 间距、7mm x 7mm VQFN 封装

2 应用

•

笔记本、台式机、一体机、平板电脑、游戏机和工

业电脑

•

音频/视频设备

Blu-Ray™DVD

游戏系统

SNx5DP159 器件采用多种方法来进行电源管理和降低

有功功率。

器件信息⁽¹⁾

HDMI 适配器或软件狗

扩展基座

器件型号

SN65DP159

封装

VQFN (48)

WQFN (40)

封装尺寸（标称值）

7.00mm × 7.00mm

5.00mm x 5.00mm

SN75DP159

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

DP159 母板应用结构

DP159 软件狗应用结构

GPU

Dongle

DP++

HDMI

Monitor

TDP158

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLLSEJ2

SN65DP159, SN75DP159

ZHCSE15F –JULY 2015–REVISED MAY 2018

www.ti.com.cn

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）.............................................................. 4

Pin Configuration and Functions......................... 4

Specifications......................................................... 7

7.1 Absolute Maximum Ratings ...................................... 7

7.2 ESD Ratings.............................................................. 7

7.3 Recommended Operating Conditions....................... 8

7.4 Thermal Information.................................................. 8

7.5 Power Supply Electrical Characteristics ................... 9

7.6 Differential Input Electrical Characteristics ............. 10

9

Detailed Description ............................................ 24

9.1 Overview ................................................................. 24

9.2 Functional Block Diagram ....................................... 24

9.3 Feature Description................................................. 25

9.4 Device Functional Modes........................................ 31

9.5 Register Maps......................................................... 32

10 Application and Implementation........................ 40

10.1 Application Information.......................................... 40

10.2 Typical Application ................................................ 45

10.3 System Example ................................................... 47

11 Power Supply Recommendations ..................... 48

11.1 Power Management.............................................. 48

12 Layout................................................................... 49

12.1 Layout Guidelines ................................................. 49

12.2 Layout Examples................................................... 50

12.3 Thermal Considerations........................................ 51

13 器件和文档支持 ..................................................... 52

13.1 相关链接................................................................ 52

13.2 文档支持................................................................ 52

13.3 接收文档更新通知 ................................................. 52

13.4 社区资源................................................................ 52

13.5 商标....................................................................... 52

13.6 静电放电警告......................................................... 52

13.7 术语表 ................................................................... 52

14 机械、封装和可订购信息....................................... 52

7.7 HDMI and DVI TMDS Output Electrical

Characteristics ......................................................... 11

7.8 AUX, DDC, and I²C Electrical Characteristics ........ 12

7.9 HPD Electrical Characteristics ................................ 12

7.10 HDMI and DVI Main Link Switching

Characteristics ......................................................... 13

7.11 AUX Switching Characteristics (Only for RGZ

Package).................................................................. 15

7.12 HPD Switching Characteristics ............................. 15

7.13 DDC and I²C Switching Characteristics................ 15

7.14 Typical Characteristics.......................................... 16

Parameter Measurement Information ................ 16

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision E (April 2018) to Revision F

Page

•

将“SN75DP159 的工作温度范围为 –40°C 至 85°C”更改为“SN65DP159 的工作温度范围为 –40°C 至 85°C”（说明

（续）） ................................................................................................................................................................................. 4

将“SN65DP159 的工作温度范围为 0°C 至 85°C”更改为“SN75DP159 的工作温度范围为 0°C 至 85°C”（说明（续））..... 4

Changes from Revision D (June 2017) to Revision E

Page

•

Changed the pinout images appearance in the Pin Configuration and Functions section..................................................... 4

Changes from Revision C (July 2016) to Revision D

Page

•

将标题从“SNx5DP159 6-Gbps DP++ 到 HDMI 重定时器”更改为“SNx5DP159 6-Gbps 交流耦合 TMDS™ 到 HDMI™

电平转换器重定时器” .............................................................................................................................................................. 1

更改了特性列表....................................................................................................................................................................... 1

更改了应用列表...................................................................................................................................................................... 1

•

V_SADJ: Added Note: "Best transmit eye ..", added MIN and MAx values in the Recommended Operating Conditions

table ....................................................................................................................................................................................... 8

•

Changed the description of t_d1in 表 1 .................................................................................................................................. 26

Changed read procedures in the I²C Control Behavior section ........................................................................................... 34

Added paragraph: "DP159 is designed..." to the Application and Implementation section.................................................. 40

Added 2 paragraphs to the Application Information section................................................................................................. 40

2

SN65DP159, SN75DP159

www.ti.com.cn

ZHCSE15F –JULY 2015–REVISED MAY 2018

•

Added line item "Adding pre-emphasis will improve..." to the Detailed Design Procedure section ..................................... 46

Changes from Revision B (Arpil 2016) to Revision C

Page

•

Recommended Operating Conditions, Changed the CONTROL PINS section ..................................................................... 8

Changed the AUX, DDC, and I²C Electrical Characteristics table ....................................................................................... 12

Added text to 图 31 Note: "The SCL_SRC and SDA_SRC pins must be pulled to ground."............................................... 42

Changes from Revision A (July 2015) to Revision B

Page

•

Added "Low-level input voltage at OE" to V_ILin the Recommended Operating Conditions table.......................................... 8

Added OE to V_IH"High-level input voltage" in the Recommended Operating Conditions table ............................................ 8

Changed 图 22 .................................................................................................................................................................... 25

Deleted the VDD_ramp and VCC_ramp MIN values in 表 1 ............................................................................................... 26

Changed text "through the I²C interface" To: "through the I²C access on the DDC interface" in DDC Functional

Description............................................................................................................................................................................ 31

•

Changed the HDMI and DVI value for 1Ah 表 3 ................................................................................................................. 32

Added Note to 11–400-kbps in 表 7 .................................................................................................................................... 36

Changed the note in the DEV_FUNC_MODE section of 表 7.............................................................................................. 36

Changed Note in the DDC_TRAIN_SET section of 表 8 ..................................................................................................... 37

Changes from Original (July 2015) to Revision A

Page

•

将器件状态从“产品预览”更新为“生产数据”.............................................................................................................................. 1

更新了典型电源数................................................................................................................................................................... 1

删除了备用电源数................................................................................................................................................................... 1

将“预览”更改为“生产数据” ....................................................................................................................................................... 1

Replaced SIG_EN with NC in pinout drawing and Pin Functions table ................................................................................. 4

Removed lane swap from description of SWAP/POL = H .................................................................................................... 7

Updated swing data ............................................................................................................................................................... 8

Changed DDC link into its pin names between SNK and SRC and updated min value ....................................................... 8

Added new line for SCL_SNK, SDA_SNK ............................................................................................................................. 8

Removed standby power and standby current rows and updated active power and current numbers ................................ 9

Changed term control to no source termination .................................................................................................................. 11

Increased I_LEAKmax value from 10 µA to 45 µA................................................................................................................... 11

Updated redriver mode max jitter value .............................................................................................................................. 13

Clarified polarity swap to input signals ................................................................................................................................ 27

Added more information on compliance in redriver mode ................................................................................................... 31

Added note to DDC Functional Description section describing DDC snoop function ......................................................... 31

Removed bit 4 SIG_EN and made reserved ....................................................................................................................... 36

Removed SIG_EN Pin and added Note 1 for DDC Snoop ................................................................................................. 42

Updated schematic to replace SIG_EN pin with NC ........................................................................................................... 43

Updated VID swing .............................................................................................................................................................. 46

Changed Title to better match table. Removed Standby and redundant rows .................................................................... 48

Updated drawing with pin 17 changed to NC ...................................................................................................................... 51

3

SN65DP159, SN75DP159

ZHCSE15F –JULY 2015–REVISED MAY 2018

www.ti.com.cn

5 说明（续）

SNx5DP159 接收器使用多种方法来确定应用支持 HDMI1.4b[2] 还是 HDMI2.0[3] 数据速率。SNx5DP159 接收器

采用两种封装：40 引脚 RSB 封装（支持空间受限的应用）和 48 引脚 RGZ 封装（支持软件狗等应用中

DisplayPort 双模标准版本 1.1 的全部特性）。

SN65DP159 器件可在 –40°C 至 85°C 的工业级温度范围内运行。

SN75DP159 器件可在 0°C 至 85°C 的扩展商业级温度范围内运行。

6 Pin Configuration and Functions

RGZ Package

48-Pin VQFN

Top View

SWAP/POL

IN_D2p

1

36

35

34

33

32

31

30

29

28

27

26

25

TX_TERM_CTL

OUT_D2p

OUT_D2n

HPD_SNK

OUT_D1p

OUT_D1n

GND

2

IN_D2n

3

HPD_SRC

IN_D1p

4

5

IN_D1n

6

Thermal

Pad

GND

7

IN_D0p

8

OUT_D0p

OUT_D0n

HDMI_SEL/A1

OUT_CLKp

OUT_CLKn

IN_D0n

9

I2C_EN/PIN

IN_CLKp

IN_CLKn

10

11

12

Not to scale

4

SN65DP159, SN75DP159

www.ti.com.cn

ZHCSE15F –JULY 2015–REVISED MAY 2018

RSB Package

40-Pin WQFN

Top View

IN_D2p

IN_D2n

1

2

3

4

5

6

7

8

9

10

30

29

28

27

26

25

24

23

22

21

OUT_D2p

OUT_D2n

HPD_SNK

OUT_D1p

OUT_D1n

OUT_D0p

OUT_D0n

HDMI_SEL/A1

OUT_CLKp

OUT_CLKn

HPD_SRC

IN_D1p

IN_D1n

Thermal

Pad

IN_D0p

IN_D0n

I2C_EN/PIN

IN_CLKp

IN_CLKn

Not to scale

Pin Functions

PIN⁽¹⁾

I/O

DESCRIPTION⁽²⁾

SIGNAL NAME

RGZ

RSB

MAIN LINK INPUT PINS (FAIL SAFE)

IN_D2p

IN_D2n

IN_D1p

IN_D1n

IN_D0p

IN_D0n

IN_CLKp

IN_CLKn

2

3

1

2

I

Channel 2 differential input

Channel 1 differential input

Channel 0 differential input

Clock differential input

5

4

6

5

8

6

9

7

11

12

9

10

MAIN LINK OUTPUT PINS (FAIL SAFE)

OUT_D2n

OUT_D2p

OUT_D1n

OUT_D1p

34

35

31

32

29

30

26

27

O

TMDS data 2 differential output

TMDS data 1 differential output

(1) Blue pin names are only in the SNx5DP159 RGZ package.

(2) (H) Logic high (pin strapped to VCC through 65-kΩ resistor); (L) logic low (pin strapped to GND through 65-kΩ resistor); (for mid-level,

no connect)

5

SN65DP159, SN75DP159

ZHCSE15F –JULY 2015–REVISED MAY 2018

www.ti.com.cn

Pin Functions (continued)

PIN⁽¹⁾

I/O

O

DESCRIPTION⁽²⁾

SIGNAL NAME

OUT_D0n

RGZ

28

RSB

24

TMDS data 0 differential output

OUT_D0p

29

25

OUT_CLKn

25

21

O

TMDS data clock differential output

OUT_CLKp

26

22

HOT PLUG DETECT PINS

HPD_SRC

4

3

O

Hot plug detect output

HPD_SNK

33

28

I (Failsafe)

Hot plug detect input

AUXILIARY/DDC DATA PINS

AUX_SRCp

AUX_SRCn

SDA_SRC

45

N/A

39

Source side bidirectional DisplayPort auxiliary for I²C-over-AUX (DP159RGZ only)

I/O

44

47

46

39

38

I/O (Failsafe) Source side TMDS port bidirectional DDC data line

I/O (Failsafe) Sink side TMDS port bidirectional DDC data lines

SCL_SRC

38

SDA_SNK

33

SCL_SNK

32

CONTROL PINS

Operation enable/reset pin

OE = L: Power-down mode

OE = H: Normal operation

OE

42

36

I

Internal weak pullup: Resets device when transitions from H to L

(1)

NC

17

18

N/A

I

No connect

(1)

CEC_EN

O

CEC control pin for Dongle applications

Slew rate control when I2C_EN/PIN = Low.

SLEW_CTL = H, fastest data rate

SLEW_CTL = L, 5 ps slow

SLEW_CTL = No Connect, 10 ps slow

When I2C_EN/PIN = High Slew rate is controlled through I²C[4]

I

3

level

SLEW_CTL

PRE_SEL

40

20

34

16

(2)

De-emphasis pin strap when I2C_EN/PIN = Low.

PRE_SEL = L: - 2 dB de-emphasis

PRE_SEL = No Connect: 0 dB

I

3

level

PRE_SEL = H: Reserved

Input Receive Equalization pin strap when I2C_EN/PIN = Low

EQ_SEL = L: Fixed EQ at 7.5 dB

EQ_SEL = No Connect: Adaptive EQ

EQ_SEL = H: Fixed at 14 dB

When I2C_EN/PIN = High

I

3

level

EQ_SEL/A0

21

17

(2)

Address bit 1

Note: (3 level for pin strap programming but 2 level when I²C[4] address)

I2C_EN/PIN = High; puts device into I²C control mode

I2C_EN/PIN = Low; puts device into pin strap mode

I2C_EN/PIN

SCL_CTL

10

15

8

I

I²C clock signal

13

Note: When I2C_EN/PIN = Low Pin strapping take priority and those functions cannot be

changed by I²C

I²C data signal

SDA_CTL

Vsadj

16

22

14

18

I/O

I

Note: When I2C_EN/PIN = Low Pin strapping take priority and those functions cannot be

changed by I²C

TMDS-compliant voltage swing control nominal resistor to GND

HDMI_SEL when I2C_EN/PIN = Low

HDMI_SEL = High: Device configured for DVI

HDMI_SEL = Low: Device configured for HDMI (Adaptor ID block is readable through I²C[4]

or I²C-over-AUX.

When I2C_EN/PIN = High

Address bit 2

HDMI_SEL/A1

27

36

23

I

Note: Weak internal pull down

Transmit Termination Control when I2C_EN/PIN = Low

TX_TERM_CTL = H, No transmit termination

TX_TERM_CTL = L, Transmit termination impedance in 75 to about 150 Ω

TX_TERM_CTL = No Connect, automatically selects the termination impedance

Data rate (DR) > 3.4 Gbps – 75- to 150-Ω differential near end termination

2 Gbps < DR < 3.4 Gbps – 150- to 300-Ω differential near end termination

DR < 2 Gbps – no termination

I

3

level

(1)

TX_TERM_CTL

N/A

(2)

Note: If left floating will be in automatic select mode.

6

SN65DP159, SN75DP159

www.ti.com.cn

SIGNAL NAME

ZHCSE15F –JULY 2015–REVISED MAY 2018

Pin Functions (continued)

PIN⁽¹⁾

I/O

DESCRIPTION⁽²⁾

RGZ

RSB

Input lane SWAP and polarity control pin when I2C_EN/PIN = Low

SWAP/POL = H receive lane polarity swap (retimer mode only)

SWAP/POL = L receive lanes swap (retimer and redriver mode)

SWAP/POL = No Connect normal working

I

3

level

(1)

SWAP/POL

1

N/A

(2)

SUPPLY AND GROUND PINS

V_CC

V_DD

13, 43

11, 37

P

3.3-V power supply

1.1-V power supply

14, 23, 24, 12, 19, 20,

37, 48

31, 40

7, 19, 41,

30,

GND

15, 35

G

Ground

Thermal Pad

Connected to ground

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)

(1)(2)

MIN

–0.3

MAX

4

UNIT

V

V_CC

Supply voltage⁽³⁾

V_DD

1.4

V

Main link input (IN_Dx AC-coupled mode), AUX_SRCp, AUX_SRCn

differential voltage

1.56

V

TMDS outputs ( OUT_Dx)

–0.3

4

6

Voltage

HPD_SRC, Vsadj, SDA_CTL, SCL_CTL, OE, HDMI_SEL/A1, EQ_SEL/A0,

I2C_EN/PIN, SLEW_CTL, TX_TERM_CTL, SDA_SRC, SCL_SRC

HPD_SNK, SDA_SNK, SCL_SNK

Continuous power dissipation

Storage temperature, T_stg

See Thermal Information

–65 150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential voltages, are with respect to network ground terminal.

(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

V

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7

SN65DP159, SN75DP159

ZHCSE15F –JULY 2015–REVISED MAY 2018

www.ti.com.cn

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

GENERAL PARAMETERS

V_CC

3

3.3

1.1

3.6

1.27

93.5

92.7

85

Supply voltage

V_DD

V

1.00

T_CASE

Case temperature for RSB package

Case temperature for RGZ package

°C

SN75DP159

0

T_A

Operating free-air temperature

°C

SN65DP159

–40

85

MAIN LINK DIFFERENTIAL PINS

V_{ID_PP}

Peak-to-peak input differential voltage

75

0

1200

2

mv

V

V_IC

Input common mode voltage

AC coupling capacitance

Data rate

C_AC

75

100

200

5

nF

d_R

0.25

4.5

Gbps

kΩ

(1)

V_SADJ

TMDS-compliant swing voltage bias resistor

7.06

7.5

CONTROL PINS

V_I-DC

DC input voltage

Control pins

–0.3

3.6

0.8

V

Low-level input voltage at OE

(2)

V_IL

Low-level input voltage at SLEW_CTL, PRE_SEL, EQ_SEL/A0, TX_TERM_CTL,

SWAP/POL

0.3

1.4

No connect input voltage at SLEW_CTL, PRE_SEL, EQ_SEL/A0, TX_TERM_CTL,

SWAP/POL

High-level input voltage at SLEW_CTL, OE⁽³⁾, PRE_SEL, EQ_SEL/A0,

TX_TERM_CTL, SWAP/POL

(2)

V_IM

1

1.2

V

(2)

V_IH

2.6

V_OL

V_OH

I_IH

Low-level output voltage

High-level output voltage

High-level input current

0.4

V

2.4

–30

–10

–50

30

10

µA

mA

µA

kΩ

I_IL

Low-level input current

I_OS

Short circuit output current

High impedance output current

Pullup resistance on OE pin

50

I_OZ

10

R_OEPU

150

250

(1) Best transmit eye with minimum intra-pair skew, largest vertical and horizontal eye opening, maintaining HDMI compliant output swing

can be achieved with resistors around 6.4k. Using smaller resistors may lead to compliance failures.

(2) These values are based upon a microcontroller driving the control pins. The pullup/pulldown/floating resistor configuration will set the

internal bias to the proper voltage level which will not match the values shown here.

(3) This value is based upon a microcontroller driving the OE pin. A passive reset circuit using an external capacitor and the internal pullup

resistor will set OE pin properly, but may have a different value than shown due to internal biasing.

7.4 Thermal Information

SNx5DP159

RGZ (VQFN)

48 PINS

31.1

SNx5DP159

THERMAL METRIC⁽¹⁾

RSB (WQFN)

UNIT

40 PINS

37.3

23.1

9.9

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance (High-K board⁽²⁾

Junction-to-board thermal resistance (High-K board⁽²⁾

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

°C/W

R_θJC(top)

R_θJB

)

18.2

)

8.1

ψ_JT

0.4

0.3

ψ_JB

8.1

3.8

R_θJC(bot)

3.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Test conditions for Ψ_JBand Ψ_JTare clarified in TI document Semiconductor and IC Package Thermal Metrics.

8

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ZHCSE15F –JULY 2015–REVISED MAY 2018

7.5 Power Supply Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾MAX⁽²⁾UNIT

OE = H, V_CC= 3.3 V/3.6 V, V_DD= 1.1 V/1.27 V

Device power dissipation IN_Dx: V_{ID_PP}= 1200 mV, 6Gbps TMDS pattern, V_I= 3.3 V,

P_D1

435

600

mW

(Retimer operation)

I2C_EN/PIN = L, PRE_SEL= H, EQ_CTL= H,

SDA_CTL/CLK_CTL = 0 V, VSadj = 7.06 kΩ

OE = H, V_CC= 3.3 V/3.6 V, V_DD= 1.1 V/1.27 V

Device power dissipation IN_Dx: V_{ID_PP}= 1200 mV, 6Gbps TMDS pattern, V_I= 3.3 V,

P_D2

215

10

400

30

mW

(Redriver operation)

I2C_EN/PIN = L, PRE_SEL= H, EQ_CTL= H,

SDA_CTL/CLK_CTL = 0 V, VSadj = 7.06 kΩ

Device power in power

down

OE = L, V_CC= 3.3 V/3.6 V, V_DD= 1.1 V/1.27 V, VSadj = 7.06

kΩ

P_SD1

OE = H, V_CC= 3.3 V/3.6 V, V_DD= 1.1V/1.27 V, VSadj = 7.06

kΩ

IN_Dx: VID_PP = 1200 mV, 6Gbps TMDS pattern

I2C_EN/PIN = L, PRE_SEL = H, EQ_CTL = H,

SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H

VCC supply current

(TMDS 6Gpbs retimer

mode)

I_CC1

I_DD1

I_CC2

I_DD2

35

295

8

50

325

20

mA

OE = H, V_CC= 3.3 V/3.6 V, V_DD= 1.1 V/1.27 V, VSadj = 7.06

kΩ

IN_Dx: V_{ID_PP}= 1200 mV, 6Gbps TMDS pattern

I2C_EN/PIN = L, PRE_SEL = H, EQ_CTL = H,

SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H

VDD supply current

(TMDS 6Gpbs retimer

mode)

OE = H, V_CC= 3.3 V/3.465 V, V_DD= 1.1 V/1.27 V, VSadj =

7.06 kΩ

IN_Dx: V_{ID_PP}= 1200 mV, 6Gbps TMDS pattern

I2C_EN/PIN = L, PRE_SEL = H, EQ_CTL = H,

SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H

VCC supply current

(TMDS 6Gpbs redriver

mode)

OE = H, V_CC= 3.3 V/3.465 V, V_DD= 1.1 V/1.27 V, VSadj =

7.06 kΩ

IN_Dx: V_{ID_PP}= 1200 mV, 6Gbps TMDS pattern

I2C_EN/PIN = L, PRE_SEL = H, EQ_CTL = H,

SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H

VDD supply current

(TMDS 6Gpbs redriver

mode)

170

250

mA

OE = L, V_CC= 3.3 V/3.465 V, V_DD

3.3-V rail

I_SD1

Power-down current

2

5

= 1.1 V/1.27 V, VSadj = 7.06 kΩ

OE = L, V_CC= 3.3 V/3.465 V, V_DD

1.1-V rail

3.5

10

= 1.1 V/1.27 V, VSadj = 7.06 kΩ

(1) The typical rating is simulated at 3.3-V V_CCand 1.1-V V_DDand at 27°C temperature unless otherwise noted

(2) The maximum rating is simulated at 3.6-V V_CCand 1.27-V V_DDand at 85°C temperature unless otherwise noted

9

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MAX UNIT

7.6 Differential Input Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

0.25

25

TYP

D_{R_RX_DATA}Ddata lanes data rate

6

340

60%

0.3

Gbps

MHz

D_{R_RX_CLK}

t_{RX_DUTY}

t_{CLK_JIT}

Clock lanes clock rate

Input clock duty circle

Input clock jitter tolerance

Input data jitter tolerance

40%

50%

Tbit

ps

t_{DATA_JIT}

Test the TTP2, see 图 10

150

Test at TTP2 when DR = 1.6-Gbps, see 图

10

T_{RX_INTRA}

T_{RX_INTER}

E_QH(D)

Input intra-pair skew tolerance

Input inter-pair skew tolerance

112

ps

ns

dB

1.8

Fixed EQ gain for data lane

IN_D(0,1,2)n/p

EQ_SEL/A0 = H; Fixed EQ gain,

test at 6-Gbps

15

Fixed EQ gain for data lane

IN_D(0,1,2)n/p

EQ_SEL/A0 = L; Fixed EQ gain,

test at 6-Gbps

E_QL(D)

E_QZ(D)

7.5

dB

Adaptive EQ gain for data lane

IN_D(0,1,2)n/p

EQ_SEL/A0 = Z; adaptive EQ

EQ_SEL/A0 = H,L,NC

2

15

E_Q(c)

EQ gain for clock lane IN_CLKn/p

Input differential termination impedance

Input termination voltage

3

100

0.7

R_INT

80

75

120

Ω

V_ITERM

V_{ID_PP}

OE = H

V

Input differential voltage (peak to peak)

Tested at TTP2, check 图 10

1200 mV_PP

10

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ZHCSE15F –JULY 2015–REVISED MAY 2018

7.7 HDMI and DVI TMDS Output Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Data rate ≤ 1.65-Gbps; PRE_SEL =

NC; TX_TERM_CTL = H;

SLEW_CTL = H; OE = H; DR = 750-

Mbps, VSadj = 7.06-kΩ

V_CC– 10

V_CC+ 10

V_OH

V_OL

Single-ended high level output voltage

mV

1.65-Gbps < Data rate ≤ 3.4-Gbps;

PRE_SEL = NC; TX_TERM_CTL =

H; SLEW_CTL = H; OE = H; DR =

2.97-Gbps, VSadj = 7.06-kΩ

V_CC– 200

V_CC– 400

V_CC– 600

V_CC– 700

V_CC– 1000

400

V_CC+ 10

V_CC– 400

600

3.4-Gbps < Data rate < 6 Gbps;

PRE_SEL = NC; TX_TERM_CTL = L;

SLEW_CTL = H; OE = H; DR = 6-

Gbps, VSadj = 7.06-kΩ

Single-ended high level output voltage

Single-ended low level output voltage

Data rate ≤ 1.65-Gbps; PRE_SEL =

NC; TX_TERM_CTL = H;

SLEW_CTL = H; OE = H; DR = 750-

Mbps, VSadj = 7.06-kΩ

1.65-Gbps < Data rate ≤ 3.4-Gbps;

PRE_SEL = NC; TX_TERM_CTL =

H; SLEW_CTL = H; OE = H; DR =

2.97-Gbps, VSadj = 7.06-kΩ

3.4-Gbps < Data rate < 6-Gbps;

PRE_SEL = NC; TX_TERM_CTL = L;

SLEW_CTL = H; OE = H; DR = 6-

Gbps

V_OL

mV

PRE_SEL = NC; TX_TERM_CTL =

H/NC/L; SLEW_CTL = H; OE = H;

DR = 270-Mbs/2.97/6Gbps VSadj =

7.06-kΩ

Single-ended output voltage swing on

data lane

V_{SWING_DA}

500

Data rate ≤ 3.4-Gbps; PRE_SEL =

NC; TX_TERM_CTL = H;

SLEW_CTL = H; OE = H; VSadj =

7.06-kΩ

400

600

Single-ended output voltage swing on

clock lane

V_{SWING_CLK}

mV

Data rate > 3.4-Gbps; PRE_SEL =

NC; TX_TERM_CTL = NC;

SLEW_CTL = H; OE = H; VSadj =

7.06-kΩ

200

300

20

400

Change in single-end output voltage

swing per 100 Ω ΔVsadj

ΔV_SWING

ΔV_OCM(SS)

V_OD(PP)

mV

Change in steady state output common

mode voltage between logic levels

–5

800

600

5

1200

1050

Output differential voltage before pre-

emphasis

Vsadj = 7.06-kΩ; PRE_SEL = Z, See

图 8

Vsadj = 7.06-kΩ; PRE_SEL = L, See

图 9

V_OD(SS)

Steady-state output differential voltage

V_CC= 0-V; V_DD= 0-V; output pulled

to 3.3 V through 50-Ω resistors

I_LEAK

I_OS

Failsafe condition leakage current

Short circuit current limit

45

50

µA

mA

Ω

Main link output shorted to GND

Source termination resistance for HDMI

2.0

R_TERM

75

150

11

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ZHCSE15F –JULY 2015–REVISED MAY 2018

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7.8 AUX, DDC, and I²C Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

pF

C_IO

Input capacitance

AUX data rate = 1-MHz

10

C_AC

AUX AC coupling capacitance

Data rate of the AUX channel input

75

200

1.2

nF

D_R(AUX)

0.8

1

Mbps

DC input voltage on AUX channel,

AUX_SRCp/n: 100-kΩ pull up to 3.6 V

but differential common mode is 2 V

or less.

V_I-DC(AUX)

-0.5

3.6

V

Peak-to-peak differential voltage at

TX pins

V_{AUX_DIFF_PP_TX}

V_{AUX_DIFF_PP_RX}

V_{AUX_DC_CM}

I_{AUX_SHORT}

V_I-DC

V_{AUX_DIFF_PP}= 2 × |V_AUXP– V_AUXN

|

0.29

0.14

0

1.38

1.36

2

V

Peak-to-peak differential voltage at

RX pins

AUX channel DC common mode

voltage

AUX channel short circuit current limit

SCL/SDA_SNK DC input voltage

90

mA

V

–0.3

-0.3

5.6

SCL/SDA_CTL, SCL/SDA_SRC DC

input voltage

3.6

0.3 x V_CC

V

SCL/SDA_SNK, SCL/SDA_SRC Low

level input voltage

V_IL

SCL/SDA_CTL Low level input

voltage

SCL/SDA_SNK high level input

voltage

3

0.7 x V_CC

SCL/SDA_SRC high level input

voltage

V_IH

SCL/SDA_CTL high level input

voltage

I₀= 3-mA and V_CC> 2-V

I₀= 3-mA and V_CC< 2-V

0.4

V

SCL/SDA_CTL, SCL/SDA_SRC low-

level output voltage

V_OL

0.2 V_CC

SCL clock frequency fast I2C mode

for local I2C control

f_SCL

400

kHz

pF

Total capacitive load for each bus line

(DDC and local I2C pins)

C_bus

7.9 HPD Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

V_IH

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

Failsafe condition leakage current

HPD_SNK

2.1

V_IL

HPD_SNK

0.8

3.6

0.1

40

V

V_OH

V_OL

I_LEAK

I_OH= –500-µA; HPD_SRC

I_OL= 500-µA; HPD_SRC

VCC = 0-V; V_DD= 0-V; HPD_SNK = 5-V

2.4

0

V

μA

Device powered; V_IH= 5-V;

I_{H_HPD}includes R_pdHPDresistor current

I_{H_HPD}

High-level input current

40

μA

Device powered; V_IL= 0.8-V;

I_{L_HPD}includes R_pdHPDresistor current

I_{L_HPD}

Low-level input current

30

R_pdHPD

HPD input termination to GND

V_CC= 0-V

150

190

220

kΩ

12

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ZHCSE15F –JULY 2015–REVISED MAY 2018

7.10 HDMI and DVI Main Link Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

REDRIVER MODE

D_R

Data rate (Automatic Mode)

250

1000 Mbps

6000 Mbps

D_R

Data rate (full redriver mode)

t_PLH

t_PHL

Propagation delay time (low to high)

Propagation delay time (high to low)

600

800

ps

SLEW_CTL = H; TX_TERM_CTL = L;

PRE_SEL = NC; OE = H; DR = 6 Gbps

t_T1

t_T2

45

65

Transition time (rise and fall time);

measured at 20% and 80% levels for data

lanes. TMDS clock meets t_T3for all three

times.

SLEW_CTL = L; TX_TERM_CTL = NC;

PRE_SEL = NC; OE = H; DR = 6 Gbps

ps

SLEW_CTL = NC; TX_TERM_CTL =

NC; PRE_SEL = NC; OE = H; DR = 6

Gbps; CLK 150MHz

t_T3

100

SLEW_CTL = NC; TX_TERM_CTL =

NC; PRE_SEL = NC; OE = H; DR = 6

Gbps;

t_SK1(T)

Intra-pair output skew

Inter-pair output skew

40

ps

SLEW_CTL = NC; TX_TERM_CTL =

NC; PRE_SEL = NC; OE = H; DR = 6

Gbps;

t_SK2(T)

100

DR = 2.97 Gbps, HDMI_SEL/A1 = NC,

EQ_SEL/A0 = NC; PRE_SEL = NC;

SLEW_CTL = H OE = H.

t_JITD1(1.4b)

Total output data jitter

0.2

Tbit

See 图 10 at TTP3

3.4Gbps < Rbit ≤ 3.712Gps SLEW_CTL

= H; TX_TERM_CTL = NC; PRE_SEL =

NC; OE = H

0.4

-0.033

2Rbit2

+0.23

12

Rbit +

0.1998

3.712Gbps < Rbit < 5.94Gbps

SLEW_CTL = H; TX_TERM_CTL = NC;

PRE_SEL = NC; OE = H

t_JITD1(2.0)

Total output data jitter

Tbit

5.94Gbps ≤ Rbit ≤ 6.0Gbps SLEW_CTL

= H; TX_TERM_CTL = NC; PRE_SEL =

NC; OE = H

0.8

t_JITC1(1.4b)

Total output clock jitter

CLK = 297 MHz

0.25

0.3

Tbit

t_JITC1(2.0)

DR = 6Gbps: CLK = 150 MHz

RETIMER MODE

d_R

Data rate (Full retimer mode)

Data rate (Automatic mode)

0.25

1.0

6

Gbps

Measured with input signal applied from

0 to 200 mVpp

d_XVR

Automatic redriver to retimer crossover

.75

1.0

1.25 Gbps

MHz

f_CROSSOVER

P_LLBW

Crossover frequency hysteresis

Data retimer PLL bandwidth

250

.4

Default loop bandwidth setting

1

MHz

Input clock frequency detection and retimer

acquisition time

t_ACQ

I_JT1

t_T1

180

μs

Input clock jitter tolerance

Tested when data rate > 1.0 Gbps

0.3

Tbit

SLEW_CTL = H; TX_TERM_CTL = L;

PRE_SEL = NC; OE = H; DR = 6 Gbps

45

65

Transition time (rise and fall time);

measured at 20% and 80% levels for data

lanes. TMDS clock meets t_T3for all three

times.

SLEW_CTL = L; TX_TERM_CTL = NC;

PRE_SEL = NC; OE = H; DR = 6 Gbps

t_T2

ps

SLEW_CTL = NC; TX_TERM_CTL =

NC; PRE_SEL = NC; OE = H; DR = 6

Gbps; CLK = 150 MHz

t_T3

100

t_DCD

OUT_CLK ± duty cycle

40%

50%

60%

13

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MAX UNIT

HDMI and DVI Main Link Switching Characteristics (接下页)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

t_{SK_INTER}

t_{SK_INTRA}

t_JITC1(1.4b)

t_JITC1(2.0)

0.2

0.15

0.25

0.3

Tch

Tbit

Default setting for internal inter-pair skew

adjust, HDMI_SEL/A1 = NC

Inter-pair output skew

Total output clock jitter

CLK = 297 MHz

DR = 6Gbps: CLK = 150 MHz

3.4 Gbps < R_bit≤ 3.712 Gbps

0.4

See

t_JITD2

Total output data jitter

3.712 Gbps < R_bit< 5.94 Gbps

Tbit

mV

(1)

5.94 Gbps ≤ R_bit≤ 6.0 Gbps

3.4 Gbps < R_bit≤ 3.712 Gbps

0.6

335

Total TMDS data lanes output differential

voltage

See

V_{OD_range}

3.712 Gbps < R_bit< 5.94 Gbps

(2)

5.94 Gbps ≤ R_bit≤ 6.0 Gbps

150

(1) –0.0332R_bit²+ 0.2312 R_bit+ 0.1998

(2) –19.66 × (R_bit²) + (106.74 × R_bit) + 209.58

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ZHCSE15F –JULY 2015–REVISED MAY 2018

7.11 AUX Switching Characteristics (Only for RGZ Package)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

0.6

UNIT

µs

UI_MAN

Manchester transaction unit interval

Cycle-to-cycle jitter time at transmit pins

Cycle-to-cycle jitter time receive pins

0.4

t_{AUXjitter_TX}

t_{AUXjitter_RX}

0.08

0.05

UI_MAN

7.12 HPD Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

See 图 14; not valid during switching time

See 图 15

MIN

TYP

MAX UNIT

Propagation delay from HPD_SNK to

HPD_SRC; rising edge and falling edge

t_PD(HPD)

t_T(HPD)

40

2

120

ns

HPD logical disconnected timeout

ms

7.13 DDC and I²C Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

Vcc = 3.3-V

MIN

TYP

MAX

UNIT

ns

t_r

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Pulse duration, SCL high

300

t_f

ns

t_HIGH

t_LOW

t_SU1

0.6

1.3

100

0.6

1.3

μs

Pulse duration, SCL low

μs

Setup time, SDA to SCL

ns

t_{ST, STA}

t_HD,STA

t_ST,STO

t_(BUF)

Setup time, SCL to start condition

Hold time, start condition to SCL

Setup time, SCL to stop condition

Bus free time between stop and start condition.

μs

Source-to-sink: 100-kbps pattern;

t_PLH1

t_PHL1

t_PLH2

t_PHL2

Propagation delay time, low-to-high-level output Cb(Sink) = 400-pF⁽¹⁾

;

360

230

250

200

ns

See 图 18

Propagation delay time, high-to-low-level output

Sink to Source: 100-kbps pattern;

Propagation delay time, low-to-high-level output Cb(Source) = 100-pF⁽¹⁾

See 图 19

;

Propagation delay time, high-to-low-level output

(1) Cb = total capacitance of one bus line in pF.

15

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7.14 Typical Characteristics

350

300

250

200

150

100

50

200

180

160

140

120

100

80

1.1 V

3.3 V

1.1 V

3.3 V

60

40

20

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

Data Rate (Gbps)

D001

D002

图 1. Current vs Data Rate in Retimer Mode

图 2. Current vs Data Rate in Redriver Mode

1600

V_ODNo Term

V_OD150 to 300 W

V_OD75 to 150 W

1400

1200

1000

800

600

400

200

0

4

4.5

5

5.5

6

6.5

7

7.5

8

V_sadj(kW)

D003

图 3. V_ODvs V_sadj

8 Parameter Measurement Information

V_TERM

3.3V

50Q

75-200nF

50Q

0.5 pF

D+

D-

Y

Z

Receiver

Driver

V_ID

V_D+

V_Y

V_ID= V_D+- V_D-

V_OD= V_Y- V_Z

V_D-

V_Z

V_ICM= (V_D++ V_D-

)

V_OC= (V_Y+ V_Z)

2

图 4. TMDS Main Link Test Circuit

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ZHCSE15F –JULY 2015–REVISED MAY 2018

Parameter Measurement Information (接下页)

2.2 V

V_TERM

V_ID

1.8 V

V_ID+

V_ID(pp)

0 V

V_IDœ

t_PHL

80%

t_PLH

80%

V_OD(pp)

V_OD

0 V

20%

t_f

20%

t_r

图 5. Input and Output Timing Measurements

t_SK1(T)

TMDS_OUTxp

TMDS_OUTxn

50%

t_SK2(T)

TMDS_OUTyp

TMDS_OUTyn

图 6. HDMI and DVI Sink TMDS Output Skew Measurements

V_OC

ûV_OC(SS)

图 7. TMDS Main Link Common Mode Measurements

17

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Parameter Measurement Information (接下页)

VOD(PP)

PRE_SEL=Z

Vsadj = 7.06YQ

图 8. Output Differential Waveform 0 dB De-Emphasis

PRE_SEL = Z

Vsadj = 7.06 lQ

PRE_SEL = L

Vsadj = 7.06 lQ

1^stbit

2^ndto N bit

VOD(SS)

VOD(PP)

图 9. PRE_SEL = L for –2-dB De-Emphasis

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ZHCSE15F –JULY 2015–REVISED MAY 2018

Parameter Measurement Information (接下页)

Avcc⁽⁴⁾

R_T

(5)

R_T

SMA

REF

Cable

EQ

Data +

Coax

RX

+EQ

OUT

Data œ

Parallel⁽⁶⁾

BERT

Jitter Test

Instrument^(2,3)

FR4 PCB trace⁽¹⁾

and AC coupling

capacitors

Device

FR4 PCB trace

AVcc

R_T

[No Pre-

emphasis]

R_T

REF

SMA

Coax

Clk+

Cable

EQ

RX

+EQ

OUT

Clkœ

Jitter Test

Instrument^(2,3)

TTP4_EQ

TTP4

TTP1

TTP2

TTP3

TTP2_EQ

(1) The FR4 trace between TTP1 and TTP2 is designed to emulate 1-8” of FR4, AC coupling cap, connector and another

1-2” of FR4. Trace width – 4 mils. 100-Ω differential impedance.

(2) All jitter is measured at a BER of 10-9.

(3) Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP1.

(4) AVCC = 3.3-V

(5) RT = 50-Ω

(6) The input signal from parallel bit error rate tester (BERT) does not have any pre-emphasis. Refer to Recommended

Operating Conditions.

图 10. TMDS Output Jitter Measurement

HDMI Mask

(mV)

75

V

20

0

DP159 Post EQ Eye Mask

t20

t75

H

T_bit

(ps)

0.3

t33.7 t25

0.5

0.7

25 33.7

图 11. Post EQ Input Eye Mask at TTP2_EQ

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Parameter Measurement Information (接下页)

V

0

H

0

0.5

TMDS DATA RATE (Gbps)

3.4 < DR < 3.712

H (Tbit)

V (mV)

0.6

335

3.712 < DR < 5.94

5.94 ≤ DR ≤ 6.0

–0.0332R_bit²+ 0.2312R_bit+ 0.1998

–19.66R_bit²+ 106.74R_bit+ 209.58

0.4

150

图 12. Output Eye Mask at TTP4_EQ

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HPD_SNK

HPD_SRC

190Kꢀ

100Kꢀ

图 13. HPD Test Circuit

HPD_SNK

V_CC

50%

0 V

t_PD(HPD)

HPD_SRC

V_CC

50%

0 V

图 14. HPD Timing Diagram Number 1

HPD_SNK

Vcc

50%

0V

HPD Logical Disconnect

Timeout

HPD_SRC

tT(HPD)

Vcc

0V

Logically

Disconnected

Device Logically

Connected

图 15. HPD Logic Disconnect Timeout

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tHD,STA

tf

tr

SCL

tST,STO

SDA

t(BUF)

START

STOP

图 16. Start and Stop Condition Timing

tHIGH

tLOW

SCL

tST,STA

SDA

t

SU1

图 17. SCL and SDA Timing

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SDA_SRC/

SCL_SRC

INPUT

½ Vcc

tPLH1

tPHL1

80%

20%

SDA_SNK/

SCL_SNK

OUTPUT

½ Vcc

tf

tr

图 18. DDC Propagation Delay – Source to Sink

SDA_SNK/

SCL_SNK

INPUT

½ Vcc

tPHL2

tPLH2

80%

20%

SDA_SRC/

SCL_SRC

OUTPUT

½ Vcc

tf

图 19. DDC Propagation Delay – Sink to Source

tr

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9 Detailed Description

9.1 Overview

The SNx5DP159 device is a Dual Mode[1] DisplayPort retiming level shifter that supports data rates up to 6-

Gbps for HDMI2.0a. The device takes in AC coupled HDMI/DVI signals and level shifts them to TMDS signals

while compensating for loss and jitter through its receiver equalizer and retiming functions. The SNx5DP159 in

default configuration should meet most system needs but also provides features that allow the system

implementer flexibility in design. Programming can be accomplished through I²C[4] or pin strapping.

9.2 Functional Block Diagram

HPD_SRC

HPD_SNK

VSADJ

190YQ

VBIAS

50Q

OUT_CLKp

OUT_CLKn

IN_CLKp

IN_CLKn

TMDS

EQ

Data Registers

SWAP

VBIAS

PLL

PLL Control

SERDES

50Q

IN_D[2:0]p

IN_D[2:0]n

OUT_D[2:0]p

OUT_D[2:0]n

EQ

TMDS

TERM_SEL

SLEW_SEL

PRE_SEL

Enable

Control Block, I2C Registers

I2C_EN/PIN

EQ_CTL

EQ_SEL

EQ_SEL/A0

HDMI_SEL

A0

CEC_EN

HDMI_SEL/A1

PRE_SEL

OE

TX_TERM_CTL

SLEW_CTL

SWAP/POL

A1

Local I2C

Control

SDA_CTL

SCL_CTL

DDC Snoop Block

SDA_SRC

SCL_SRC

SDA_SNK

ACTIVE DDC BLOCK

SCL_SNK

GND

I2C over AUX

DDC

Bridge

AUX_SRCp

AUX_SRCn

1.1V

3.3V

VDD

VREG

VCC

NOTE: Black pin names are common to both packages.

Blue pin names are only in the SNx5DP159 RGZ package.

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9.3 Feature Description

9.3.1 Reset Implementation

When OE is de-asserted, control signal inputs are ignored; the Dual Mode[1] DisplayPort inputs and outputs are

high impedance. It is critical to transition the OE input from a low level to a high level after the V_CCsupply has

reached the minimum recommended operating voltage. Achieve this transition by a control signal to the OE

input, or by an external capacitor connected between OE and GND. To ensure that the SNx5DP159 device is

properly reset, the OE pin must be de-asserted for at least 100-μs before being asserted. When OE is toggled in

this manner the device is reset. This requires the device to be reprogrammed if it was originally programmed

through I²C for configuration. When implementing the external capacitor, the size of the external capacitor

depends on the power-up ramp of the V_CCsupply, where a slower ramp-up results in a larger value external

capacitor. Refer to the latest reference schematic for SNx5DP159; consider approximately 200-nF capacitor as a

reasonable first estimate for the size of the external capacitor. Both OE implementations are shown in 图 20 and

图 21.

SPACE

GPO

OE

RRST = 200 KΩ

C

图 20. External Capacitor Controlled OE

9.3.2 Operation Timing

图 21. OE Input from Active Controller

SNx5DP159 starts to operate after the OE signal goes high (see 图 22, 图 23, and 表 1). Keeping OE low until

V_DDand V_CCbecome stable avoids any timing requirements as shown in 图 22.

t

d2

OE

t

d1

V_CC/ V_DD

V_DD/ V_CC

图 22. Power-Up Timing for SSNx5DP159

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Feature Description (接下页)

t_d3

CDR Active

t_d4

Retimer mode

OE De-assert or

HPD_SNK De-assert or

Redriver mode

图 23. CDR Timing for SNx5DP159

表 1. SNx5DP159 Operation Timing

MIN

0

MAX

UNIT

µs

t_d1

V_DD/V_CCstable before V_CC/V_DD

V_DDand V_CCstable before OE deassertion

200

t_d2

100

µs

t_d3

CDR active operation after retimer mode initial

CDR turn off time after retimer mode de-assert

V_DDsupply ramp-up requirements

15

120

100

ms

ns

t_d4

VDD_ramp

VCC_ramp

ms

V_CCsupply ramp-up requirements

9.3.3 I²C-over-AUX to DDC Bridge (SNx5DP159 48-Pin Package Version Only)

The SNx5DP159 device incorporates the I²C-over-AUX to DDC bridge to support the DisplayPort Dual-Mode

standard version 1.1. It enables the communication between source device and sink device through AUX

channel. The bridge receives the request from source device in the I²C-over-AUX format and transfers it into

DDC signal to sink device. When the sink device responds, the request in the DDC channel and bridge packages

it into I²C-over-AUX and sends it back to the source device.

9.3.4 Input Lane Swap and Polarity Working

The SNx5DP159 device incorporates the swap function, which can set the input lanes in swap mode. The IN_D2

routes to the OUT_CLK position. The IN_D1 swaps with IN_D0. The swap function only changes the input pins;

EQ setup follows new mapping. The SWAP/POL is pin 1 in the 48-pin RGZ package.For the RSB version, the

user needs to control the register 0x09h bit 7 for SWAP enable. Lane swap is operational in both redriver and

retimer mode.

表 2. Lane Swap⁽¹⁾

NORMAL OPERATION

IN_D2 → OUT_D2

IN_D1 → OUT_D1

IN_D0 → OUT_D0

IN_CLK → OUT_CLK

SWAP = L OR CSR 0x09h BIT 7 IS 1’b1

IN_D2 → OUT_CLK

IN_D1 → OUT_D0

IN_D2 → OUT_D1

IN_CLK → OUT_D2

(1) The output lanes never change. Only the input lanes change. See 图 24 and 图 25.

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36

35

34

33

32

TERM_CTL

OUT_D2p

OUT_D2n

SWAP/POL

1

2

SWAP/POL

36

35

34

33

32

TERM_CTL

OUT_D2p

OUT_D2n

1

2

IN_D2p

IN_D2n

IN_D2p

IN_D2n

DATA LANE2

CLOCK LANE

3

HPD_SNK

OUT_D1p

4

HPD_SNK

OUT_D1p

HPD_SRC

IN_D1p

HPD_SRC

IN_D1p

4

5

DATA LANE1

DATA LANE0

OUT_D1n

IN_D1n

GND

31

30

IN_D1n

GND

6

31

30

6

GND

7

GND

7

29

28

27

26

25

IN_D0p

OUT_D0p

OUT_D0n

A1

8

IN_D0p

OUT_D0p

OUT_D0n

29

28

27

26

25

8

DATA LANE0

DATA LANE1

IN_D0n

I2C_EN/PIN

IN_CLKp

9

IN_D0n

I2C_EN/PIN

IN_CLKp

9

10

11

12

10

11

12

A1

OUT_CLKp

OUT_CLKn

CLOCK LANE

OUT_CLKp

OUT_CLKn

DATA LANE2

IN_CLKn

SWAP = Z

In Normal Working

SWAP = L

In Swap Working

图 24. SNx5DP159 Swap Function for 48 Pins

IN_D2p

IN_D2n

1

2

30

IN_D2p

IN_D2n

1

2

3

4

5

6

7

8

9

30

29

28

27

26

OUT_D2p

OUT_D2n

HPD_SNK

OUT_D2p

OUT_D2n

HPD_SNK

DATA LANE2

CLOCK LANE

29

28

27

26

HPD_SRC

3

IN_D1p

IN_D1n

4

IN_D1p

IN_D1n

OUT_D1p

DATA LANE1

DATA LANE0

DATA LANE1

5

OUT_D1n

OUT_D0p

OUT_D1n

OUT_D0p

IN_D0p

25

24

IN_D0p

IN_D0n

6

25

24

IN_D0n

I2C_EN/GPIO

IN_CLKp

7

OUT_D0n

23

22

21

I2C_EN/GPIO

IN_CLKp

23

22

21

8

HDMI_SEL

OUT_CLKp

OUT_CLKn

HDMI_SEL

OUT_CLKp

OUT_CLKn

9

DATA LANE2

CLOCK LANE

IN_CLKn

10

40-Pin RSB

In Swap Working

40-Pin RSB

In Normal Working

图 25. SNx5DP159 Swap Function for 40 Pins

The SNx5DP159 can also change the polarity of the input signals. When SWAP/POL is high, the n and p pins on

each lane will swap.Use Register 0x9h bit 6 to swap polarity using I²C. Polarity swap only works for retimer

mode. When the device is in automatic redriver to retimer mode this only works when device is in retimer stage.

If set and data rate falls below 1.0-Gbps in this mode the polarity function will be lost.

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9.3.5 Main Link Inputs

Standard Dual Mode[1] DisplayPort terminations are integrated on all inputs with expected AC coupling

capacitors on board prior to input pins. External terminations are not required. Each input data channel contains

an adaptive or fixed equalizer to compensate for cable or board losses. The voltage at the input pins must be

limited below the absolute maximum ratings. The input pins have incorporated failsafe circuits. The input pins

can be polarity changed through the local I2C register or pin strapping.

9.3.6 Main Link Inputs Debug Tools

There are two methods for debugging a system making sure the inputs to the SNx5DP159 are valid. A TMDS

error checker is implemented that will increment an error counter per data lane. This allows the system

implementer to determine how the link between the source and SNx5DP159 is performing on all three data

lanes. See CSR Bit Field Definitions – RX PATTERN VERIFIER CONTROL/STATUS register in 表 10.

If a high error count is evident, the SNx5DP159 has the ability to provide the general eye quality. A tool is

available that uses the I²C[4] link to download data that can be plotted for an eye diagram. This is available per

data lane.

9.3.7 Receiver Equalizer

Equalizers are used to clean up inter-symbol interference (ISI) jitter or loss from the bandwidth-limited board

traces or cables. The SNx5DP159 device supports both fixed receiver equalizer (redriver and retimer mode) and

adaptive receive equalizer (retimer mode) by setting the EQ_SEL/A0 pin or through I²C using reg0Ah[5]. When

the EQ_SEL/A0 pin is high, the EQ gain is fixed to 14-dB. The EQ gain will be 7.5-dB if the EQ_SEL/A0 pin is

set low. The SNx5DP159 device operates in adaptive equalizer mode when EQ_SEL/A0 left floating. Using

adaptive equalization the gain will be automatically adjusted based on the data rate to compensate for variable

trace or cable loss. Using the local I²C[4] control, reg0Dh[5:1], the fixed EQ gain can be selected for both data

and clock.

图 26. Adaptive EQ Gain Curve

9.3.8 Termination Impedance Control

HDMI2.0[3] standard requires the transmitter termination impedance should be between 75 to 150-Ω. Older

versions of the HDMI standard required no source termination. For HDMI1.4b[2] when data rate over 2 Gbps, the

output performance could be better if the termination value between 150 to 300-Ω which was allowed. The

SNx5DP159 supports three different source termination impedances for HDMI1.4b[2] and HDMI2.0[3]. Pin 36,

TX_TERM_CTL, offers a selection option to choose the output termination impedance value. This can be

adjusted by I²C[4]; reg0Bh[4:3] TX_TERM_CTL.

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9.3.9 TMDS Outputs

An 1% precision resistor, 7.06-kΩ, is recommended to be connected from Vsadj pin to ground to allow the

differential output swing to comply with TMDS signal levels. The differential output driver provides a typical 10-

mA current sink capability when no source term is enabled, which provides a typical 500-mV voltage drop across

a 50-Ω termination resistor. As compliance testing is system dependant this resistor value can be adjusted.

AVCC

Vcc

Zo=RT

TMDS DRIVER

TMDS RECEIVER

图 27. TMDS Driver and Termination Circuit

Referring to 图 27, if both V_CC(device supply) and AVCC (sink termination supply) are powered, the TMDS

output signals are high impedance when OE = low. The normal operating condition is that both supplies are

active. A total of 33-mW of power is consumed by the terminations independent of the OE logical selection.

When AVCC is powered on, normal operation (OE controls output impedance) is resumed. When the power

source of the device is off and the power source to termination is on, the IO(off) (output leakage current)

specification ensures the leakage current is limited 45-μA or less.

The clock and data lanes V_ODcan be changed through I²C[4] (see VSWING_CLK and VSWING_DATA in 表 8

for details). 图 3 shows the different output voltage based on different Vsadj resistor values.

9.3.9.1 Pre-Emphasis/De-Emphasis

The SNx5DP159 provides De-emphasis as a way to compensate for the ISI loss between the TMDS outputs and

the receiver it is driving. There are two methods to implement this function. When in pin strapping mode the

PRE_SEL pin controls this. The PRE_SEL pin provides –2-dB, or 0-dB de-emphasis, which allows output signal

pre-conditioning to offset interconnect losses from the SNx5DP159 device outputs to a TMDS receiver. TI

recommends setting PRE_SEL at 0 dB while connecting to a receiver through a short PCB route. When pulled to

ground with a 65-kΩ resistor –2-dB can be realized, see 图 9. When using I²C, Reg0Ch[1:0] is used to make

these adjustments.

As there are times true pre-emphasis may be the best solution there are two ways to accomplish this. If pin

strapping is being use the best method is to reduce the Vsadj resistor value increasing the V_ODand then pulling

the PRE_SEL pin to ground using the 65-kΩ resistor, see 图 28. If using I²C this can be accomplished using two

methods. First is similar to pin strapping by adjusting the Vsadj resistor value and then implementing –2-dB de-

emphasis. Second method is to set Reg0Ch[7:5] = 011 and the set Reg0Ch[1:0] = 01 which accomplishes the

same pre-emphasis setting. See 图 29.

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PRE_SEL = Z

Vsadj = 7.06YQ

PRE_SEL = L

Vsadj = 4.5YQ

1^stbit

VOD(PP) = 1400mVpp

2^ndto N bit

VOD(SS) = 1150mVpp

图 28. Pre-Emphasis Using Pin Strapping Method

PRE_SEL = Z

Vsadj = 7.06YQ

I2C Reg0Ch[7:5] = 011

Reg0C[1:0] = 01

1^stbit

2^ndto N bit

VOD(PP) = 1200mVpp

VOD(SS) = 1020mVpp

图 29. Pre-Emphasis Using I²C Method

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9.4 Device Functional Modes

9.4.1 Retimer Mode

Clock and data recovery circuits (CDR) are used to track, sample and retime the equalized data bit streams. The

CDRs are designed with loop bandwidth to minimize the amount of jitter transfer from the video source to the

TMDS outputs. Input jitter within the CDR’s PLL bandwidth, < 1-MHz, will be transferred to the TMDS outputs.

Higher frequency jitter above the CDR loop bandwidth is attenuated, providing a jitter cleaning function to reduce

the amount of high frequency jitter from the video source. The retimer is automatically activated at pixel clock

above approximately 100-MHz when jitter cleaning is needed for robust operation. The retimer operates at about

1.0 to 6-Gbps DR supporting HDMI2.0[3]. At pixel clock frequency below about 100 MHz, the SNx5DP159

automatically bypasses the internal retimer and operates as a redriver. When the video source changes

resolution, the internal retimer starts the acquisition process to determine the input clock frequency and acquire

lock to the new data bit streams. During the clock frequency detection period and the retimer acquisition period

(that last approximately 7-ms), the TMDS drivers can be kept active (default) or programmed to be disabled to

avoid sending invalid clock or data to the downstream receiver.

9.4.2 Redriver Mode

The SNx5DP159 also has a redriver mode that can be enabled through I²C[4]; at offset address 0Ah bits 1:0

DEV_FUNC_MODE. When in this mode, the CDR and PLL are shut off, thus reducing power. Jitter performance

is degraded as the device will now only compensate for ISI loss in the link. In redriver mode HDMI2.0[3]

compliance is not guaranteed as skew compensation and retiming functions are disabled. Excessive random or

phase jitter will not be compensated.

9.4.3 DDC Training for HDMI2.0 Data Rate Monitor

As part of discovery, the source reads the sink’s E-EDID information to understand the sink’s capabilities. Part of

this read is HDMI forum vendor specific data block (HF-VSDB) MAX_TMDS_Character_Rate byte to determine

the data rate supported. Depending upon the value, the source will write to slave address 0xA8 offset 0x20 bit1,

TMDS_CLOCK_RATIO_STATUS. The SNx5DP159 snoops this write to determine the TMDS clock ratio and

thus sets its own TMDS_CLOCK_RATIO_STATUS bit accordingly. If a 1 is written, then the TMDS clock is 1/40

of TMDS bit period. If a 0 is written, then the TMDS clock is 1/10 of TMDS bit period. The SNx5DP159 will

always default to 1/10 of TMDS bit period unless a 1 is written to address 0xA8 offset 0x20 bit 1. When

HPD_SNK is de-asserted, this bit is reset to default values. If the source does not write this bit the SNx5DP159

will not be configured for TMDS clock 1/40 mode in support of HDMI2.0. As the SNx5DP159 is in link but not

recognized as part of the link it is possible that the source could read the sink EDID where this bit is set and

does not re-write this bit. If the SNx5DP159 has entered a power down state this bit is cleared and does not re-

set on a read. To work properly the bit has to be set again with a write by the source.

9.4.4 DDC Functional Description

The SNx5DP159 solves sink- or source-level issues by implementing a master/slave control mode for the DDC

bus. When the SNx5DP159detects the start condition on the DDC bus from the SDA_SRC/SCL_SRC, it will

transfer the data or clock signal to the SDA_SNK/SCL_SNK with little propagation delay. When SDA_SNK

detects the feedback from the downstream device, the SNx5DP159 will pull up or pull down the SDA_SRC bus

and deliver the signal to the source.

The DDC link defaults to 100 kbps, but can be set to various values including 400 kbps by setting the correct

value to address 22h (see 表 3) through the I²C access on the DDC interface. The DDC lines are 5-V tolerant.

The HPD_SRC goes to high impedance when VCC is under low power conditions, < 1.5-V.

注

The SNx5DP159 uses clock stretching for DDC transactions. As there are sources and

sinks that do no perform this function correctly a system may not work correctly as DDC

transactions are incorrectly transmitted/received. To overcome this a snoop configuration

can be implemented where the SDA/SCL from the source is connected directly to the

SDA/SCL sink. The SNx5DP159 will need its SDA_SNK and SCL_SNK pins connected to

this link in order to the SNx5DP159 to configure the TMDS_CLOCK_RATIO_STATUS bit.

Care must be taken when this configuration is being implemented as the voltage levels for

DDC between the source and sink may be different, 3.3 V vs 5 V.

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9.5 Register Maps

9.5.1 DP-HDMI Adaptor ID Buffer

The SNx5DP159 device includes the DP-HDMI adapter ID buffer for HDMI/DVI adaptor recognition, defined by

the VESA DisplayPort Dual-Mode Standard Version 1.1, accessible by standard I²C[4] protocols through the

DDC interface when the HDMI_SEL/A1 pin is low. The DP-HDMI adapter buffer and extended DDC register for

Type 2 capability is accessed at target addresses 80h (Write) and 81h (Read).

The DP-HDMI adapter buffer contains a read-only phrase DP-HDMI ADAPTOR<EOT> converted to ASCII

characters, as shown in 表 3, and supports the WRITE command procedures (accessed at target address 80h)

to select the subaddress, as recommended in the VESA DisplayPort Interoperability Guideline Adaptor Checklist

Version 1.0 section 2.3.

表 3. SNx5DP159 DP-HDMI Adaptor ID Buffer and Extended DDC

Read or

Read/Write

Address

Description

Value HDMI

Value DVI

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

44h

50h

2Dh

48h

44h

4Dh

49h

20h

41h

44h

41h

50h

54h

4Fh

52h

04h

00h

HDMI ID code

Read only

Video Adaptor Identifier

Bit 2:0 ADAPTOR_REVISION

0

10h

Read only

Bit 3 Reserved: but 0 for type 2

Bits 7:4 1010 = Dual mode defined by dual mode[1]

standard

1010

11h

12h

13h

14h

15h

16h

17h

18h

19h

IEE_OUI first two hex digits

IEE_OUI second two hex digits

IEE_OUI third two hex digits

08h

00h

28h

44h

50h

31h

35h

39h

00h

02h

00h

02h

00h

08h

00h

28h

44h

50h

31h

35h

39h

00h

02h

00h

02h

00h

Read only

Device ID

Read only

Hardware revision

1Ah

Bits 7:4 major revision

Read only

Bits 3:0 minor revision

1Bh

1Ch

Firmware or software major revision

Firmware or software minor revision

Read only

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Register Maps (接下页)

表 3. SNx5DP159 DP-HDMI Adaptor ID Buffer and Extended DDC (接下页)

Read or

Read/Write

Address

Description

Value HDMI

Value DVI

Max TMDS clock rate

Default value is F0h in HDMI column

Note: Value determined by taking clock rate and dividing by

2.5 and converting to HEX. For HDMI2.0 extend as if the

clock rate extended instead of its actual method, clock 1/10

DR and not 1/40 DR.

1Dh

1Eh

F0h

42h

Read only

If I2C_DR_CTL = 0 the value is 0Fh → If

DDC_AUX_DR_SEL = 0 the value is 0Fh

If I2C_DR_CTL = 1 the value is 1Fh → If

DDC_AUX_DR_SEL = 1 then value is 1Fh

If I2C_DR_CTL = 0 the value is 0Fh

If I2C_DR_CTL = 1 the value is 1Fh

0Fh

1Fh

20h

Reserved

00h

Write/Read

TMDS_OE

Bit 0: 0 = TMDS_ENABLED (default)

Bit 0: 1 = TMDS_DISABLED

Bits 7:1 Reserved

HDMI Pin Control

Bit 0 = CEC_EN

Enables connection between the HDMI CEC pin connected

to the sink and the

CONFIG2 pin to the upstream device + 27-kΩ pullup.

0 = CEC_ DISABLED (default)

1 = CEC_ ENABLED

21h

00h

Write/Read

Bits 7:1 = RESERVED

Writing a bit pattern to this register that is not defined above

may result in an unpredictable I²C speed selection, but the

adaptor must continue to otherwise work normally. Only

applicable when using I²C-over-AUX transport

01h = 1-Kbps

02h = 5-Kbps

04h = 10-Kbps

22h

08h = 100-kbps

08h

Write/Read

10h = 400-Kbps (RSVD in Dual Mode STND)

On read, the dual-mode cable adaptor returns a value to

indicate the speed currently in use. The default I2C speed

prior to software writing to this register is 100-Kbps.

Illegal write value shall write register default (08h). This

register sets the DDC output DR whether I²C-over-AUX or

straight DDC

23h-FFh Reserved

00h

Read

9.5.2 Local I²C Interface Overview

The SCL_CTL and SDA_CTL pins are used for I²C clock and I²C data respectively. The SNx5DP159 I²C

interface conforms to the 2-wire serial interface defined by the I²C Bus Specification, Version 2.1 (January 2000),

and supports the fast mode transfer up to 400 kbps.

The device address byte is the first byte received following the start condition from the master device. The 7-bit

device address for the SNx5DP159 device decides by the combination of EQ_SEL/A0 and HDMI_SEL/A1. 表 4

clarifies the SNx5DP159 device target address.

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表 4. I²C Device Address Description

SNx5DP159 I²C Device Address

A1/A0

ADD

7 (MSB)

6

0

5

1

4

1

3

1

0

2

1

0

1

0

1

0

1

0 (W/R)

0/1

00

01

10

11

1

BC/BD

BA/BB

B8/B9

B6/B7

0/1

9.5.3 I²C Control Behavior

Follow this procedure to write to the SNx5DP159 device I²C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the SNx5DP159 device

7-bit address and a zero-value W/R bit to indicate a write cycle.

2. The SNx5DP159 device acknowledges the address cycle by combination of A0 and A1.

3. The master presents the subaddress (I²C register within SNx5DP159 device) to be written, consisting of one

byte of data, MSB-first.

4. The SNx5DP159 device acknowledges the subaddress cycle.

5. The master presents the first byte of data to be written to the I²C register.

6. The SNx5DP159 device acknowledges the byte transfer.

7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing

with an acknowledge from the SNx5DP159 .

8. The master terminates the write operation by generating a stop condition (P).

Follow this procedure to read the SNx5DP159 I²C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the SNx5DP159 7-bit

address and a zero-value W/R bit to indicate a write cycle.

2. The SNx5DP159 device acknowledges the address cycle by combination of A0 and A1.

3. The master presents the subaddress (I2C register within SNx5DP159 device) to be read, consisting of one

byte of data, MSB-first.

4. The SNx5DP159 device acknowledges the subaddress cycle.

5. The master initiates a read operation by generating a start condition (S), followed by the SNx5DP159 7-bit

address and a one-value W/R bit to indicate a read cycle.

6. The SNx5DP159 device acknowledges the address cycle.

7. The SSNx5DP159 device transmit the contents of the memory registers MSB-first starting at the written

subaddress.

8. The SNx5DP159 device will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the

master after each byte transfer; the I²C master acknowledges reception of each data byte transfer.

9. If an ACK is received, the SNx5DP159 device transmits the next byte of data.

10. The master terminates the read operation by generating a stop condition (P).

注

Upon reset, the SNx5DP159 sub-address will always be set to 0x00. When no subaddress

is included in a read operation, the SNx5DP159 subaddress increments from previous

acknowledged read or write data byte. If it is required to read from a subaddress that is

different from the SNx5DP159 internal subaddress, a write operation with only a

subaddress specified is needed before performing the read operation.

Refer to 表 6 for the SNx5DP159 device local I²C register descriptions. Reads from reserved fields return 0s and

writes are ignored.

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9.5.4 I²C Control and Status Registers

Reads from reserved fields return 0, and writes to read-only reserved registers are ignored. Writes to reserved

registers, which are marked with ‘W’, produce unexpected behavior. All addresses not defined by this

specification are considered reserved. Reads from these addresses return 0 and writes will be ignored.

9.5.4.1 Bit Access Tag Conventions

A table of bit descriptions is typically included for each register description that indicates the bit field name, field

description, and the field access tags. The field access tags are described in 表 5.

表 5. Field Access Tags

ACCESS TAG

NAME

Read

Write

Set

DESCRIPTION

R

W

S

The field is read by software

The field is written by software

The field is set by a write of one. Writes of 0 to the field have no effect

C

Clear

The field is cleared by a write of 1. Writes of 0 to the field have no

effect

U

Update

Hardware may autonomously update this field

Not accessible or not applicable

NA

No access

9.5.4.2 CSR Bit Field Definitions

9.5.4.2.1 ID Registers

表 6. ID Registers

ADDRESS

BIT

DESCRIPTION

ACCESS

DEVICE_ID

00h:07h

7:0

R

These fields return a string of ASCII characters “DP159” followed by three space characters.

Address 0x00 – 0x07 = {0x44”D”, 0x50”P”, 0x31”1”, 0x35”5”, 0x39”9”, 0x20, 0x20, 0x20}

REV _ID. This field identifies the device revision.

0000001 – DP159 revision 1

08h

7:0

R

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9.5.4.2.2 Misc Control

表 7. Misc Control

ADDRESS

BIT

DEFAULT DESCRIPTION

ACCESS

SWAP_EN: This field enables swapping the input main link lanes

0 – Disable (default)

1 – Enable

7

1’b0

RWU

Note: field is loaded from SWAP/POL pin; Writes ignored when I2C_EN/PIN = 0

LANE_POLARITY: swaps the input data and clock lanes polarity.

0 – Disabled: No polarity swap

6

1’b0

1 – Swaps the input data and clock lane polarity

RWU

Note: field is loaded from SWAP/POL pin; Writes ignored when I2C_EN/PIN = 0. This

feature is only valid when in retimer mode.

5:4

3

2'b00

1’b0

Reserved

R

PD_EN

09h

0 – Normal working (default)

RW

1 – Forced power-down by I²C, lowest power state

HPD_AUTO_PWRDWN_DISABLE

0 – Automatically enters power down mode based on HPD_SNK (default)

1 – Will not automatically enter power mode based upon HPD_SNK

2

1’b0

RW

I2C_DR_CTL. I2C data rate supported for configuring device

00 – 5-kbps

01 – 10-kbps

10 – 100-kbps (default)

1:0

2’b10

11 – 400-kbps (Note: HPD_AUTO_PWRDWN_DISABLE must be set before enabling 400

Kbps mode)

Application Mode Selection

0 – Source (default) - Set the adaptive EQ mid point to between 6.5-dB and 7.5-dB

1 – Sink - Sets the adaptive EQ starting point to between 12-dB and 13-dB

7

6

1’b0

RW

HPDSNK_GATE_EN: This field sets the functional relationship between HPD_SNK and

HPD_SRC.

0 – HPD_SNK passed through to the HPD_SRC (default)

1 – HPD_SNK will not pass through to the HPD_SRC.

EQ_ADA_EN: this field enables the equalizer working state.

0 – Fixed EQ

1 – Adaptive EQ (default)

5

4

3

1’b1

RWU

RW

Writes are ignored when I2C_EN/PIN = 0

EQ_EN: this field enables the receiver equalizer.

0 – EQ disabled

1 – EQ enable (default)

0Ah

AUX_BRG_EN: this field enable the AUX bridge working.This is only valid for the 48-pin

package.

0 – AUX bridge disable

1 – AUX bridge enable (default)

RWU

APPLY_RXTX_CHANGES , Self clearing write-only bit. Writing a 1 to this bit will apply new

slew, tx_term, twpst1, eqen, eqadapten, swing, eqftc, eqlev settings to the clock and data

2

1’b0

lanes. Writes to the respective registers do not take immediate effect. This bit does not need

to be written if I²C configuration occurs while OE or hpd_sink are low, I²C power down is

active.

W

DEV_FUNC_MODE: This field selects the device working function mode.

00 – Redriver mode across full range 250 Mbps to 6-Gbps

01 - Automatic redriver to retimer crossover at 1.0 Gbps (default)

10 - Automatic retimer for HDMI2.0

1:0

2’b01

RW

11 - Retimer mode across full range 250 Mbps to 6-Gbps

When changing crossover point, need to toggle PD_EN or toggle external HPD_SNK.

Mode Selection Definition: This bit lets the receiver know where the device is located in a system for the

purpose of centering the AEQ point. The SNx5DP159 is targeting the source application, so the default value is

0, which will center the EQ at 6.5 to 7.5-dB depending upon TMDS_CLOCK_RATIO_STATUS value, see 表 9. If

the SNx5DP159 is in a dock or sink application, the value should be changed to a value of 1, which will center

the EQ at 12 to 13-dB depending upon TMDS_CLOCK_RATIO_STATUS value.

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9.5.4.2.3 HDMI Control

表 8. HDMI Control

ADDRESS BIT

DEFAULT DESCRIPTION

ACCESS

SLEW_CTL. Slew rate control.2’00 is fastest and 2’b11 is slowest

Writes ignored when I2C_EN/PIN = 0

7:6

2’b00

RWU

HDMI_SEL: Contro; Writes ignored when I2C_EN/PIN = 0l

0 – HDMI (default)

1 – DVI

5

1’b0

RWU

TX_TERM_CTL: Controls termination for HDMI TX

00 – No termination

01 – 150 to 300-Ω

10 – Reserved

11 – 75 to 150-Ω

4:3

2’b00

1’b0

Note: Reflects the value of the TX_TERM_CTL pin; Writes ignored when I2C_EN/PIN = 0

2

Reserved

R

TMDS_CLOCK_RATIO_STATUS: This field is updated from snoop of I²C write to slave

address 0xA8 offset 0x20 bit 1 that occurred on the SDA_SRC/SCL_SRC interface. When

bit 1 of address 0xA8 offset 0x20 is written to a 1’b1, then this field will be set to a 1’b1.

When bit 1 of address 0xA8 offset 0x20 is written to a 1’b0, then this field will be set to a

1’b0. This field is reset to the default value whenever HPD_SNK is de-asserted for greater

than 2 ms.

0Bh

1

0

1’b0

RWU

0 – TMDS clock is 1/10 of TMDS bit period (default)

1 – TMDS clock is 1/40 of TMDS bit period

DDC_TRAIN_SET: This field indicates the DDC training block function status. If disabled,

the device can only work at the HDMI1.4b[2] or DVI mode

0 – DDC training enable (default)

RW

1 – DDC training disable

Note: To force TMDS_CLOCK_RATIO_STATUS to 1, this register bit must be set to 1

which will force the 1/40 mode for HDMI2.0.

VSWING_DATA: Data output swing control

000 – Vsadj set

001 – Increase by 7%

010 – Increase by 14%

011 – Increase by 21%

100 – Decrease by 30%

101 – Decrease by 21%

110 – Decrease by 14%

111 – Decrease by 7%

7:5

3’b000

VSWING_CLK: Clock Output Swing Control

000 – Vsadj set

001 – Increase by 7%

0Ch

010 – Increase by 14%

011 – Increase by 21%

4:2

3’b000

100 – Decrease by 30%

RW

101 – Decrease by 21%

110 – Decrease by 14%

111 – Decrease by 7%

Note: Default is set by DR, which means standard based swing values but this allows for

the swing to be overridden by selecting one of these values

HDMI_TWPST1. HDMI de-emphasis FIR post-cursor-1 signed tap weight.

00 – No de-emphasis

01 – 2-dB de-emphasis

10 – Reserved

1:0

2’b00

RWU

11 – Reserved

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9.5.4.2.4 Equalization Control Register

表 9. Equalization Control Register

ADDRESS

BIT

DEFAULT

DESCRIPTION

ACCESS

7:6

2’b00

Reserved

RW

Data Lane EQ – Sets fixed EQ values

HDMI1.4b[2]

000 – 0-dB

HDMI2.0[3]

000 – 0-dB

001 – 3-dB

010 – 5-dB

011 – 7.5-dB

100 – 9.5-dB

101 – 11-dB

110 – 13-dB

111 – 14.5-dB

001 – 4.5-dB

010 – 6.5-dB

011 – 8.5-dB

100 – 10.5-dB

101 – 12-dB

110 – 14-dB

111 – 16.5-dB

5:3

1’b000

RW

0Dh

Clock Lane EQ - Sets fixed EQ values

HDMI1.4b[2]

00 – 0-dB

01 – 1.5-dB

10 – 3-dB

HDMI2.0[3]

00 – 0-dB

01 – 1.5-dB

10 – 3-dB

2:1

0

1’b00

1’b0

RW

11 – RSVD

11 – 4.5-dB

0 – Clock VOD is half the set value when TMDS_CLOCK_RATIO_STATUS

states in HDMI2.0 mode

1 – Disables TMDS_CLOCK_RATIO_STATUS control of the clock VOD so the

output swing is full swing

9.5.4.2.5 EyeScan Control Register

表 10. EyeScan Control Register

ADDRESS

BITS

DEFAULT

DESCRIPTION

ACCESS

PV_SYNC[3:0]. Pattern timing pulse. This field is updated for 8UI once

every cycle of the PRBS generator. 1 bit per lane.

7:4

4’b0000

R

PV_LD[3:0]. Load pattern-verifier controls into RX lanes. When asserted

high, the PV_TO, PV_SEL, PV_LEN, PV_CP20, and PV_CP values are

enabled into the corresponding RX lane. These values are then latched

and held when PV_LD[n] is subsequently de-asserted low. 1 bit per lane.

0Eh

3:0

4’b0000

RWU

7:4

3:0

4’b0000

PV_FAIL[3:0]. Pattern verification mismatch detected. 1 bit per lane.

PV_TIP[3:0]. Pattern search/training in progress. 1 bit per lane.

RU

0Fh

PV_CP20. Customer pattern length 20 or 16 bits.

7

6

1’b0

0 – 16 bits

1 – 20 bits

RW

R

Reserved

PV_LEN[2:0]. PRBS pattern length

000 – PRBS7

001 – PRBS11

010 – PRBS23

5:3

3’b000

011 – PRBS31

100 – PRBS15

RW

10h

101 – PRBS15

110 – PRBS20

111 – PRBS20

PV_SEL[24:0]. Pattern select control

000 – Disabled

001 – PRBS

010 – Clock

2:0

3’b000

RW

011 – Custom

1xx – Timing only mode with sync pulse spacing defined by PV_LEN

11h

12h

7:0

‘h00

PV_CP[7:0]. Custom pattern data.

PV_CP[15:8]. Custom pattern data.

RW

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表 10. EyeScan Control Register (接下页)

ADDRESS

BITS

7:4

DEFAULT

4’b0000

5’b00000

3’b000

DESCRIPTION

ACCESS

Reserved

R

13h

3:0

PV_CP[19:16]. Custom pattern data. Used when PV_CP20 = 1’b1.

Reserved

RW

R

7:3

14h

15h

2:0

PV_THR[2:0]. Pattern-verifier retain threshold.

RW

DESKEW_CMPLT: Indicates TMDS lane deskew has completed when

high

7

1'b0

R

6:5

4

2’b00

1’b0

Reserved

R

BERT_CLR. Clear BERT counter (on rising edge).

TST_INTQ_CLR. Clear latched interrupt flag.

TST_SEL[2:0]. Test interrupt source select.

RSU

RW

3

1’b0

2:0

3’b000

PV_DP_EN[3:0]. Enabled datapath verified based on DP_TST_SEL, 1 bit

per lane.

7:4

3

4’b0000

1’b0

RW

R

Reserved

DP_TST_SEL[2:0] Selects pattern reported by BERT_CNT[11:0],

TST_INT[0] and TST_INTQ[0]. PV_DP_EN is non-zero

000 – TMDS disparity or data errors

001 – FIFO errors

16h

010 – FIFO overflow errors

011 – FIFO underflow errors

100 – TMDS deskew status

2:0

3'b000

RW

101 – Reserved

110 – Reserved

111 – Reserved

7:4

3:0

7:0

7:4

3:0

7:0

7:4

3:0

7:0

7:4

3:0

7:0

7:4

3:0

7:4

3

4’b0000

‘h00

TST_INTQ[3:0]. Latched interrupt flag. 1 bit per lane

TST_INT[3:0]. Test interrupt flag. 1 bit per lane.

BERT_CNT[7:0]. BERT error count. Lane 0

Reserved

RU

R

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

4’b0000

‘h00

BERT_CNT[11:8]. BERT error count. Lane 0

BERT_CNT[19:12]. BERT error count. Lane 1

Reserved

RU

R

4’b0000

‘h00

BERT_CNT[23:20]. BERT error count. Lane 1

BERT_CNT[31:24]. BERT error count. Lane 2

Reserved

RU

R

4’b0000

‘h00

BERT_CNT[35:32]. BERT error count. Lane 2

BERT_CNT[19:12]. BERT error count. Lane 3

Reserved

RU

R

4’b0000

‘h00

BERT_CNT[23:20]. BERT error count. Lane 3

Reserved

RU

R

4’b0000

1'b1

AUX_TX_SR Slew Rate Control for AUX Output

RW

AUX_SWING; Swing Control for AUX Output

000 – 270 mV

001 – 355 mV

010 – 450 mV

20h

2:0

3'b010

011 – 535 mV

RW

100 – 625 mV

101 – 710 mV

110 – 800 mV

111 – Not allowed

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10 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

DP159 is designed to accept AC coupled HDMI input signals. The device provides signal conditioning and level

shifting functions to drive a compliant HDMI source connector. DP159 can be used as an DP1.2 retimer, follow

application note SLLA358 for required additional configuration. In many major PC or gaming platforms APU/GPU

can provide AC coupled HDMI 2.0 signals, DP159 is suitable for such platforms.

10.1 Application Information

The DP159 was defined to work in mainly in source applications such as gaming systems, Blu-Ray DVD player,

desktop, notebook or VR. The following sections provide design consideration for various types of applications.

10.1.1 Use Case of SNx5DP159

SNx5DP159 can be used on the motherboard and dongle applications. The following use case diagrams show

the connection of AUX and DDC between source side and sink side. The control pin pull up and pull down

resistors are shown from reference. If a high is needed only use the pull up. If a low is needed only use the pull

down. If mid level is to be selected do not use either resistors and leave the pin floating/No connect. The 6.5-KΩ

Vsadj resistor value shown is explained further in the compliance section, for the RSB package.

The DP159 was defined to work in mainly in source applications such as gaming systems, Blu-Ray DVD player,

Desktop, Notebook or VR. The following sections provide design consideration for various types of applications.

图 30 shows the original connection of SNx5DP159 on motherboard through the DDC channel. The DDC DR

default is 100-kHz and is capable to adjust to 400-kHz.

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Application Information (接下页)

HDMI/DVI

Receptacle

40-Pin

1

30

29

27

26

25

24

22

21

0.1uF

1

2

TMDS_D2p

ML0p

ML0n

ML1p

ML1n

ML2p

ML2n

ML3p

ML3n

IN_D2p

IN_D2n

IN_D1p

IN_D1n

IN_D0p

IN_D0n

IN_CLKp

IN_CLKn

HPD_SRC

OUT_D2p

OUT_D2n

OUT_D1p

OUT_D1n

OUT_D0p

OUT_D0n

GND1

3

4

5

TMDS_D2n

TMDS_D1p

GND2

GND3

GND4

GND5

GND6

8

4

11

14

17

6

5

TMDS_D1n

TMDS_D0p

TMDS_D0n

TMDS_CLKp

TMDS_CLKn

CEC

7

6

9

7

10

12

9

OUT_CLKp

OUT_CLKn

10

3

5V

13

HPD

CEC

20

21

22

23

2YQ

CASE_GND1

DDC_SCL CASE_GND2

DDC_SDA CASE_GND3

3.3V

2YQ

32

33

28

15

16

19

SCL_SNK

SDA_SNK

HPD_SNK

2YQ

38

39

DDC_SCL

DDC_SDA

SCL_SRC

SDA_SRC

HPD

CASE_GND4

VCC

3.3V

0.01uF

100YQ

VCC

CAD_DET

65lQ

2YQ

13

14

SCL_CTL

SDA_CTL

I2C_SCL

I2C_SDA

10uF

0.1uF 0.1uF

8

I2C_EN/PIN

PRE_SEL

16

17

23

Optional

36

18

EQ_SEL/A0

HDMI_SEL/A1

SLEW_CTL

OE

0.1uF

34

VSADJ

CEC

6.5YQ

1%

65lQ

15

35

GND

VDD

GND

THERMAL PAD

10uF

0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF

11

37

12

20

19

31 40

VCC

VDD

图 30. Implementation for Motherboard 1

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Application Information (接下页)

图 31 shows the connection for both DDC and AUX GPU connections with the SNx5DP159RGZ. Only one can

be implemented at a time. Only the RGZ package supports the I²C-over-AUX implementation. The control pin

pull up and pull down resistors are shown for reference. If a high is needed only use the pull up. If a low is

needed only use the pull down. If mid level is to be selected do not use either resistors and leave the pin

floating/No connect.

HDMI/DVI

Receptacle

SNx5DP159RGZ

1

3

35

34

32

31

29

28

26

25

0.1uF

2

3

2

5

TMDS_D2p

TMDS_D2n

TMDS_D1p

ML0p

ML0n

ML1p

ML1n

ML2p

ML2n

ML3p

ML3n

IN_D2p

IN_D2n

IN_D1p

IN_D1n

IN_D0p

IN_D0n

IN_CLKp

IN_CLKn

HPD_SRC

OUT_D2p

OUT_D2n

OUT_D1p

OUT_D1n

OUT_D0p

OUT_D0n

OUT_CLKp

OUT_CLKn

GND1

GND2

8

4

5

GND3

GND4

GND5

GND6

11

14

17

6

TMDS_D1n

TMDS_D0p

TMDS_D0n

TMDS_CLKp

TMDS_CLKn

CEC

7

8

9

10

12

11

12

4

5V

13

HPD

CEC

20

21

22

23

2YQ

CASE_GND1

DDC_SCL CASE_GND2

DDC_SDA CASE_GND3

VCC_3.3V

2YQ

38

39

33

15

16

19

SCL_SNK

SDA_SNK

HPD_SNK

2YQ

Note 1

46

47

DDC_SCL

DDC_SDA

SCL_SRC

SDA_SRC

NC

Note 1

HPD

CASE_GND4

VCC_3.3V

17

1aQ

0.01uF

65lQ

0.1uF

45

44

7

65lQ

AUXp

AUXn

AUX_SRCp

AUX_SRCn

GND

1

SWAP/POL

I2C_EN/PIN

PRE_SEL

10

20

21

27

36

40

19

30

GND

VCC_3.3V

100YQ

GND

EQ_SEL/A0

HDMI_SEL/A1

TX_TERM_CTL

SLEW_CTL

VCC_3.3V

CAD_DET

2YQ

15

16

I2C_SCL

I2C_SDA

SCL_CTL

SDA_CTL

10uF

0.1uF 0.1uF

Optional

42

22

65lQ

OE

65lQ

0.1uF

VDD_1.1V

VSADJ

13

43

CEC

VCC

VCC_3.3V

0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF

7YQ

1%

10uF

14

24

41

23

37 48

VDD_1.1V

Note 1: For applications where the GPU or Sink does not support clock stretching the DDC lines from the GPU/DP TX

should bypass the SCL_SRC and SDA_SRC but still connect to the SCL_SNK and SDA_SNK pins on the DP159.

The SCL_SRC and SDA_SRC pins must be pulled to ground. Note that if the GPU/DP TX cannot support the 5V

DDC lines from the connector, a level shifter is needed to step down the 5V signals to the voltage level the GPU/DP

TX can support.

图 31. Implementation for Motherboard 2

42

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ZHCSE15F –JULY 2015–REVISED MAY 2018

Application Information (接下页)

图 32 shows the SNx5DP159 in the dongle application. It uses the unified structure on DisplayPort connector.

SNx5DP159 has to identify if the signal comes from DDC or from AUX in I²C-over-AUX format. Due to the AUX

channel needed, use only the RGZ package for this application.

Dongle

SNx5DP159RGZ

DisplayPort

Plug

HDMI/DVI

Receptacle

12

1

3

2

5

8

35

34

32

31

29

28

26

25

33

0.1uF

2

5

2

3

TMDS_D2p

IN_D2p

IN_D2n

IN_D1p

IN_D1n

IN_D0p

IN_D0n

IN_CLKp

IN_CLKn

HPD_SRC

OUT_D2p

ML0p

ML0n

ML1p

ML1n

ML2p

ML2n

ML3p

ML3n

GND1

10

9

TMDS_D2n

TMDS_D1p

TMDS_D1n

TMDS_D0p

TMDS_D0n

TMDS_CLKp

TMDS_CLKn

HPD

GND2

GND3

GND4

GND5

GND6

GND2

OUT_D2n

OUT_D1p

OUT_D1n

OUT_D0p

OUT_D0n

OUT_CLKp

8

4

5

GND3

11

14

17

6

7

11

16

6

GND4

7

6

8

GND5

9

19

4

9

DP_PWR_RTN

10

12

3

11

12

4

1

OUT_CLKn

HPD_SNK

18

19

18

HPD

5V

5VCC

DP_PWR

3.3V

5V

20

21

22

23

13

CASE_GND1

CASE_GND2

CASE_GND3

CASE_GND4

CEC

2YQ

15

17

DDC_SCL

DDC_SDA

38

39

18

15

16

46

47

AUX_CHp/DDC_CLK

SCL_SRC

SDA_SRC

SCL_SNK

SDA_SNK

CEC_EN

AUX_CHn/DDC_DATA

DP_PWR

3.3V

CEC_EN

45

44

1aQ

0.01uF

NC

AUX_SRCp

AUX_SRCn

65lQ

1

SWAP/POL

I2C_EN/PIN

PRE_SEL

NC

17

10

20

21

27

36

40

21

22

23

24

EQ_SEL/A0

HDMI_SEL/A1

TX_TERM_CTL

SLEW_CTL

THERMAL PAD

GND

CASE_GND1

CASE_GND2

CASE_GND3

CASE_GND4

41

7

GND

19

30

GND

65lQ

1aQ

0.01uF

42

22

OE

DP_PWR

3.3V

100YQ

0.1uF

DP_PWR_RTN

DP_PWR

3.3V

VSADJ

15

16

SCL_CTL

SDA_CTL

100YQ

DP_PWR

3.3V

7.06YQ

1%

CONFIG1

(CAD_DET)

13

20

100YQ

10uF

0.1uF 0.1uF

DP_PWR

3.3V

VDD_1.1V

V-REG

5V

14

24

13 43

23

37 48

DP_PWR

3.3V

DP_PWR

3.3V

VDD_1.1V

HDMI Adaptor Only

27YQ

14

CONFIG2

(CEC)

10uF

CEC

0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF

NC for DVI

27K installed for

HDMI

CEC_EN

图 32. SNx5DP159 in Dongle Application

10.1.2 DDC Pullup Resistors

注

This section is for information only and subject to change depending upon system

implementation.

43

SN65DP159, SN75DP159

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www.ti.com.cn

Application Information (接下页)

The pullup resistor value is determined by two requirements:

A. The maximum sink current of the I²C buffer:

The maximum sink current is 3-mA or slightly higher for an I²C driver supporting standard-mode I²C[4]

operation.

VCC

=

R_up(min)

Isink

(1)

B. The maximum transition time on the bus:

The maximum transition time, T, of an I²C bus is set by an RC time constant, where R is the pullup resistor

value, and C is the total load capacitance. The parameter, k, can be calculated from 公式 3 by solving for t,

the times at which certain voltage thresholds are reached. Different input threshold combinations introduce

different values of t. 表 11 summarizes the possible values of k under different threshold combinations.

T = k ´RC

(2)

-t

æ

ö

÷

RC

ç

V(t) = VCC´ 1- e

ç

÷

è

ø

(3)

表 11. Value k Upon Different Input Threshold Voltages

V_th–\V_th+

0.7 V_CC

1.0986

1.0415

0.9808

0.9163

0.8473

0.65 V_CC

0.9445

0.8873

0.8267

0.7621

0.6931

0.6 V_CC

0.8109

0.7538

0.6931

0.6286

0.5596

0.55 V_CC

0.6931

0.6360

0.5754

0.5108

0.4418

0.5 V_CC

0.5878

0.5306

0.4700

0.4055

0.3365

0.45 V_CC

0.4925

0.4353

0.3747

0.3102

0.2412

0.4 V_CC

0.4055

0.3483

0.2877

0.2231

0.1542

0.35 V_CC

0.3254

0.2683

0.2076

0.1431

0.0741

0.3 V_CC

0.2513

0.1942

0.1335

0.0690

0.1 VCC

0.15 VCC

0.2 VCC

0.25 VCC

0.3 VCC

From 公式 1, R_up(min)= 5.5-V / 3-mA = 1.83-kΩ to operate the bus under a 5-V pullup voltage and provide less

than 3-mA when the I²C device is driving the bus to a low state. If a higher sink current, for example 4 mA, is

allowed, R_up(min)can be as low as 1.375-kΩ.

If DDC is working at a standard mode of 100-Kbps, the maximum transition time, T, is fixed, 1 μs, and using the

k values from 表 11, the recommended maximum total resistance of the pullup resistors on an I²C bus can be

calculated for different system setups. If DDC is working in a fast mode of 400-kbps, the transition time should be

set at 300 ns, according to I²C[4] specification.

To support the maximum load capacitance specified in the HDMI specification, C_cable(max)= 700-pF, C_source= 50-

pF, C_i= 50-pF, and R_(max)can be calculated as shown in 表 12.

表 12. Pullup Resistor Upon Different Threshold Voltages and 800-pF Loads

V_th–\V_th+

0.1 VCC

0.15 VCC

0.2 VCC

0.25 VCC

0.3 VCC

0.7 V_CC

1.14

1.2

0.65 V_CC

1.32

0.6 V_CC

1.54

1.66

1.8

0.55 V_CC

1.8

0.5 V_CC

2.13

0.45 V_CC

2.54

0.4 V_CC

3.08

3.59

4.35

5.6

0.35 V_CC

3.84

0.3 V_CC

4.97

6.44

9.36

18.12

—

UNIT

kΩ

1.41

1.97

2.36

2.87

4.66

kΩ

1.27

1.36

1.48

1.51

2.17

2.66

3.34

6.02

kΩ

1.64

1.99

2.23

2.45

3.08

4.03

8.74

kΩ

1.8

2.83

3.72

5.18

8.11

16.87

kΩ

To accommodate the 3-mA drive current specification, a narrower threshold voltage range is required to support

a maximum 800-pF load capacitance for a standard-mode I²C bus.

44

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10.2 Typical Application

HDMI/DVI

40-Pin

Receptacle

1

30

29

27

26

25

24

22

21

0.1uF

1

2

TMDS_D2p

ML0p

IN_D2p

IN_D2n

IN_D1p

IN_D1n

IN_D0p

IN_D0n

IN_CLKp

IN_CLKn

HPD_SRC

OUT_D2p

OUT_D2n

OUT_D1p

OUT_D1n

OUT_D0p

OUT_D0n

GND1

3

4

5

0.1uF

TMDS_D2n

TMDS_D1p

GND2

GND3

GND4

GND5

GND6

ML0n

8

0.1uF

4

ML1p

11

14

17

6

0.1uF

5

TMDS_D1n

TMDS_D0p

TMDS_D0n

TMDS_CLKp

TMDS_CLKn

CEC

ML1n

7

0.1uF

6

ML2p

9

0.1uF

7

ML2n

10

12

0.1uF

9

ML3p

OUT_CLKp

OUT_CLKn

0.1uF

10

3

ML3n

5V

13

HPD

CEC

20

21

22

23

2YQ

CASE_GND1

DDC_SCL CASE_GND2

DDC_SDA CASE_GND3

3.3V

2YQ

32

33

28

15

16

19

SCL_SNK

SDA_SNK

HPD_SNK

2YQ

38

39

DDC_SCL

DDC_SDA

SCL_SRC

SDA_SRC

HPD

CASE_GND4

VCC

3.3V

0.01uF

100YQ

VCC

CAD_DET

65lQ

2YQ

13

14

SCL_CTL

SDA_CTL

I2C_SCL

I2C_SDA

10uF

0.1uF 0.1uF

8

I2C_EN/PIN

PRE_SEL

16

17

23

Optional

36

18

EQ_SEL/A0

HDMI_SEL/A1

SLEW_CTL

OE

0.1uF

34

VSADJ

CEC

6.5YQ

1%

65lQ

15

35

GND

VDD

GND

THERMAL PAD

10uF

0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF

11

37

12

20

19

31 40

VCC

VDD

图 33. Implementation for Motherboard 1 Schematic

10.2.1 Design Requirements

The SNx5DP159 can be designed into many types of applications. All applications have certain requirements for

the system to work properly. Two voltage rails are required to support the lowest possible power consumption.

The OE pin must have a 0.1-µF capacitor to ground. This pin can be driven by a processor but the pin needs to

change states after voltage rails have stabilized. Configure the device by using I²C. Pin strapping is provided as

I²C is not available in all cases. Because sources may have different naming conventions, confirm the link

between the source and the SNx5DP159 is correctly mapped. A swap function is provided for the input pins in

case signaling is reversed between the source and the device. For the control pins the values provided below are

when they are being controlled by a micro-controller. If this is not the case then using the 65-kΩ for a pull up for

high, pulled down for low, and left floating for mid level.

45

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www.ti.com.cn

表 13. Design Parameters

DESIGN PARAMETER

VALUE

V_CC

V_DD

3.3 V

1.1 V

Main link input voltage

V_ID= 75 mVpp to 1.2 Vpp

65-kΩ pulled to GND

No Connect

Control pin Low

Control pin Mid

Control pin High

Vsadj resistor

65-kΩ pulled to 3.3-V

7.06-kΩ

Main link AC decoupling capacitor 75 to 200 nF, recommend 100 nF

10.2.2 Detailed Design Procedure

The SNx5DP159 is a signal conditioner that provides AC coupling to DC coupling level shifting, to support Dual

Mode DisplayPort-capable GPUs or GPUs with AC-coupled drive capability to support HDMI or DVI connectors

and compliance. Signal conditioning is accomplished using receive equalization, retiming, and output driver

configurability. The transmitter drives 2 to 3 inches of board trace and connector.

Designing in the SNx5DP159 requires the following:

•

Determine the loss profile between the GPU and the HDMI/DVI connector.

Based upon the loss profile and signal swing, determine the optimal location for the SNx5DP159, to pass

electrical compliance.

•

Use the typical application drawings in Use Case of SNx5DP159 for information on using the AC coupling

capacitors and control pin resistors.

The DP159 has a receiver adaptive equalizer by default but can also be configured for fixed value

equalization using the EQ_SEL control pin.

Set the VOD, pre-emphasis, termination, and edge rate levels to support compliance by using the appropriate

Vsadj resistor value and by setting the PRE_SEL, SLEW_CTL, and TX_TERM_CTL control pins.

Adding pre-emphasis will improve performance on bandwidth limited channels and make steeper transitions.

V_ODcan be increased to compensate for DC losses and have a sheerer slope. SLEW_CTL handle transition

inclination. Making the transition sharper will improve skew performance.

•

The thermal pad must be connected to ground.

See the schematics in Application Information on recommended decouple capacitors from VCC pins to

ground.

10.2.3 Application Curve

图 34. 5.94 Gbps Compliance Eye Mask

46

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ZHCSE15F –JULY 2015–REVISED MAY 2018

10.3 System Example

10.3.1 Compliance Testing

Compliance testing is very system design specific. Properly designing the system and configuring the DP159 can

help pass transmitter compliance for the system. The following information is the starting point to help prepare for

compliance test. As each system is different there are many features in the DP159 to help tune the circuit. These

include V_ODadjust by changing the Vsadj resistor value or using I²C. Other knobs to turn are pre/de-emphasis

and slew rate control. Passing both HDMI2.0 and HDMI1.4b compliance is easier to accomplish when using I²C

as this provides more fine tuning capability.

For the SNx5DP159RGZ:

Pin Strapping

HDMI2.0 & HDMI1.4b

Vsadj Resistor = 7.06-kΩ

PRE_SEL = NC for 0-dB

TX_TERM_CTL = NC for Auto Select

SLEW_CTL = NC

I²C Control

HDMI2.0 & HDMI1.4b

Vsadj Resistor = 7.06 kΩ

PRE_SEL = Reg0Ch[1:0] = 00 (labeled HDMI_TWPST)

TX_TERM_CTL =

•

Reg0Bh[4:3] = 00 → No term; HDMI1.4b < 2Gbps (This may be best value for all HDMI1.4b)

Reg0Bh[4:3] = 01 → 150 to 300 Ω; HDMI1.4b > 2Gbps

Reg0Bh[4:3] = 11 → 75 to 150 Ω; HDMI2.0

SLEW_CTL = Reg0Bh[7:6] = 10

For the SNx5DP159RSB:

Pin Strapping

HDMI2.0 and HDMI1.4b

Vsadj Resistor = 6.5 kΩ

PRE_SEL = L for –2 dB

TX_TERM_CTL = NC for Auto Select

SLEW_CTL = NC

I²C

HDMI2.0

Vsadj Resistor = 6.5 kΩ

PRE_SEL = Reg0Ch[1:0] = 01 (labeled HDMI_TWPST)

TX_TERM_CTL = Reg0Bh[4:3] = 11

SLEW_CTL = Reg0Bh[7:6] = 10

HDMI1.4b

Vsadj Resistor = 6.5 kΩ

VSWING_DATA & VSWING_CLK to -7% = Reg0Ch[7:2] = 111111

PRE_SEL = Reg0Ch[1:0] = 00: (Labeled HDMI_TWPST)

TX_TERM_CTL: Reg0Bh[4:3]

•

<2 Gbps = 00 for no termination (This may be best value for all HDMI1.4b)

>2 Gbps and < 3.4 Gbps = 01 for 150 to 300 Ω

SLEW_CTL = Reg0Bh[7:6] = 10

47

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www.ti.com.cn

11 Power Supply Recommendations

11.1 Power Management

To minimize the power consumption of customer application, SNx5DP159 uses dual power supply. V_CCis 3.3-V

with 10% range to support the I/O voltage. The V_DDis 1.00-V to 1.27-V range to supply the internal digital control

circuit. v operates in two different working states. See 表 14 for conditions for each mode. When OE is

deasserted and then reasserted the device will rest to its default configurations. If different configurations were

programmed using I²C then the device will have to be reprogrammed.

•

Power-down mode:

OE = Low puts the device into its lowest power state by shutting down all function blocks

–

When OE is re-asserted the transitions from L → H will create a reset and if the device is programmed

through I²C it will have to be reprogrammed.

–

OE = High, HPD_SNK = Low

Writing a 1 to register 09h[3]

•

Normal operation: Working in redriver or retimer

When HPD asserts, the device CDR and output will enable based on the signal detector circuit result

HPD_SRC = HPD_SNK in all conditions. The HPD channel operational when V_CCover 3-V.

注

When the SNx5DP159 is put into a power down state using the OE pin the I²C registers

are cleared. The TMDS_CLOCK_RATIO_STATUS bit will be cleared in all power down

states. If cleared and HDMI2.0 resolutions are to be supported, the SNx5DP159 expects

the source to write a 1 to this bit location. If this does not happen the PLL will not be set

properly and no video may be evident.

表 14. Control Logic and Mode of Operation

INPUTS⁽¹⁾

HPD_SNK

STATUS

MODE

SDA_CTL

SCL_CTL

OUT_Dx

OUT_CLK

AUX_SRC±

(48 PIN ONLY)

Mode of

Operation

OE

L

HPD_SRC

IN_Dx

High-Z

DDC

Power-down

mode

H

L

X

H

L

Disabled

High-Z

Disabled

Disable

Power-down

mode

H

Active

Power-down

mode when a one

is written to 09h[3]

H

X

H

High-Z

Disabled

Disable

H

Redriver

Retimer

H

RX active

Active

TX active

Active

Normal operation

(1) L = LOW, H = HIGH

TMDS output termination control impacts the operating power.

表 15. Control Logic and Mode of Operation

INPUTS⁽¹⁾

HPD_SNK

STATUS

MODE

SDA_CTL

SCL_CTL

OUT_Dx

OUT_CLK

OE

Mode of Operation

HPD_SRC

IN_Dx

DDC

H

L

X

H

L

High-Z

Disabled

Active

High-Z

Disabled

Power-down mode

H

High-Z

Power-down mode

when a one is written

to 09h[3]

H

X

H

High-Z

Active

High-Z

Disabled

H

Redriver

Retimer

H

RX active

Active

TX active

Active

Normal operation

(1) L = LOW, H = HIGH

48

SN65DP159, SN75DP159

www.ti.com.cn

ZHCSE15F –JULY 2015–REVISED MAY 2018

TMDS output termination control impacts the operating power.

12 Layout

12.1 Layout Guidelines

TI recommends to use at a minimum a four layer stack up to accomplish a low-EMI PCB design. TI recommends

six layers because the SNx5DP159 is a two voltage rail device.

•

Routing the high-speed input DisplayPort traces and TMDS output traces on the top layer avoids the use of

vias (and their discontinuities) and allows for clean interconnects from the HDMI connectors to the repeater

inputs and from the repeater output to the subsequent receiver circuit. It is important to match the electrical

length of these high speed traces to minimize both inter-pair and intra-pair skew.

•

Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for

transmission line interconnects and provides an excellent low-inductance path for the return current flow.

•

Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance.

Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

•

If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to

the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also

the power and ground plane of each power system can be placed closer together, thus increasing the high-

frequency bypass capacitance significantly.

•

The control pin pullup and pulldown resistors are shown in application section for reference. If a high is

needed only use the pull up. If a low is needed only use the pull down. If mid level is to be selected do not

use either resistors and leave the pin floating/No connect.

Layer 1: TMDS signal layer

5 to 10 mils

Layer 2: Ground

Layer 3: V_CC

Layer 2: Ground plane

20 to 40 mils

Layer 4: V_DD

Layer 3: Power plane

Layer 5: Ground

5 to 10 mils

Layer 6: Control signal layer

Layer 4: Control signal layer

图 35. Recommended 4- or 6-Layer Stack for a Receiver PCB Design

49

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www.ti.com.cn

12.2 Layout Examples

图 36. Layout Example for the DP159RSB

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SN65DP159, SN75DP159

www.ti.com.cn

ZHCSE15F –JULY 2015–REVISED MAY 2018

Layout Examples (接下页)

100nF

AUX_SRCn

100nF

AUX_SRCp

SCL_SRC

SLEW_CTL

SDA_SNK

5V

2kQ

V_CC

2kQ

OE

V_CC

5V

SCL_SNK

SDA_SRC

Match High Speed traces

length as close as possible to

minimize Skew

65kQ

V_CC

SWAP/POL

65kQ

GND

65kQ

V_CC

TX_TERM_CTL

100nF

1

65kQ

GND

IN_D2p/n

OUT_D2p/n

HPD_SNK

HPD_SRC

IN_D1p/n

100nF

OUT_D1p/n

100nF

GND

100nF

IN_D0p/n

OUT_D0p/n

65kQ

V_CC

TEST/A1

GND

65kQ

V_CC

I2C_EN/PIN

65kQ

GND

OUT_CLKp/n

100nF

IN_CLKp/n

SCL_CTL

Place V_CCand V_DDdecoupling

caps as close to V_CCand V_DD

pins as possible

V_CC

2kQ

Note 1: CEC_EN

VSADJ

This pin is either NC or can be

routed to control a CEC enable

FET

SDA_CTL

Match High Speed traces

length as close as possible to

minimize Skew

图 37. Layout Example for the DP159RGZ

12.3 Thermal Considerations

On a high-K board: TI recommends to solder the PowerPAD™ onto the thermal land. A thermal land is the area

of solder-tinned-copper underneath the PowerPAD package. On a high-K board, the SNx5DP159 device can

operate over the full temperature range by soldering the PowerPAD onto the thermal land without vias.

On a low-K board: For the device to operate across the temperature range on a low-K board, a 1-oz Cu trace

connecting the GND pins to the thermal land must be used. A simulation shows R_θJA= 100.84°C/W allowing 545-

mW power dissipation at 70°C ambient temperature.

A general PCB design guide for PowerPAD packages is provided in PowerPAD Thermally Enhanced Package,

SLMA002.

51

SN65DP159, SN75DP159

ZHCSE15F –JULY 2015–REVISED MAY 2018

www.ti.com.cn

13 器件和文档支持

13.1 相关链接

下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链

接。

表 16. 相关链接

器件

产品文件夹

请单击此处

样片与购买

请单击此处

技术文档

请单击此处

工具与软件

请单击此处

支持和社区

请单击此处

SN65DP159

SN75DP159

13.2 文档支持

13.2.1 相关文档

本节标识的文档均在本数据表中引用。为简化文本，数据表中的大多数参考文献均使用方括号 [文档标签] 标识的文

本，而不使用完整的文档标题。

(1) [双模] VESA DisplayPort 双模标准版本 1.1，2013 年 2 月 8 日

(2) [HDMI1.4b] 高清多媒体接口规范版本 1.4b，2011 年 10 月

(3) [HDMI2.0] 高清多媒体接口规范版本 2.0a，2015 年 3 月

(4) [I²C] I²C 总线规范版本 2.1，2000 年 1 月

(5) [HDMI1.4b CTS] 高清多媒体接口 CTS 版本 1.4b，2011 年 10 月

(6) [HDMI2.0 CTS] 高清多媒体接口 CTS 版本 2.0k，2015 年 6 月

13.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

13.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

13.5 商标

PowerPAD, E2E are trademarks of Texas Instruments.

Blu-Ray is a trademark of Blu-ray Disc Accociation.

13.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

13.7 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

14 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查看左侧的导航栏。

52

GENERIC PACKAGE VIEW

RGZ 48

7 x 7, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUADFLAT PACK- NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224671/A

www.ti.com

PACKAGE OUTLINE

RGZ0048B

VQFN - 1 mm max height

S

C

A

L

E

2

.

0

PLASTIC QUAD FLATPACK - NO LEAD

7.15

6.85

A

B

PIN 1 INDEX AREA

7.15

6.85

1 MAX

C

SEATING PLANE

0.05

0.00

0.08 C

2X 5.5

4.1 0.1

(0.2) TYP

EXPOSED

THERMAL PAD

13

24

44X 0.5

12

25

49

SYMM

2X

5.5

0.30

0.18

36

48X

1

0.1

0.05

C B A

48

37

SYMM

PIN 1 ID

(OPTIONAL)

0.5

0.3

48X

4218795/B 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGZ0048B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

4.1)

(1.115) TYP

(0.685)

TYP

37

48

48X (0.6)

1

36

48X (0.24)

(1.115)

TYP

44X (0.5)

(0.685)

TYP

SYMM

49

(

0.2) TYP

VIA

(6.8)

(R0.05)

TYP

12

25

13

24

SYMM

(6.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:12X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218795/B 02/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGZ0048B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.37)

TYP

37

48

48X (0.6)

1

36

48X (0.24)

44X (0.5)

(1.37)

TYP

SYMM

49

(R0.05) TYP

(6.8)

9X

METAL

TYP

(

1.17)

12

25

13

24

SYMM

(6.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 49

73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:12X

4218795/B 02/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

RSB0040E

WQFN - 0.8 mm max height

S

C

A

L

E

2

.

7

0

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

B

A

PIN 1 INDEX AREA

5.1

4.9

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 3.6

(0.2) TYP

EXPOSED

11

20

THERMAL PAD

36X 0.4

10

21

2X

41

SYMM

3.6

3.15 0.1

1

30

0.25

0.15

40X

40

31

PIN 1 ID

(OPTIONAL)

0.1

C A B

SYMM

0.5

0.3

0.05

40X

4219096/A 11/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RSB0040E

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.15)

SYMM

40

31

40X (0.6)

40X (0.2)

1

30

36X (0.4)

41

SYMM

(4.8)

(1.325)

(

0.2) TYP

VIA

10

21

(R0.05)

TYP

11

20

(1.325)

(4.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219096/A 11/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RSB0040E

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.785)

4X ( 1.37)

40

31

40X (0.6)

1

30

40X (0.2)

36X (0.4)

SYMM

(0.785)

(4.8)

41

(R0.05) TYP

10

21

METAL

TYP

20

11

SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 41

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4219096/A 11/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	SN75DP159RSBT
厂家：	TEXAS INSTRUMENTS
描述：	工作温度为 -40°C 至 85°C 的 6Gbps DP++ 1.1 至 HDMI 2.0 重定时器 \| RSB \| 40 \| 0 to 85 商用集成电路
文件：	总65页 (文件大小：3058K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN75DP159RSBT [TI]

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