SN75HVD1176DG4 [TI]
RS-485 Transceivers;
| 型号： | SN75HVD1176DG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | RS-485 Transceivers 驱动 信息通信管理 光电二极管 接口集成电路 驱动器 |
| 文件： | 总17页 (文件大小：247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLLS563C − JULY 2003 − REVISED APRIL 2005
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FEATURES
APPLICATIONS
D
Optimized for PROFIBUS Networks
D
D
D
Process Automation
− Meets the Requirements of EN 50170
− Signaling Rates Up to 40 Mbps
− Differential Output Exceeds 2.1 V
(54 Ω Load)
−
−
−
Chemical Production
Brewing and Distillation
Paper Mills
− Low Bus Capacitance: 10 pF (Max)
Factory Automation
D
D
D
D
D
D
D
D
D
Meets the Requirements of TIA/EIA-485-A
ESD Protection Exceeds 10 kV HBM
−
−
−
Automobile Production
Rolling, Pressing, Stamping Machines
Networked Sensors
Failsafe Receiver for Bus Open, Short, Idle
Up to 160 Transceivers on a Bus
General RS-485 Networks
Low Skew During Output Transitions and
Driver Enabling / Disabling
−
−
−
Motor/Motion Control
HVAC and Building Automation Networks
Networked Security Stations
Common-Mode Rejection Up to 50 MHz
Short-Circuit Current Limit
Hot Swap Capable
Thermal Shutdown Protection
DESCRIPTION
These devices are half-duplex differential transceivers, with characteristics optimized for use in PROFIBUS (EN 50170)
applications. The driver output differential voltage exceeds the Profibus requirements of 2.1 V with a 54-Ω load. A signaling
rate of up to 40 Mbps allows technology growth to high data transfer speeds. The low bus capacitance provides low signal
distortion.
The SN65HVD1176 and SN75HVD1176 meet or exceed the requirements of ANSI standard TIA/EIA-485-A (RS-485) for
differential data transmission across twisted-pair networks. The driver outputs and receiver inputs are tied together to form
a half-duplex bus port, with one-fifth unit load, allowing up to 160 nodes on a single bus. The receiver output stays at logic
high when the bus lines are shorted, left open, or when no driver is active. The driver outputs are in high impedance when
the supply voltage is below 2.5 V to prevent bus disturbance during power cycling or during live insertion to the bus.
An internal current limit protects the transceiver bus pins in short-circuit fault conditions by limiting the output current to a
constant value. Thermal shutdown circuitry protects the device against damage due to excessive power dissipation caused
by faulty loading and drive conditions.
The SN75HVD1176 is characterized for operation at temperatures from 0°C to 70°C. The SN65HVD1176 is characterized
for operation at temperatures from −40°C to 85°C.
D PACKAGE
(TOP VIEW)
LOGIC DIAGRAM (POSITIVE LOGIC)
A
B
D
R
RE
DE
D
V
B
A
1
2
3
4
8
7
6
5
CC
DE
GND
RE
R
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢉꢊ ꢋ ꢆꢏ ꢕ ꢓꢍ ꢋꢁ ꢆ ꢔꢓꢔ ꢗꢘ ꢙꢚ ꢛ ꢜꢝ ꢞꢗꢚꢘ ꢗꢟ ꢠꢡ ꢛ ꢛ ꢢꢘꢞ ꢝꢟ ꢚꢙ ꢣꢡꢤ ꢥꢗꢠ ꢝꢞꢗ ꢚꢘ ꢦꢝ ꢞꢢꢧ ꢉꢛ ꢚꢦꢡ ꢠꢞꢟ
ꢠ ꢚꢘ ꢙꢚꢛ ꢜ ꢞꢚ ꢟ ꢣꢢ ꢠ ꢗ ꢙꢗ ꢠ ꢝ ꢞꢗ ꢚꢘꢟ ꢣ ꢢꢛ ꢞꢨꢢ ꢞꢢ ꢛ ꢜꢟ ꢚꢙ ꢓꢢꢩ ꢝꢟ ꢍꢘꢟ ꢞꢛ ꢡꢜ ꢢꢘꢞ ꢟ ꢟꢞ ꢝꢘꢦ ꢝꢛ ꢦ ꢪ ꢝꢛ ꢛ ꢝ ꢘꢞꢫꢧ
ꢉꢛ ꢚ ꢦꢡꢠ ꢞ ꢗꢚ ꢘ ꢣꢛ ꢚ ꢠ ꢢ ꢟ ꢟ ꢗꢘ ꢬ ꢦꢚ ꢢ ꢟ ꢘꢚꢞ ꢘꢢ ꢠꢢ ꢟꢟ ꢝꢛ ꢗꢥ ꢫ ꢗꢘꢠ ꢥꢡꢦ ꢢ ꢞꢢ ꢟꢞꢗ ꢘꢬ ꢚꢙ ꢝꢥ ꢥ ꢣꢝ ꢛ ꢝꢜ ꢢꢞꢢ ꢛ ꢟꢧ
Copyright 2003, Texas Instruments Incorporated
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SLLS563C − JULY 2003 − REVISED APRIL 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
(1)
T
PACKAGED DEVICES
MARKED AS
VN1176
A
0°C to 70°C
SN75HVD1176D
−40°C to 85°C
SN65HVD1176D
VP1176
(1)
The D package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD1176DR).
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted
(1)
SN65HVD1176, SN75HVD1176
−0.5 V to 7 V
−9 V to 14 V
−40 V to 40 V
−0.5 V to 7 V
−10 mA to 10 mA
4 kV
(2)
Supply voltage , V
CC
Voltage at any bus I/O terminal
Voltage input, transient pulse, A and B, (through 100 Ω, see Figure 14)
Voltage input at any D, DE or RE terminal
Receiver output current, I
O
All pins
(3)
Human Body Model, (HBM)
Electrostatic discharge
Junction temperature, T
Bus terminals and GND
10 kV
150°C
J
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(2)
(3)
Tested in accordance with JEDEC standard 22. test method A114−A.
RECOMMENDED OPERATING CONDITIONS
MIN
4.75
−7
NOM MAX UNIT
Supply voltage, V
CC
5
5.25
12
Voltage at either bus I/O terminal
A, B
High−level input voltage, V
IH
2
V
CC
0.8
V
D, DE, RE
Low−level input voltage, V
IL
0
Differential input voltage, V
A with respect to B
Driver
−12
−70
−8
12
70
ID
Output current
mA
Receiver
8
SN65HVD1176
SN75HVD1176
−40
0
130
130
Ω
Ω
Ω
(1)
Junction temperature, T
J
Differential load resistance, R
54
L
Signaling rate, 1/t
U1
40 Mbps
(1)
See the Thermal Characteristics table for more information on maintenance of this requirement.
2
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DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
(1)
MIN TYP
PARAMETER
TEST CONDITIONS
MAX
UNIT
V
Open-circuit output voltage
A or B,
R = 54 Ω,
No load
0
V
CC
V
O
See Figure 1
With common-mode loading,
(V from −7 V to 12 V)
2.1
2.9
2.7
L
V
Steady-state differential output voltage magnitude
V
OD(SS)
2.1
TEST
See Figure 2
Change in steady-state differential output voltage
between logic states
∆|V
|
See Figure 1 and Figure 6
−0.2
2
0
2.5
0
0.2
3
V
V
V
V
OD(SS)
V
Steady-state common-mode output voltage
OC(SS)
Change in steady-state common-mode output
voltage
∆V
OC(SS)
−0.2
0.2
See Figure 5
V
Peak-to-peak common-mode output voltage
Differential output voltage over and under shoot
Input current
0.5
OC(PP)
V
R = 54 Ω, C = 50 pF, See Figure 6
10%
50
V
OD(PP)
OD(RING)
L
L
I
I
D, DE
−50
µA
I
Output current with power off
V
< = 2.5 V
O(OFF)
CC
DE at 0 V
See receiver line input
current
I
High impedance state output current
Peak short-circuit output current
OZ
I
V
V
= −7 V to 12 V
> 4 V,
−250
60
250
mA
mA
OS(P)
OS
OS
90
135
−60
DE at V
See Figure 8
,
CC
Output driving low
I
Steady-state short-circuit output current
Differential output capacitance
OS(SS)
V
OS
< 1 V,
−135
−90
Output driving high
C
See receiver C
I
OD
(1)
All typical values are at V
CC
= 5 V and 25°C.
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
4
TYP
7
MAX
10
10
2
UNIT
ns
t
t
t
t
t
t
Propagation delay time low-level-to-high-level output
Propagation delay time high-level-to-low-level output
Pulse skew | t – t
PLH
PHL
sk(p)
r
4
7
ns
R = 54 Ω, C = 50 pF,
L
L
|
0
ns
PLH PHL
See Figure 3
Differential output rise time
Differential output fall time
Output transition skew
2
2
3
7.5
7.5
1
ns
3
ns
f
, t
t(MLH) t(MHL)
See Figure 4
0.2
ns
t
t
, t
p(AZH) p(BZH)
Propagation delay time, high-impedance-to-active output
Propagation delay time, active-to- high-impedance output
Enable skew time
10
10
20
20
1.5
2.5
4
ns
ns
ns
ns
µs
ns
, t
p(AZL) p(BZL)
t
t
, t
p(AHZ) p(BHZ)
, t
p(ALZ) p(BLZ)
RE at 0 V
R
C
= 110 Ω,
= 50 pF,
|t
|t
− t
|
|
L
L
p(AZL) p(BZH)
0.55
− t
p(AZH) p(BZL)
See Figure 7a
and 7b
|t
|t
− t
|
|
p(ALZ) p(BHZ)
Disable skew time
− t
p(AHZ) p(BLZ)
t
t
, t
Propagation delay time, high-impedance-to-active output
(from sleep mode)
p(AZH) p(BZH)
, t
p(AZL) p(BZL)
1
RE at 5 V
t
t
, t
, t
Propagation delay time, active-output-to high-impedance
(to sleep mode)
p(AHZ) p(BHZ)
p(ALZ) p(BLZ)
30
50
t
Time from application of short-circuit to current foldback
Time from application of short-circuit to thermal shutdown
See Figure 8
0.5
µs
µs
(CFB)
(TSD)
t
T
= 25°C, See Figure 8
100
A
(1)
All typical values are at V
CC
= 5 V and 25°C.
3
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RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
(1)
MIN TYP
PARAMETER
TEST CONDITIONS
= 2.4 V, I = −8 mA
MAX
UNIT
V
IT(+)
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
V
O
−80
−120
40
−20
O
See Figure 9
mV
V
IT(−)
V
O
= 0.4 V, I = 8 mA
−200
4
O
V
HYS
Hysteresis voltage (V
IT+
− V
)
mV
V
IT−
V
OH
High-level output voltage
Low-level output voltage
V
ID
= 200 mV,
I
= −8 mA, See Figure 9
= 8 mA, See Figure 9
4.6
OH
V
V
ID
= −200 mV, I
0.2
0.4
V
OL
I , I
OL
V
= 4.75 V to 5.25 V
A B
CC
CC
V = − 7 V to 12 V,
I
Other input = 0 V
Bus pin input current
−160
200
µA
I
I
A(OFF),
V
= 0V
B(OFF)
I
Receiver enable input current
RE
−50
−1
50
1
µA
µA
kΩ
I
I
High-impedance -state output current
Input resistance
RE = V
CC
OZ
R
60
I
Test input signal is a 1.5 MHz sine wave
with amplitude 1 Vpp, capacitance
measured across A and B
C
Differential input capacitance
Common mode rejection
7
4
10
pF
V
ID
See Figure 11
CMR
(1)
All typical values are at 25°C.
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
t
Propagation delay time, low-to-high level output
Propagation delay time, high-to-low level output
20
20
1
25
25
2
PLH
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
PHL
sk(p)
r
Pulse skew | t |
– t
See Figure 10
PLH PHL
Receiver output voltage rise time
2
4
Receiver output voltage fall time
2
4
f
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, low-level-to-high-impedance output
Propagation delay time, high-impedance-to-high-level output (standby to active)
Propagation delay time, high-level-to-high-impedance output (active to standby)
Propagation delay time, high-impedance-to-low-level output (standby to active)
Propagation delay time, low-level-to-high-impedance output (active to standby)
20
20
20
20
4
PZH
PHZ
PZL
PLZ
PZH
PHZ
PZL
PLZ
DE at V ,
CC
See Figure 13
ns
ns
DE at V
See Figure 14
,
CC
1
13
2
µs
ns
µs
ns
DE at 0 V,
See Figure 12
20
4
DE at 0 V
See Figure 12
13
20
SUPPLY CURRENT
over recommended operating conditions
PARAMETER
TEST CONDITIONS
Driver and receiver, RE at 0 V, DE at V , All other inputs open, no load
MIN
TYP
4
MAX
UNIT
mA
mA
mA
µA
6
6
6
5
CC
Driver only, RE at V
,
DE at V , All other inputs open, no load
3.8
3.6
0.2
CC
CC
Receiver only, RE at 0 V, DE at 0 V, All other inputs open, no load
Standby only, RE at V DE at 0 V, All other inputs open
I
Supply current
CC
,
CC
4
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PARAMETER MEASUREMENT INFORMATION
NOTES:
Test load capacitance includes probe and jig capacitance (unless otherwise specified).
Signal generator characteristics: rise and fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle, Z = 50 Ω (unless otherwise specified)
o
I
A
B
O
O
27 Ω
27 Ω
I
I
V
OD
50 pF
0 V or 3 V
D
I
V
OC
Figure 1. Driver Test Circuit, V
and V
Without Common-Mode Loading
OC
OD
375 Ω
A
V
= −7 V to 12 V
TEST
V
OD
60 Ω
375 Ω
0 V or 3 V
D
B
V
TEST
Figure 2. Driver Test Circuit, V
With Common-Mode Loading
OD
3 V
0 V
INPUT
V
OD
R
L
= 54 Ω
C
L
= 50 pF
V
OD(H)
OD(L)
Signal
Generator
90%
10%
50 Ω
OUTPUT
V
t
r
t
f
Figure 3. Driver Switching Test Circuit and Rise/Fall Time Measurement
D
1.5 V
1.5 V
t
t
PLH
PHL
A,B
50%
50%
A
B
t
t
t(MLH)
t(MHL)
50%
50%
Figure 4. Driver Switching Waveforms for Propagation Delay and Output Midpoint Time Measurements
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27 Ω
27 Ω
A
V
A
≈ 3.25 V
≈ 1.75 V
D
V
B
Signal
Generator
B
50 Ω
V
V
OC
∆V
OC(SS)
OC(PP)
50 pF
V
OC
Figure 5. Driver V
OC
Test Circuit and Waveforms
V
OD(SS)
V
OD(RING)
V
OD(PP)
0 V Differential
V
OD(RING)
V
OD(SS)
:
NOTE
V
V
is measured at four points on the output waveform, corresponding to overshoot and undershoot from the
OD(RING)
and V
steady state values.
OD(H)
OD(L)
Figure 6. V
Waveform and Definitions
OD(RING)
3 V
DE
1.5 V
R
L
= 110 Ω
V
CC
t
t
p(AZL)
p(ALZ)
A
B
C
C
= 50 pF
L
D
A
50%
50%
0 V
V
+0.5 V
OL
DE
R
= 110 Ω
L
0 V
t
p(BHZ)
−0.5 V
t
p(BZH)
Signal
Generator
50 Ω
= 50 pF
L
V
OL
B
a) D at Logic Low
3 V
t
DE
1.5 V 1.5 V
R
= 110 Ω
L
0 V
V
t
p(AZH)
p(AHZ)
−0.5 V
A
B
C
C
= 50 pF
L
D
V
OH
A
50%
3 V
R
L
= 110 Ω
DE
t
p(BLZ)
CC
t
p(BZL)
Signal
Generator
50 Ω
= 50 pF
L
50%
V
OH
+0.5 V
B
b) D at Logic High
Figure 7. Driver Enable/Disable Test
6
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250
Output
Current |mA|
135
60
I
OS
D
V
OS
Voltage
Source
time
t
(CFB)
t
(TSD)
Figure 8. Driver Short-Circuit Test Circuit and Waveforms (Short Circuit applied at Time t = 0)
I
A
A
B
I
O
R
V
A
V
I
ID
V
B
V
IC
V
O
V
A
+ V
2
B
B
Figure 9. Receiver DC Parameter Definitions
Signal
Generator
50 Ω
Input B
V
ID
1.5 V
0 V
A
B
50%
I
O
Input A
t
R
t
PHL
PLH
V
C
= 15 pF
O
V
OH
Signal
Generator
L
90%
50 Ω
Output
1.5 V
10%
V
OL
t
r
t
f
Figure 10. Receiver Switching Test Circuit and Waveforms
50 Ω
50 Ω
A
B
100 nF
R
V = A sin 2pft
1 MHz < f < 50 MHz
I
470 nF
RE
DE
D
2.2 kΩ
V
R
Scope
2.2 kΩ
V
=
offset
−2 V to 7 V
GND
V
CC
Scope
100 nF
V
shall be greater than
R
2 V throughout this test.
Figure 11. Receiver Common-Mode Rejection Test Circuit
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3 V
A
B
A
1 kΩ 1%
= 15 pF 20%
0 V or 1.5 V
1.5 V or 0 V
R
V
O
S1
B
C
L
RE
Input
Generator
V
I
50 Ω
3 V
1.5 V
V
I
0 V
V
t
PZH(2)
OH
A at 1.5 V
B at 0 V
S1 to B
1.5 V
V
O
GND
t
PZL(2)
3 V
A at 0 V
B at 1.5 V
S1 to A
1.5 V
V
O
V
OL
Figure 12. Receiver Enable Time From Standby (Driver Disabled)
D
V
V
CC
DE
CC
A
54 Ω
B
3 V
0 V
1 kΩ
R
RE
1.5 V
0 V
C
L
= 15 pF
RE
t
t
PHZ
PZH
Signal
Generator
V
OH
−0.5 V
50 Ω
V
OH
1.5 V
R
GND
Figure 13. Receiver Enable Test Circuit and Waveforms, Data Output High (Driver Active)
8
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SLLS563C − JULY 2003 − REVISED APRIL 2005
D
0 V
DE
V
CC
A
54 Ω
B
3 V
0 V
1 kΩ
R
RE
1.5 V
PZL
5 V
C
L
= 15 pF
RE
t
t
PLZ
Signal
Generator
V
CC
50 Ω
1.5 V
R
V
OL
+0.5 V
V
OL
Figure 14. Receiver Enable Test Circuit and Waveforms, Data Output Low (Driver Active)
V
TEST
100 Ω
0 V
Pulse Generator,
15 µs Duration,
1% Duty Cycle
1.5 ms
15 µs
−V
TEST
Figure 15. Test Circuit and Waveforms, Transient Over-Voltage Test
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SLLS563C − JULY 2003 − REVISED APRIL 2005
DEVICE INFORMATION
DRIVER FUNCTION TABLE
INPUT
ENABLE
OUTPUTS
D
DE
A
H
L
B
L
H
H
L
X
H
L
H
Z
Z
L
Z
Z
H
X
OPEN
H
OPEN
H = high level, L= low level, X = don’t care,
Z = high impedance (off)
RECEIVER FUNCTION TABLE
DIFFERENTIAL INPUT
= (V – V )
ENABLE
OUTPUT
V
ID
RE
R
H
?
A
B
V
≥ 0.02 V
L
ID
−0.2 V < V < −0.02 V
L
ID
V
ID
≤ −0.2 V
L
L
X
X
H
Z
Z
H
H
H
OPEN
Open circuit
Short Circuit
L
L
L
Idle (terminated) bus
H = high level, L= low level, X = don’t care,Z = high impedance (off),
? = indeterminate
(1)
THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
(2)
TYP
PARAMETERS
TEST CONDITIONS
MIN
MAX
UNITS
(4)
Low-K board , no air flow
208.3
128.7
77.6
°C/W
°C/W
°C/W
°C/W
(3)
θ
θ
Junction-to-ambient thermal resistance
JA
(5)
High-K board , no air flow
Junction-to-board thermal resistance
Junction-to-case thermal resistance
High-K board
JB
JC
θ
43.9
R
L
= 54 Ω, C = 50 pF, 0 V to 3 V
L
15 MHz, 50% duty cycle square
wave input, driver and receiver
enabled
P
D
Device power dissipation
277
318
mW
SN65HVD1176
SN75HVD1176
SN65HVD1176
SN75HVD1176
−40
0
Low-K board, no air flow,
64
89
°C
P
D
= 318 mW
T
Ambient air temperature
A
−40
0
High-K board, no air flow,
= 318 mW
°C
°C
P
D
T
(1)
(2)
(3)
Thermal shut down junction temperature
150
SD
See Application Information section for an explanation of these parameters.
All typical values are with V = 5 V and T = 25°C.
CC
A
The intent of θ specification is solely for a thermal performance comparison of one package to another in a standardized environment. This
JA
methodology is not meant to and will not predict the performance of a package in an application-specific environment.
JESD51−3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
JESD51−7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
(4)
(5)
10
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SLLS563C − JULY 2003 − REVISED APRIL 2005
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Inputs
DE Input
V
CC
V
CC
200 kΩ
500 Ω
500 Ω
Input
Input
200 kΩ
9 V
9 V
A Input
B Input
V
CC
V
CC
18 kΩ
16 V
18 kΩ
16 V
90 kΩ
90 kΩ
18 kΩ
Input
Input
18 kΩ
16 V
16 V
A and B Outputs
R Output
V
CC
V
CC
16 V
5 Ω
Output
9 V
Output
16 V
11
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SLLS563C − JULY 2003 − REVISED APRIL 2005
TYPICAL CHARACTERISTICS
DRIVER SUPPLY CURRENT
DIFFERENTIAL OUTPUT VOLTAGE
vs
vs
SIGNALING RATE
LOAD CURRENT
66
64
5
V
CC
= 5 V
V
4.5
4
100 Ω
= 5.25 V
CC
3.5
3
62
50 Ω
V
CC
= 4.75 V
60
58
2.5
2
V
= 5 V
= 25°C
= 56 Ω,
CC
1.5
T
A
R
L
1
0.5
0
DE and RE at 5 V
Input 0 V to 3 V PRBS
See Figure 3
56
54
T
A
= 255C
0
10
20
30
40
50
0
20
40
60
80
Signaling Rate − Mbps
I
L
− Load Current − mA
Figure 16
Figure 17
DRIVER OUTPUT TRANSITION SKEW
DRIVER RISE, FALL TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
4
0.35
0.3
R
C
= 54 Ω,
= 50 pF
L
L
R
C
= 54 Ω,
= 50 pF
L
L
3.75
3.5
See Figure 3
See Figure 4
V
CC
= 4.75 V
V
= 4.75 V
CC
0.25
0.2
V
CC
= 5 V
3.25
3
V
CC
= 5 V
V
CC
= 5.25 V
0.15
0.1
V
CC
= 5.25 V
2.75
2.5
0.05
0
2.25
2
−40
−15
10
35
60
85
−40
−15
10
35
60
85
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 18
Figure 19
12
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SLLS563C − JULY 2003 − REVISED APRIL 2005
DRIVER ENABLE SKEW
vs
FREE-AIR TEMPERATURE
0.7
0.6
0.5
0.4
0.3
0.2
V
= 4.75 V
CC
V
= 5.25 V
CC
V
CC
= 5 V
R
C
= 110 Ω,
L
L
= 50 pF
0.1
0
See Figure 7
−40
−15
10
35
60
85
T
A
− Free-Air Temperature − °C
Figure 20
APPLICATION INFORMATION
TI uses two test PCBs as defined by JEDEC
specifications. The low-k board gives average in-use
condition thermal performance, and it consists of a single
copper trace layer 25 mm long and 2-oz thick. The high-k
board gives best case in-use condition, and it consists of
two 1-oz buried power planes with a single copper trace
layer 25 mm long and 2-oz thick. A 4% to 50% difference
THERMAL CHARACTERISTICS OF IC
PACKAGES
q
(Junction-to-Ambient Thermal Resistance) is
JA
defined as the difference in junction temperature to
ambient temperature divided by the operating power.
in θ can be measured between these two test cards
θ
is not a constant and is a strong function of:
the PCB design (50% variation)
JA
JA
q
(Junction-to-Case Thermal Resistance) is defined
JC
D
D
D
θ
as difference in junction temperature to case divided by the
operating power. It is measured by putting the mounted
package up against a copper block cold plate to force heat
to flow from die, through the mold compound into the
copper block.
altitude (20% variation)
device power (5% variation)
can be used to compare the thermal performance of
θ
is a useful thermal characteristic when a heatsink is
JC
JA
packages if the specific test conditions are defined and
used. Standardized testing includes specification of PCB
construction, test chamber volume, sensor locations, and
applied to package. It is not a useful characteristic to
predict junction temperature because it provides
pessimistic numbers if the case temperature is measured
in a nonstandard system and junction temperatures are
the thermal characteristics of holding fixtures. θ is often
JA
misused when it is used to calculate junction temperatures
for other installations.
backed out. It can be used with θ in 1-dimensional
JB
thermal simulation of a package system.
13
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SLLS563C − JULY 2003 − REVISED APRIL 2005
q
(Junction-to-Board Thermal Resistance) is defined
θ
provides an overall thermal resistance between the die
JB
JB
as the difference in the junction temperature and the PCB
temperature at the center of the package (closest to the
and the PCB. It includes a bit of the PCB thermal
resistance (especially for BGA’s with thermal balls) and
can be used for simple 1-dimensional network analysis of
package system (see Figure 21).
die) when the PCB is clamped in a cold-plate structure. θ
JB
is only defined for the high-k test card.
Ambient Node
Calculated
q
CA
Surface Node
Calculated/Measured
q
JC
Junction
Calculated/Measured
q
JB
PC Board
Figure 21. Thermal Resistance
14
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
PACKAGING INFORMATION
Orderable Device
SN65HVD1176D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65HVD1176DR
SN75HVD1176D
SOIC
SOIC
SOIC
SOIC
D
D
D
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75HVD1176DR
SN75HVD1176DRG4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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