SN75LBC175ANR [TI]
QUAD LINE RECEIVER, PDIP16, ROHS COMPLIANT, PLASTIC, MS-001BB, DIP-16;
| 型号： | SN75LBC175ANR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUAD LINE RECEIVER, PDIP16, ROHS COMPLIANT, PLASTIC, MS-001BB, DIP-16 |
| 文件： | 总10页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LBC175, SN75LBC175
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS
SLLS171C – OCTOBER 1993 – REVISED APRIL 2000
Meet or Exceed the EIA Standards
RS-422-A, RS-423-A, RS-485, and CCITT
Recommendation V.11
D OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
1B
1A
Designed to Operate With Pulse Durations
as Short as 20 ns
CC
4B
4A
1Y
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
4Y
1,2EN
2Y
3,4EN
3Y
Input Sensitivity . . . ±200 mV
2A
Low-Power Consumption . . . 20 mA Max
Open-Circuit Fail-Safe Design
3A
2B
3B
GND
Common-Mode Input Voltage Range of
–7 V to 12 V
†
logic symbol
Pin Compatible With SN75175 and MC3486
4
EN
1,2EN
description
2
1
6
7
3
5
1A
1B
2A
2B
The SN65LBC175 and SN75LBC175 are
monolithic, quadruple, differential line receivers
with 3-state outputs and are designed to meet the
requirements of the EIA standards RS-422-A,
RS-423-A, RS-485, andCCITTRecommendation
V.11. The devices are optimized for balanced
multipointbustransmissionatdataratesuptoand
exceeding 10 million bits per second. The
receivers are enabled in pairs, with an active-high
enable input. Each differential receiver input
features high impedance, hysteresis for
increased noise immunity, and sensitivity of
±200 mV over a common-mode input voltage
range of 12 V to –7 V. The fail-safe design ensures
that when the inputs are open-circuited, the
outputs are always high. Both devices are
designed using the TI proprietary LinBiCMOS
technology allowing low power consumption, high
switching speeds, and robustness.
1Y
2Y
12
EN
3,4EN
10
9
11
13
3A
3B
4A
4B
3Y
4Y
14
15
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
logic diagram (positive logic)
4
1,2EN
These devices offer optimum performance when
used with the SN75LBC172 or SN75LBC174
quadruple line drivers. The SN65LBC175 and
SN75LBC175 are available in the 16-pin DIP (N)
2
1A
3
5
1
1Y
2Y
1B
6
2A
and small-outline inline circuit (SOIC)
packages.
D
7
2B
The SN65LBC175 is characterized over the
industrial temperature range of –40°C to 85°C.
The SN75LBC175 is characterized for operation
over the commercial temperature range of 0°C
to 70°C.
12
3,4EN
10
3A
9
11
13
3Y
4Y
3B
14
4A
15
4B
LinBiCMOS is a trademark of Texas Instruments Incorporated.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC175, SN75LBC175
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS
SLLS171C – OCTOBER 1993 – REVISED APRIL 2000
FUNCTION TABLE
(each receiver)
DIFFERENTIAL INPUTS
A–B
OUTPUT
Y
ENABLE
V
≥ 0.2 V
H
H
H
L
H
?
ID
–0.2 V < V < 0.2 V
ID
V
ID
≤ –0.2 V
L
X
Z
H
Open circuit
H
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
TYPICAL OF EN INPUT
EQUIVALENT OF A AND B INPUTS
V
CC
V
CC
V
CC
100 kΩ
3 kΩ
(A Only)
Input
Output
Input
18 kΩ
Y Output
100 kΩ
(B Only)
12 kΩ
1 kΩ
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC175, SN75LBC175
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS
SLLS171C – OCTOBER 1993 – REVISED APRIL 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
CC
Input voltage, V (A or B inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
I
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V
ID
Voltage range at Y, 1/2EN, 3/4EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
+ 0.5 V
CC
Operating free-air temperature range, T : SN65LBC175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
A
SN75LBC175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
D
N
1100 mW
8.7 mW/°C
9.2 mW/°C
709 mW
736 mW
578 mW
598 mW
1150 mW
recommended operating conditions
MIN NOM
MAX
5.25
12
UNIT
V
Supply voltage, V
CC
4.75
–7
5
Common-mode input voltage, V
IC
V
Differential input voltage, V
±6
V
ID
High-level input voltage, V
IH
2
V
EN inputs
Low-level input voltage, V
0.8
–8
16
85
70
V
IL
High-level output current, I
mA
mA
OH
Low-level output current, I
OL
SN65LBC175
SN75LBC175
–40
0
Operating free-air temperature, T
°C
A
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC175, SN75LBC175
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS
SLLS171C – OCTOBER 1993 – REVISED APRIL 2000
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
Positive-going input threshold voltage
Negative-going input threshold voltage
I
I
= –8 mA
= 16 mA
0.2
IT+
IT–
hys
IK
O
–0.2
V
O
Hysteresis voltage (V
IT+
– V
)
45
–0.9
4.5
mV
V
IT–
Enable input clamp voltage
High-level output voltage
Low-level output voltage
I = –18 mA
–1.5
I
V
V
V
V
V
V
V
V
V
V
= 200 mV,
I
I
= –8 mA
= 8 mA
3.5
V
OH
OL
ID
ID
O
OH
= –200 mV,
0.3
0.5
±20
1
V
OL
I
High-impedance-state output current
= 0 V to V
= 12 V,
= 12 V,
= –7 V,
= –7 V,
= 5 V
µA
mA
mA
mA
mA
µA
µA
mA
OZ
CC
V
V
V
V
= 5 V, Other inputs at 0 V
= 0 V, Other inputs at 0 V
= 5 V, Other inputs at 0 V
= 0 V, Other inputs at 0 V
0.7
0.8
IH
IH
IH
IH
IH
IL
CC
CC
CC
CC
1
I
I
Bus input current
A or B inputs
–0.5
–0.4
–0.8
–0.8
±20
–20
I
I
I
High-level enable input current
Low-level enable input current
Short-circuit output current
IH
= 0 V
IL
= 0
–80 –120
OS
O
Outputs enabled,
Outputs disabled
I
O
= 0,
V
ID
= 5 V
11
20
I
Supply current
mA
CC
0.9
1.4
†
All typical values are at V
= 5 V and T = 25°C.
A
CC
switching characteristics, V
= 5 V, C = 15 pF, T = 25°C
L A
CC
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
30
30
30
30
40
30
6
UNIT
ns
t
t
t
t
t
t
t
t
Propagation delay time, high- to low-level output
Propagation delay time, low- to high-level output
Output enable time to high level
11
11
22
22
17
18
30
23
4
V
ID
= –1.5 V to 1.5 V,
See Figure 1
PHL
PLH
PZH
PZL
PHZ
PLZ
sk(p)
t
ns
See Figure 2
See Figure 3
See Figure 2
See Figure 3
See Figure 2
See Figure 1
ns
Output enable time to low level
ns
Output disable time from high level
Output disable time from low level
ns
ns
Pulse skew (|t
– t
PHL PLH
|)
ns
Transition time
3
10
ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC175, SN75LBC175
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS
SLLS171C – OCTOBER 1993 – REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
1.5 V
Input
0 V
0 V
Generator
– 1.5 V
(see Note A)
50 Ω
Output
= 15 pF
t
t
PHL
PLH
V
OH
C
90%
10%
L
Output
1.3 V
1.3 V
(see Note B)
V
OL
t
2 V
t
t
t
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 1. t
and t
Test Circuit and Voltage Waveforms
PLH
PHL
V
CC
2 kΩ
Input
Output
1.5 V
S1
3 V
0 V
1.3 V
1.3 V
C
= 15 pF
L
(see Note B)
t
t
PHZ
0.5 V
PZH
5 kΩ
See Note C
V
Generator
(see Note A)
OH
Output
S1 Open
1.3 V
S1 Closed
≈ 1.4 V
0 V
50 Ω
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, t ≤ 6 ns,
r
t ≤ 6 ns, Z = 50 Ω.
f
O
B.
C
includes probe and jig capacitance.
L
C. All diodes are 1N916 or equivalent.
Figure 2. t
and t
Test Circuit and Voltage Waveforms
PHZ
PZH
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC175, SN75LBC175
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS
SLLS171C – OCTOBER 1993 – REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
V
CC
2 kΩ
Output
1.5 V
3 V
0 V
Input
t
C
= 15 pF
1.3 V
1.3 V
L
(see Note B)
5 kΩ
See Note C
t
PZL
PLZ
S2 Closed
≈ 1.4 V
Generator
(see Note A)
S2 Open
Output
1.3 V
50 Ω
V
OL
S2
0.5 V
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, t ≤ 6 ns,
r
t ≤ 6 ns, Z = 50 Ω.
f
O
B.
C
includes probe and jig capacitance.
L
C. All diodes are 1N916 or equivalent.
Figure 3. t
and t
Test Circuit and Voltage Waveforms
PZL
PLZ
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
DIFFERENTIAL INPUT VOLTAGE
5.5
5
4.5
4
V
T
A
= 5 V
CC
= 25°C
V
CC
= 5.25 V
4.5
4
3.5
3
V
CC
= 5 V
3.5
3
V
CC
= 4.75 V
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
V
T
A
= 0.2 V
ID
= 25°C
0.5
0
0
– 4 – 8 – 12 – 16 – 20 – 24 – 28 – 32 – 36 – 40
0
10 20 30 40 50 60 70 80 90 100
I
– High-Level Output Current – mA
V
ID
– Differential Input Voltage – mV
OH
Figure 4
Figure 5
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC175, SN75LBC175
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS
SLLS171C – OCTOBER 1993 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
AVERAGE SUPPLY CURRENT
vs
vs
LOW-LEVEL OUTPUT CURRENT
FREQUENCY
660
600
540
480
420
360
300
240
180
120
60
14
12
10
8
T
V
= 25°C
A
T
V
V
= 25°C
A
= 5 V
CC
= 5 V
CC
= 200 mV
ID
6
4
2
0
0
0
3
6
9
12 15 18 21 24 27 30
10 K
100 K
2 M
10 M
100 M
I
– Low-Level Output Current – mA
f – Frequency – Hz
OL
Figure 6
Figure 7
INPUT CURRENT
vs
INPUT VOLTAGE
PROPAGATION DELAY TIME
vs
(COMPLEMENTARY INPUT AT 0 V)
FREE-AIR TEMPERATURE
1
24.5
24
T
V
= 25°C
V
C
= 5 V
= 15 pF
= ±1.5 V
A
CC
L
= 5 V
0.8
0.6
CC
V
IO
0.4
t
PHL
0.2
23.5
23
0
– 0.2
– 0.4
– 0.6
– 0.8
– 1
t
PLH
22.5
22
The shaded region of this graph represents
more than 1 unit load per RS-485.
– 8 – 6 – 4 – 2
0
2
4
6
8
10 12
– 40
– 20
0
20
40
60
80
100
V – Input Voltage – V
I
T
A
– Free-Air Temperature – °C
Figure 8
Figure 9
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC175, SN75LBC175
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS
SLLS171C – OCTOBER 1993 – REVISED APRIL 2000
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–8°
0.044 (1,12)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC175, SN75LBC175
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS
SLLS171C – OCTOBER 1993 – REVISED APRIL 2000
MECHANICAL DATA
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
PINS **
14
16
18
20
DIM
0.775
(19,69)
0.775
(19,69)
0.920
(23.37)
0.975
(24,77)
A MAX
A
16
9
0.745
(18,92)
0.745
(18,92)
0.850
(21.59)
0.940
(23,88)
A MIN
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.020 (0,51) MIN
0.310 (7,87)
0.290 (7,37)
0.035 (0,89) MAX
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
14/18 PIN ONLY
4040049/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明