SN75LBC182 [TI]
DIFFERENTIAL BUS TRANSCEIVER; 差动总线收发器型号: | SN75LBC182 |
厂家: | TEXAS INSTRUMENTS |
描述: | DIFFERENTIAL BUS TRANSCEIVER |
文件: | 总13页 (文件大小:190K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN65LBC182
SN75LBC182
SLLS500 – MAY 2001
DIFFERENTIAL BUS TRANSCEIVER
The driver outputs and the receiver inputs connect
internally to form a differential input/output (I/O) bus port
that is designed to offer minimum loading to the bus.
This port operates over a wide range of common-mode
voltage, making the device suitable for party-line
applications. The device also includes additional
features for party-line data buses in electrically noisy
environment applications such as industrial process
control or power inverters.
FEATURES
D
D
One-Fourth Unit Load Allows up to 128
Devices on a Bus
ESD Protection for Bus Terminals:
– ±15-kV Human Body Model
– ±8-kV IEC61000-4-2, Contact Discharge
– ±15-kV IEC61000-4-2, Air-Gap Discharge
D
D
Meets or Exceeds the Requirements of ANSI
Standard TIA/EIA-485-A and ISO 8482: 1987(E)
The SN75LBC182 and SN65LBC182 bus pins also
exhibit a high input resistance equivalent to one-fourth
unit load allowing connection of up to 128 similar
devices on the bus. The high ESD tolerance protects
the device for cabled connections. (For an even higher
level of protection, see the SN65/75LBC184, literature
number SLLS236.)
Controlled Driver Output-Voltage Slew Rates
Allow Longer Cable Stub Lengths
†
D
D
D
D
D
D
Designed for Signaling Rates Up to 250-kbps
Low Disabled Supply Current . . . 250 µA Max
Thermal Shutdown Protection
Open-Circuit Fail-Safe Receiver Design
Receiver Input Hysteresis . . . 70 mV Typ
The
differential
driver
design
incorporates
slew-rate-controlled outputs sufficient to transmit data
up to 250 kbps. Slew-rate control allows longer
unterminated cable runs and longer stub lengths from
the main backbone than possible with uncontrolled
voltage transitions. The receiver design provides a
fail-safe output of a high level when the inputs are left
floating (open circuit). Very low device supply current
canbeachievedbydisablingthedriverandthereceiver.
Glitch-Free Power-Up and Power-Down
Protection
APPLICATIONS
D
D
D
Utility Meters
Industrial Process Control
Building Automation
The SN65LBC182 is characterized for operation from
–40°C to 85°C, and the SN75LBC182 is characterized
for operation from 0°C to 70°C.
DESCRIPTION
The SN65LBC182 and SN75LBC182 are differential
datalinetransceiverswithahighlevelofESDprotection
inthetrade-standardfootprintoftheSN75176. Theyare
designed for balanced transmission lines and meet
ANSI standard TIA/EIA-485-A and ISO 8482. The
SN65LBC182 and SN75LBC182 combine a 3-state,
differential line driver and differential input line receiver,
both of which operate from a single 5-V power supply.
The driver and receiver have active-high and active-low
enables, respectively, which can be externally
connected together to function as a direction control.
functional block diagram
3
DE
6
A
B
4
2
D
RE
R
7
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
PRODUCTION DATA information is current as of publication date.
Copyright 2001, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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SN65LBC182
SN75LBC182
SLLS500 – MAY 2001
schematic of inputs and outputs
SN65LBC182D (Marked as 6LB182)
SN75LBC182D (Marked as 7LB182)
SN65LBC182P (Marked as 65LBC182)
SN75LBC182P (Marked as 75LBC182)
(TOP VIEW)
V
CC
1
2
3
4
R
8
7
6
5
V
B
CC
RE
DE
A
A Port
Only
GND
D
16 kΩ
12 µA
Nominal
72 kΩ
A or B
I/O
16 kΩ
B Port
Only
12 µA
Nominal
Function Tables
DRIVER
INPUT
D
ENABLE
DE
OUTPUTS
A
H
L
B
L
H
L
H
H
L
H
Z
L
X
Z
H
Open
H
RECEIVER
DIFFERENTIAL
INPUTS
ENABLE
RE
OUTPUT
R
V
≥
L
L
L
H
L
H
?
ID 0.2 V
-0.2V < V < 0.2 V
ID
V
≤
L
ID -0.2 V
X
Z
H
Open
AVAILABLE OPTIONS
PACKAGE
†
T
A
PLASTIC SMALL-OUTLINE
(JEDEC MS-012)
PLASTIC DUAL-IN-LINE PACKAGE
(JEDEC MS-001)
0°C to 70°C
SN75LBC182D
SN65LBC182D
SN75LBC182P
SN65LBC182P
–40°C to 85°C
†
Add R suffix for taped and reel.
2
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SN65LBC182
SN75LBC182
SLLS500 – MAY 2001
†
absolute maximum ratings
Supply voltage range, (see Note 1) V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Voltage range at any bus terminal (A or B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to 15 V
Input voltage, V (D, DE, R or RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
I
Electrostatic discharge: Human body model (see Note 2)
A, B, GND . . . . . . . . . . . . . . . . . . . . . . 15 kV
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . 3 kV
A, B, GND . . . . . . . . . . . . . . . . . . . . . . . 8 kV
A, B, GND . . . . . . . . . . . . . . . . . . . . . . 15 kV
Contact discharge (IEC61000-4-2)
Air discharge (IEC61000-4-2)
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with JEDEC Standard 22, Test Method A114-A.
DISSIPATION RATING TABLE
‡
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
D
P
725 mW
5.8 mW/°C
9.2 mW/°C
464 mW
736 mW
377 mW
598 mW
1150 mW
‡
This is the inverse ofthejunction-to-ambientthermalresistancewhenboard-mountedandwithnoairflow.
NOTE: The maximum operating junction temperature is internally limited. Use the dissipation rating table
to operate below this temperature
recommended operating conditions
MIN NOM
MAX
5.25
12
UNIT
V
Supply voltage, V
CC
4.75
–7
2
5
Voltage at any bus I/O terminal (separately or common mode) V or V
IC
V
I
High-level input voltage, V
IH
D, DE, RE
V
V
Low-level input voltage, V
0.8
12
60
4
IL
Differential input voltage, V (see Note 3)
ID
–12
–60
–8
Driver
Output current, I
mA
O
Receiver
SN65LBC182
SN75LBC182
–40
0
85
70
Operating free-air temperature, T
°C
A
NOTE 3: Differential input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
3
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SN65LBC182
SN75LBC182
SLLS500 – MAY 2001
driver electrical characteristics over recommended operating conditions
†
PARAMETER
Input clamp voltage
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
I = –18 mA
–1.5
V
V
V
V
IK
I
Output voltage
I
O
= 0
0
V
V
V
O
CC
R
= 54 Ω,
See Figure 1
1.5
1.5
–0.2
1
2.2
2.2
L
CC
|V
|
Differential output voltage
OD
V
= –7 V to 12 V, See Figure 2
test
CC
0.2
∆V
Change in magnitude of differential output voltage
Steady-state common-mode output voltage
OD
See Figure 1
V
3
OC(SS)
V
V
Change in steady-state common-mode output
voltage
∆V
–0.2
0.2
OC(SS)
OC(PP)
See Figures 1 and 4
Peak-to-peak change in common-mode output
voltage during state transitions
V
0.8
I
I
I
I
High-impedance output current
High-level input current (D, DE)
Low-level input current (D, DE)
Short-circuit output current
SN75LBC182
See receiver input currents
OZ
V = 2.4 V
I
50
µA
µA
IH
IL
V = 0.4 V
I
–50
V
O
= –7 V to 12 V
–250
250
25
mA
OS
12
12
I
Supply current
No load, DE at V
,
RE at V
CC
mA
CC
CC
SN65LBC182
30
†
All typical values are at V
= 5 V and T = 25°C.
A
CC
driver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
0.25
0.25
TYP
0.72
0.73
MAX
1.2
1.2
1.3
1.3
0.15
3.5
3.5
3.5
3.5
UNIT
t
t
t
t
t
t
t
t
t
Differential output signal rise time
r
Differential output signal fall time
f
R
= 54 Ω,
See Figure 3
C = 50 pF,
L
L
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
µs
PLH
PHL
sk(p)
PZH
PHZ
PZL
PLZ
Pulse skew (t
– t
PHL PLH
)
0.075
Output enable time to high level
Output disable time from high level
Output enable time to low level
Output disable time from low level
R
R
= 110 Ω,
= 110 Ω,
See Figure 5
See Figure 6
µs
µs
L
L
4
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SN65LBC182
SN75LBC182
SLLS500 – MAY 2001
receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
V
Positive-going input threshold voltage
Negative-going input threshold voltage
0.2
IT+
IT–
hys
IK
V
–0.2
Hysteresis voltage (V
IT+
– V
)
IT-
70
mV
V
Enable-input clamp voltage
High-level output voltage
Low-level output voltage
I = –18 mA
–1.5
I
V
V
V
V
V
V
V
V
V
= 200 mV, I = –8 mA, See Figure 7
2.8
V
OH
OL
ID
ID
O
O
= 200 mV, I = 4 mA,
O
See Figure 7
0.4
±1
V
I
High-impedance-state output current
= 0.4 to 2.4 V
µA
OZ
= 12 V, V
= 12 V, V
= –7 V, V
= –7 V, V
= 2 V
= 5 V
= 0 V
= 5 V
= 0 V
250
250
IH
IH
IH
IH
IH
IL
CC
CC
CC
CC
I
I
Bus input current
Other input at 0 V
µA
–200
–200
I
I
High-level input current (RE)
Low-level input current (RE)
50
µA
µA
mA
µA
IH
= 0.8 V
–50
IL
DE at 0 V, RE at 0 V
3.5
I
Supply current
No load
= 5 V and T = 25°C.
CC
DE at 0 V, RE at V
175
250
CC
†
All typical values are at V
CC
A
receiver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
20
MAX
UNIT
t
t
t
t
t
t
t
t
Differential output signal rise time
Differential output signal fall time
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Output enable time to high level
r
20
f
C
= 50 pF,
See Figure 7
ns
L
150
150
100
100
100
100
PLH
PHL
PZH
PZL
PHZ
PLZ
ns
Output enable time to low level
See Figure 8
Output disable time from high level
Output disable time from low level
ns
ns
t
Pulse skew
t
– t
50
sk(p)
PHL PLH
5
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SN65LBC182
SN75LBC182
SLLS500 – MAY 2001
PARAMETER MEASUREMENT INFORMATION
I
O
27 Ω
27 Ω
I
I
†
V
OD
50 pF
0 V or 3 V
I
O
V
O
V
OC
V
O
†
Includes probe and jig capacitance
Figure 1. Driver Test Circuit, V
and V
Without Common-Mode Loading
OC
OD
375 Ω
V
OD
V
TEST
= –7 V to 12 V
Input
60 Ω
375 Ω
V
TEST
Figure 2. Driver Test Circuit, V
With Common-Mode Loading
OD
3 V
0 V
Input
1.5 V
1.5 V
R
= 54 Ω
L
}
C
= 50 pF
V
OD
L
t
t
PHL
Signal
Generator
PLH
50 Ω
{
V
OD(H)
90% 90%
Output
0 V
10%
10%
V
OD(L)
t
t
f
r
†
‡
PRR = 1 MHz, 50% duty cycle, t < 6 ns, t < 6 ns, Z = 50 Ω
Includes probe and jig capacitance
r
f
o
Figure 3. Driver Switching Test Circuit and Waveforms
V
OC
V
OC(PP)
∆V
OC(SS)
Figure 4. V
Definitions
OC
6
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SN65LBC182
SN75LBC182
SLLS500 – MAY 2001
PARAMETER MEASUREMENT INFORMATION
Output
3 V
S1
Input
1.5 V 1.5 V
0 or 3 V
0 V
0.5 V
t
PZH
C
= 50 pF
R
= 110 Ω
L
L
V
OH
≈ 0 V
(see Note B)
Generator
(see Note A)
Output
50 Ω
2.3 V
V
off
t
PHZ
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1.25 kHz, 50% duty cycle, t ≤ 10 ns,
r
t ≤ 10 ns, Z = 50 Ω.
f
O
B.
C
includes probe and jig capacitance.
L
Figure 5. Driver t
and t
Test Circuit and Voltage Waveforms
PZH
PHZ
5 V
3 V
0 V
Input
1.5 V
1.5 V
R
= 110 Ω
L
S1
Output
0 or 3 V
t
PZL
t
PLZ
C
= 50 pF
L
5 V
0.5 V
(see Note B)
Generator
(see Note A)
50 Ω
2.3 V
Output
V
OL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1.25 kHz, 50% duty cycle, t ≤ 10 ns,
r
t ≤ 10 ns, Z = 50 Ω.
f
O
B.
C
includes probe and jig capacitance.
L
Figure 6. Driver t
and t
Test Circuit and Voltage Waveforms
PZL
A
PLZ
I
I
I
O
R
V
ID
B
V
I
Input
Output
V
O
50 pF
(see Note A)
1.5 V
RE
3 V
Inputs
Output
1.5 V
0 V
50%
50%
t
t
PHL
PLH
V
OH
50%
90%
90%
10%
10%
V
OL
t
t
f
r
NOTE A: This value includes probe and jig capacitance (± 10%).
Figure 7. Receiver t
and t
Test Circuit and Voltage Waveforms
PLH
PHL
7
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SN65LBC182
SN75LBC182
SLLS500 – MAY 2001
PARAMETER MEASUREMENT INFORMATION
5 V
A
620 Ω
0 V or 3 V
R
B
1.5 V
Input
620 Ω
V
O
50 pF
(see Note A)
RE
3 V
0 V
A
3 V
0 V
3 V
0 V
Inputs
Output
RE
1.5 V
t
t
t
t
PZL
PHZ
PZH
PLZ
V
OH
2.5 V
0.5 V
0.5 V
V
O
0.5 V
0.5 V
2.5 V
V
OL
NOTE A: This value includes probe and jig capacitance (± 10%).
Figure 8. Receiver t
, t
, t
, and t
Test Circuit and Voltage Waveforms
PZL PLZ PZH
PHZ
8
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SN65LBC182
SN75LBC182
SLLS500 – MAY 2001
TYPICAL CHARACTERISTICS
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
DRIVER PROPAGATION DELAY TIME
vs
vs
TEMPERATURE
TEMPERATURE
3.0
2.5
2.0
1.5
1.0
800
780
760
740
720
700
680
660
640
R
= 54 Ω
L
V
CC
= 5.25 V
t
t
PHL
PLH
V
CC
= 5 V
V
= 4.75 V
CC
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
T
A
– Free-Air Temperature – °C
T
– Free-Air Temperature – °C
A
Figure 9
Figure 10
DRIVER TRANSITION TIME
DIFFERENTIAL OUTPUT VOLTAGE
vs
vs
TEMPERATURE
OUTPUT CURRENT
900
800
700
600
500
400
300
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
t
f
V
= 5.5 V
CC
t
r
V
CC
= 4.5 V
V
CC
= 5 V
–40
–20
0
20
40
60
80
0
10 20 30 40 50 60 70 80 90 100
T
– Free-Air Temperature – °C
A
I
O
– Output Current – mA
Figure 11
Figure 12
9
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SN65LBC182
SN75LBC182
SLLS500 – MAY 2001
TYPICAL CHARACTERISTICS
RECEIVER INPUT CURRENT
vs
INPUT VOLTAGE
0.25
0.20
0.15
0.10
0.05
A, B (V
= 0 V)
CC
–0.00
–0.05
–0.10
–0.15
–0.20
B (V
CC
= 5 V)
A (V
= 5 V)
CC
–10
–5
0
5
10
15
V – Input Voltage – V
I
Figure 13
APPLICATION INFORMATION
SN65LBC182
SN75LBC182
SN65LBC182
SN75LBC182
R
R
T
T
Up to 128
Transceivers
NOTE A: The line should be terminated at both ends in its characteristic impedance (R = Z ). Stub lengths off the main line should be kept
T
O
as short as possible.
Figure 14. Typical Application Circuit
10
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SN65LBC182
SN75LBC182
SLLS500 – MAY 2001
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
DIM
0.020 (0,51)
0.010 (0,25)
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
M
0.014 (0,35)
A MAX
A MIN
14
8
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
7
A
0.010 (0,25)
0°–ā8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
4040047/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Four center pins are connected to die mount pad.
E. Falls within JEDEC MS-012
11
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SN65LBC182
SN75LBC182
SLLS500 – MAY 2001
MECHANICAL INFORMATION
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE PACKAGE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–ā15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
4040082/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
12
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accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
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