SN75LVDM977DGG [TI]
9-CHANNEL DUAL-MODE TRANSCEIVERS; 9通道双模式收发器件
| 型号： | SN75LVDM977DGG |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 9-CHANNEL DUAL-MODE TRANSCEIVERS |
| 文件： | 总28页 (文件大小：426K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
DGG PACKAGE
(TOP VIEW)
9 Channels for the Data and Control Paths
of the Small Computer Systems Interface
(SCSI)
INV/NON
GND
CDE2
CDE1
CDE0
9B+
1
56
55
54
53
52
51
50
49
48
47
46
45
Supports Single-Ended and Low-Voltage
Differential (LVD) SCSI
2
GND
3
CMOS Input Levels (’LVDM976) or TTL
Input Levels (’LVDM977) Available
1A
4
1DE/RE
2A
9B–
5
Includes DIFFSENS Comparators on CDE0
8B+
6
2DE/RE
3A
8B–
7
Single-Ended Receivers Include Noise
Pulse Rejection Circuitry
7B+
8
3DE/RE
4A
7B–
9
Packaged in Thin Shrink Small-Outline
Package With 20-Mil Terminal Pitch
6B+
10
11
12
4DE/RE
6B–
Low Disabled Supply Current 7 mA
Maximum
V
V
CC
CC
GND 13
44 GND
Power-Up/Down Glitch Protection
GND 14
43 GND
Bus is High-Impedance With V
= 1.5 V
15
16
17
18
19
20
21
22
23
24
25
26
27
28
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
GND
GND
GND
GND
GND
CC
Pin-Compatible With the SN75976ADGG
High-Voltage Differential Transceiver
V
V
CC
5A
CC
description
5B+
5B–
4B+
4B–
3B+
3B–
2B+
2B–
1B+
1B–
5DE/RE
6A
The SN75LVDM976 and SN75LVDM977 have
nine transceivers for transmitting or receiving the
signals to or from a SCSI data bus. They offer
electrical compatibility to both the single-ended
signaling of X3.277:1996–SCSI–3 Parallel Inter-
face (Fast–20) and the new low-voltage differen-
tial signaling method of proposed standard
1142–D SCSI Parallel Interface – 2 (SPI–2).
6DE/RE
7A
7DE/RE
8A
8DE/RE
9A
9DE/RE
The differential drivers are nonsymmetrical. The
SCSI bus uses a dc bias on the line to allow
terminated fail safe and wired-OR signaling. This bias can be as high as 125 mV and induces a difference in
the high-to-low and low-to-high transition times of a symmetrical driver. In order to reduce pulse skew, an LVD
SCSI driver’s output characteristics become nonsymmetrical. In other words, there is more assertion current
than negation current to or from the driver. This allows the actual differential signal voltage on the bus to be
symmetrical about 0 V. Even though the driver output characteristics are nonsymmetrical, the design of the
’LVDM976 drivers maintains balanced signaling. Balanced means that the current that flows in each signal line
is nearly equal but opposite in direction and is one of the keys to the low-noise performance of a differential bus.
AVAILABLE OPTIONS
PACKAGE
TSSOP
(DGG)
TSSOP
(DGG)
T
A
CMOS INPUT LEVELS
TTL INPUTS LEVELS
SN75LVDM976DGG
SN75LVDM976DGGR
SN75LVDM977DGG
SN75LVDM977DGGR
0°C to 70°C
†
†
†
The R suffix designates a taped and reeled package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
description (continued)
The signal symmetry requirements of the LVD-SCSI bus mean you can no longer obtain logical inversion of a
signal by simply reversing the differential signal connections. This requires the ability to invert the logic
convention through the INV/NON terminal. This input would be a low for SCSI controllers with active-high data
and high for active-low data. In either case, the B+ signals of the transceiver must be connected to the SIGNAL+
line of the SCSI bus and the B– of the transceiver to the SIGNAL– line.
The CDE0 input incorporates a window comparator to detect the status of the DIFFSENS line of a SCSI bus.
This line is below 0.5 V, if using single-ended signals, between 1.7 V and 1.9 V if low-voltage differential, and
between 2.4 V and 5.5 V if high-voltage differential. The outputs assume the characteristics of single-ended or
LVDaccordingly or place the outputs into high-impedance, when HVD is detected. This, and the INV/NONinput,
are the only differences to the trade-standard function of the SN75976A HVD transceiver.
Two options are offered to minimize the signal noise margins on the interface between the communications
controller and the transceiver. The SN75LVDM976 has logic input voltage thresholds of about 0.5 V . The
CC
SN75LVDM977 has a fixed logic input voltage threshold of about 1.5 V. The input voltage threshold should be
selected to be near the middle of the output voltage swing of the corresponding driver circuit.
The SN75LVDM976 and SN75LVDM977 are characterized for operation over an free-air temperature range of
T = 0°C to 70°C.
A
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
logic diagram (positive logic)
2.4 V
A
CDE1
(Internal)
+
–
LVD
CDE0
B
–
+
0.5 V
(Internal)
SE
INV/NON
1DEb
1REb
1DE/RE
1DEb
1B–
1DEa
1A
1B+
1DEa
1REa
1REb
1REa
2A
2DE/RE
3A
3DE/RE
4A
2B–
2B+
3B–
3B+
4B–
4B+
Channel 2
Channel 3
Channel 4
4DE/RE
INV/NON
SE
LVD
CDE2
5A
5DE/RE
6A
6DE/RE
7A
5B–
5B+
6B–
6B+
7B–
7B+
8B–
8B+
Channel 5
Channel 6
Channel 7
Channel 8
7DE/RE
8A
8DE/RE
9DE/RE
9A
INV/NON
SE
LVD
9DEb
9REb
9DEb
9DEa
9B–
9B+
9DEa
9REa
9REb
9REa
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
logic diagrams and function tables
FUNCTION TABLE
Inputs
Outputs
B–
(B+ – B–)
≥ 30 mV
DE/RE
A
NA
NA
NA
NA
L
B+
B–
Z
A
L
V
A
ID
B+
V
ID
L
L
Z
Z
Z
Z
H
L
–30 mV < V < 30 mV
Z
?
ID
–30 mV
DE/RE
V
ID
L
Z
H
?
Open circuit
L
Z
NA
NA
H
H
L
Z
Z
Figure 1. Inverting LVD Transceiver
H
H
FUNCTION TABLE
Inputs
DE/RE
Outputs
A
B–
B+
B–
H
A
NA
NA
NA
L
B+
L
B–
Z
A
L
DE/RE
L
L
L
L
Z
H
?
Open circuit
L
L
Z
NA
NA
H
H
L
H
L
Z
Z
H
L
Figure 2. Inverting Single-Ended Transceiver
A
FUNCTION TABLE
B–
Input
Outputs
A
L
B+
B–
H
L
L
B+
H
L
Figure 3. Inverting Single-Ended Driver
FUNCTION TABLE
Input Outputs
B–
A
A
L
B+
B–
L
B+
H
L
H
H
Figure 4. Inverting LVD Driver
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
logic diagrams and function tables (continued)
FUNCTION TABLE
B–
Input
Outputs
A
A
L
B+
B–
H
B+
L
H
H
L
Figure 5. Noninverting LVD Driver
FUNCTION TABLE
Inputs
Outputs
B–
ID
B+
(B+ – B–)
≥ 30 mV
DE/RE
A
NA
NA
NA
NA
L
B+
B–
Z
A
H
?
V
A
V
L
L
Z
Z
Z
Z
L
ID
–30 mV < V < 30 mV
Z
DE/RE
ID
≤ –30 mV
V
L
Z
L
ID
Open circuit
L
Z
?
NA
NA
H
H
H
L
Z
Z
Figure 6. Noninverting LVD Transceiver
H
H
FUNCTION TABLE
A
B–
Inputs
DE/RE
Outputs
DE/RE
B–
H
A
NA
NA
NA
L
B+
L
B–
Z
A
H
L
L
L
L
L
Z
B+
Open Circuit
L
L
Z
?
NA
NA
H
H
L
L
Z
Z
Figure 7. Noninverting Single-Ended Transceiver
H
L
H
B–
B+
A
FUNCTION TABLE
Input
Outputs
A
L
B+
B–
L
L
L
H
H
Figure 8. Noninverting Single-Ended Driver
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
1B–
1B–
1B+
1B–
1B+
1A
1A
1A
2A
3A
4A
1B+
1DE/RE
1DE/RE
2B–
2B+
2B–
2B+
2B–
2B+
2A
2A
2DE/RE
2DE/RE
3B–
3B+
3B–
3B+
3B–
3B+
3A
3A
3DE/RE
3DE/RE
4B–
4B+
4B–
4B+
4B–
4B+
4A
4A
4DE/RE
4DE/RE
5B–
5B+
5B–
5B+
5B–
5B+
5A
5A
5A
5DE/RE
5DE/RE
6B–
6B+
6B–
6B+
6B–
6B+
6A
6A
6A
7A
6DE/RE
6DE/RE
7B–
7B+
7B–
7B+
7B–
7B+
7A
7A
7DE/RE
7DE/RE
8B–
8B+
8B–
8B+
8B–
8B+
8A
8A
8A
8DE/RE
8DE/RE
9B–
9B+
9B–
9B+
9B–
9B+
9A
9A
9A
9DE/RE
9DE/RE
9DE/RE
Control Inputs
Control Inputs
Control Inputs
CDE0 0.7 V < V < 1.9 V
CDE0
INV/NON
CDE1
0.7 V < V < 1.9 V
I
CDE0
INV/NON
CDE1
0.7 V < V < 1.9 V
I
I
L
L
L
L
L
INV/NON
CDE1
L
H
L
CDE2
CDE2
H
CDE2
(a)
(b)
(c)
Figure 9. Logic Diagrams
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
1B–
1B+
1B–
1B+
1A
1A
1B–
1B+
1A
2A
3A
4A
5A
6A
7A
8A
1DE/RE
1DE/RE
2B–
2B+
2B–
2B+
2A
2A
2B–
2B+
2DE/RE
2DE/RE
3B–
3B+
3B–
3B+
3A
3A
3B–
3B+
3DE/RE
3DE/RE
4B–
4B+
4B–
4B+
4A
4A
4B–
4B+
4DE/RE
4DE/RE
5B–
5B+
5B–
5B+
5A
5A
6A
7A
8A
5B–
5B+
5DE/RE
6B–
6B+
6B–
6B+
6A
6B–
6B+
6DE/RE
7B–
7B+
7B–
7B+
7A
7B–
7B+
7DE/RE
8B–
8B+
8B–
8B+
8A
8B–
8B+
8DE/RE
9B–
9B+
9B–
9B+
9B–
9B+
9A
9A
9A
9DE/RE
9DE/RE
9DE/RE
Control Inputs
CDE0 0.7 V < V < 1.9 V
Control Inputs
Control Inputs
CDE0
INV/NON
CDE1
0.7 V < V < 1.9 V
I
CDE0
INV/NON
CDE1
0.7 V < V < 1.9 V
I
I
INV/NON
CDE1
L
H
H
H
L
L
H
L
CDE2
CDE2
CDE2
H
(a)
(b)
(C)
Figure 10. Logic Diagrams
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
1A
1B–
1A
1B–
1B–
1DE/RE
1DE/RE
1A
2A
3A
4A
5A
6A
7A
8A
1B+
1B+
2B–
1B+
2B–
2A
2A
2B–
2B+
2DE/RE
2DE/RE
2B+
3B–
2B+
3B–
3A
3A
3B–
3B+
3DE/RE
3DE/RE
3B+
4B–
3B+
4B–
4A
4A
4B–
4B+
4DE/RE
4DE/RE
4B+
5B–
4B+
5B–
5A
5A
6A
7A
8A
5B–
5B+
5DE/RE
5B+
5B+
6B–
6A
6B–
6B+
6B–
6B+
6DE/RE
6B+
7B–
7A
7B–
7B+
7B–
7B+
7DE/RE
7B+
8B–
8A
8B–
8B+
8B–
8B+
8DE/RE
8B+
9B–
9A
9A
9B–
9B+
9B–
9B+
9DE/RE
9DE/RE
9A
9DE/RE
9B+
Control Inputs
CDE0 V < 0.5 V
INV/NON
Control Inputs
CDE0 V < 0.5 V
INV/NON
Control Inputs
I
I
CDE0
INV/NON
CDE1
0.7 V < V < 1.9 V
I
L
L
H
L
L
L
H
H
H
CDE1
CDE2
CDE1
CDE2
CDE2
(c)
(b)
(a)
Figure 11. Logic Diagrams
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
1A
2A
1B–
1B+
1A
2A
1B–
1B+
1A
1B–
1DE/RE
1B+
2B–
2B–
2B+
2A
2B–
2B+
2DE/RE
2B+
3B–
3A
4A
3B–
3B+
3B–
3B+
3A
4A
5A
6A
3A
3DE/RE
3B+
4B–
4B–
4B+
4B–
4B+
4A
4DE/RE
4B+
5B–
5A
5B–
5B–
5B+
5A
5DE/RE
5DE/RE
5B+
6B–
5B+
6B–
6A
6B–
6B+
6A
6DE/RE
6DE/RE
6B+
7B–
6B+
7B–
7A
7A
8A
7B–
7B+
7A
7DE/RE
7DE/RE
7B+
8B–
7B+
8B–
8A
8B–
8B+
8A
8DE/RE
8DE/RE
8B+
9B–
8B+
9B–
9A
9A
9B–
9B+
9A
9DE/RE
9DE/RE
9DE/RE
9B+
9B+
Control Inputs
CDE0 V < 0.5 V
INV/NON
Control Inputs
CDE0 V < 0.5 V
INV/NON
Control Inputs
CDE0 V < 0.5 V
INV/NON
I
I
I
L
H
L
L
H
L
L
CDE1
CDE2
CDE1
CDE2
H
H
CDE1
CDE2
(a)
(b)
(c)
Figure 12. Logic Diagrams
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
1B–
1B+
1A
1A
2A
1B–
1B+
1A
2A
1B–
1DE/RE
1B+
2B–
2A
2B–
2B+
2B–
2B+
2DE/RE
2B+
3B–
3B–
3B+
3B–
3B+
3A
3A
4A
3A
4A
5A
6A
3DE/RE
3B+
4B–
4B–
4B+
4A
4B–
4B+
4DE/RE
4B+
5B–
5B–
5A
6A
7A
8A
5A
5B–
5B+
5DE/RE
5B+
5B+
6B–
6A
6B–
6B+
6B–
6B+
6DE/RE
6B+
7B–
7A
7B–
7B+
7A
8A
7B–
7B+
7DE/RE
7B+
8B–
8A
8B–
8B+
8B–
8B+
8DE/RE
8B+
9B–
9B–
9B+
9A
9DE/RE
9A
9A
9B–
9B+
9DE/RE
9DE/RE
9B+
Control Inputs
CDE0 V < 0.5 V
INV/NON
Control Inputs
CDE0 V < 0.5 V
INV/NON
Control Inputs
CDE0 V < 0.5 V
INV/NON
I
I
I
H
H
H
H
H
L
H
L
CDE1
CDE2
CDE1
CDE2
CDE1
CDE2
H
(b)
(b)
(a)
Figure 13. Logic Diagrams
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
1A
1B–
1B+
High Z
High Z
High Z
2A
2B–
2B+
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
3B–
3B+
3A
High Z
High Z
4A
4B–
4B+
High Z
High Z
5A
5B–
5B+
High Z
High Z
6A
6B–
6B+
High Z
High Z
7A
7B–
7B+
High Z
High Z
8A
8B–
8B+
High Z
High Z
9A
9B–
9B+
High Z
High Z
Control Inputs
CDE0
INV/NON
CDE1
V > 2.5 V
I
X
X
X
CDE2
Figure 14. Logic Diagrams
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
input and output equivalent schematic diagrams
CDE1, CDE2, DE/RE Inputs
A and INV/NON Inputs
10uA
V
CC
V
CC
Input
10uA
Input
CDE0 Input
A Output
V
CC
V
CC
Input
A
B+ Input
B– Input
I
ref
I
ref
37 Ω
37 Ω
BP
BN
I
ref
I
ref
113 Ω
113 Ω
V
CC
V
CC
V
CC
15 Ω
15 Ω
15 Ω
113 Ω
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
Terminal Functions
’LVDM976 ’LVDM977
TERMINAL
I/O
Termination
DESCRIPTION
Logic
Level
Logic
Level
NAME
1A – 9A
NO.
4,6,8,10,
19,21,23,
25,27
CMOS
TTL
I/O
Pullup
1A – 9A carry data to and from the communication controller.
–
–
1B – 9B
29,31,33,
35,37,46,
48,50,52
LVD or
TTL
LVD or
TTL
I/O
I/O
None
None
1B– to 9B– are the signals to and from the data bus. When
INV/NON is low, the logic sense is the opposite that of the A
input (inverted). When INV/NON is high, the logic sense is the
same as the A input (noninverted).
+
+
1B – 9B
30,32,34,
36,38,47,
49,51,53
LVD or
GND
LVD or
GND
When in the LVD mode, 1B+ – 9B+ are signals to or from the
data bus and follow the same logic sense as the A input when
INV/NON is low (noninverted). The logic sense is opposite that
of the A input (inverted) when INV/NON is high. When in
single-ended mode, these terminals become
connection through a transistor and do not switch.
a ground
CDE0
54
Trinary
Trinary
Input
None
CDE0 is the common driver enable 0. With the driver enabled
and the CDE0 input less than 0.5 V, the driver output is
single-ended mode. With the driver enabled and the CDE0
input between 0.7 V and 1.9 V the driver output is LVD mode.
All drivers are disabled when the input is greater than 2.4 V.
CDE1
CDE2
55
56
CMOS
CMOS
CMOS
TTL
TTL
TTL
Input
Input
Input
Pulldown
Pulldown
Pulldown
CDE1 is the common driver enable 1. When CDE1 is high,
drivers 1 – 4 are enabled
CDE2 is the common driver enable 2. When CDE2 is high,
drivers 5 to 8 are enabled.
1DE/RE –
9DE/RE
5,7,9,11,
20,22,24,
26,28
1DE/RE – 9DE/RE are direction controls that transmit data to
the bus when it is high and CDE0 is below 2.2 V. Data is
received from the bus when 1DE/RE – 9DE/RE, CDE1, and
CDE2 are low.
GND
2,3,13,14,
15,16,17,
40,41,42,
43,44
NA
NA
Power
NA
GND is the circuit ground.
INV/NON
1
CMOS
NA
CMOS
NA
Input
Pullup
NA
A high-level input to INV/NON inverts the logic to and
from the A terminals. (i.e., the voltage at A terminal and
the corresponding B– terminal are in phase.)
V
CC
12,18,39,
45
Power
Supply voltage
13
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9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (A, INV/NON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
I
CC
(DE/RE, B+, B–, CDE0, CDE1, CDE2) . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.25 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND unless otherwise noted.
DISSIPATION RATING TABLE
≤ 25°C DERATING FACTOR
T
A
T = 70°C
A
POWER RATING
PACKAGE
POWER RATING
ABOVE T = 25°C
A
DGG
978 mW
10.8 mW/°C
492 mW
recommended operating conditions (see Figure 15)
MIN NOM
4.75
MAX
UNIT
Supply voltage, V
CC
5
5.25
V
SN75LVDM976
SN75LVDM977
SN75LVDM976
SN75LVDM977
Differential receiver
0.7 V
CC
2
High-level input voltage, V
V
V
IH
0.3 V
CC
0.8
Low-level input voltage, V
IL
Differential input voltage, |V
ID
Common-mode input voltage, V
|
0.03
0.7
3.6
1.8
–125
–7
V
V
IC
Differential output voltage bias, V
OD(bias)
Differential
–100
mV
Single-ended driver
Receiver
High-level output current, I
mA
mA
OH
–2
Single-ended driver
Receiver
48
Low-level output current, I
OL
2
Differential load impedance, Z
40
0
65
Ω
L
Operating free-air temperature, T
A
70
°C
14
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SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
50
UNIT
CDE1 and CDE2
INV/NON
I
I
High-level input current
µA
IH
–50
50
CDE1 and CDE2
INV/NON
Low-level input current
µA
mA
pF
IL
–50
7
Disabled
LVD drivers enabled,
No load
No load
No load
26
I
Supply current
Single-ended drivers enabled,
LVD receivers enabled,
10
CC
26
Singled-ended receivers enabled, No load
V = 0.2 sin (2 π (1E06)t) + 0.5 ± 0.01 V
7
C
Input capacitance
Bus terminal
9.5
I
I
∆C Difference in input capacitance between B+ and B–
0.2
I
†
All typical values are at V
= 5 V, T = 25°C.
A
CC
DIFFSENS (CDE0) receiver electrical characteristics over recommended operating free-air
temperature range (unless otherwise noted)
†
PARAMETER
Input threshold voltage
TEST CONDITIONS
MIN TYP
MAX
0.7
UNIT
V
V
0.5
1.9
0.6
2.1
IT1
V
Input threshold voltage
Input current
2.4
IT2
I
I
0 V ≤ V ≤ 2.7 V
±1
µA
µA
I
I
Power-off input current
V
CC
= 0,
0 V ≤ V ≤ 2.7 V
±1
I(OFF)
I
†
All typical values are at V
= 5 V, T = 25°C.
A
CC
15
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9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
LVD driver electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
270
460
780
V
= 0.96 V, V
= 0.53 V,
I(1)
See Figure 16
I(2)
0.69|V
0.69|V
|+ 50
|+ 50
1.45|V
1.45|V
|– 65
|– 65
Driver differential high-level out-
put voltage
OD(L)
270
OD(L)
780
V
mV
OD(H)
500
V
= 1.96 V, V
= 1.53 V,
= 0.53 V,
= 1.53 V,
I(1)
See Figure 16
I(2)
I(2)
I(2)
OD(L)
–260
OD(L)
–640
V
= 0.96 V, V
I(1)
See Figure 16
–400
–400
1.2
Driver differential low-level output
voltage
V
V
mV
OD(L)
V
= 1.96 V, V
I(1)
See Figure 16
–260
1.1
–640
1.5
Steady-state common-mode out-
put voltage
V
OC(SS)
Change in steady-state common-
mode output voltage between
logic states
V
= 1.41 V, V
= 0.99 V,
I(1)
See Figure 17
I(2)
∆V
±50
±120
mV
OC(SS)
OC(PP)
Peak-to-peak common-mode
output voltage
V
80
150
mV
A
High-level input current
DE/RE
–7
8
V
V
= 3.3 V (’976)
= 2 V (’977)
IH
IH
I
µA
IH
50
A
Low-level input current
DE/RE
–30
V
IL
V
IL
= 1.6 V (’976)
= 0.8 V (’977)
I
IL
µA
I
I
I
Power-off output current
V
= 0, 0 V ≤ V ≤ 2.5 V
±1
±24
±1
µA
mA
µA
O(OFF)
CC
O
Short-circuit output current
High-impedance output current
0 V ≤ V ≤ 2.5 V
O
OS
V
O
= 0 or 2.5 V
OZ
†
All typical values are at V
= 5 V, T = 25°C.
A
CC
LVD driver switching characteristics over recommended operating conditions (unless otherwise
noted) (See Figure 16)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
8.8
8.8
6
UNIT
ns
t
t
t
t
t
t
t
t
Propagation delay time, low-to-high level output
Propagation delay time, high-to-low level output
Differential output signal rise time
2.9
2.9
1
PLH
PHL
r
ns
V
V
= 5 V,
= 0.99 V,
V
T
= 1.41 V,
= 25°C
CC
I2
I1
3
3
ns
A
Differential output signal fall time
1
6
ns
f
Pulse skew (|t
– t
PHL PLH
|)
3.7
5.9
50
ns
sk(p)
sk(lim)
PHZ
en
‡
Skew limit
ns
Propagation delay time, high-level to high-impedance output
Enable time, receiver to driver
ns
V
= 1.41 V,
V
I2
= 0.99 V,
I1
See Figure 18
33
ns
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
is the maximum delay time difference between any two drivers on any two devices operating at the same supply voltage and the same
t
sk(lim)
ambient temperature.
16
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9-CHANNEL DUAL-MODE TRANSCEIVERS
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single-ended driver electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
= –7 mA, See Figure 19
MIN
TYP
MAX
3.24
3.7
UNIT
I
I
2
V
V
V
OH
V
High-level output voltage
B– output
B– output
B+
OH
OL
= 0 mA
= 5 V,
OH
V
I
= 48 mA
0.5
CC
OL
V
Low-level output voltage
I
= –25 mA
= 25 mA
–0.5
0.5
OL
OL
V
I
A
DE/RE
A
–7
8
V
V
= 3.3 V (’976),
= 2 V (’977)
IH
IH
I
I
High-level input current
Low-level input current
µA
µA
IH
50
–30
V
IL
V
IL
= 1.6 V (’976),
= 0.8 V (’977)
IL
DE/RE
B–
I
I
Power-off output current
V
CC
= 0,
0 V ≤ V ≤ 5.25 V
±1
±1
µA
µA
O(OFF)
O
High-impedance output current
V
O
= 0 or V
CC
OZ
single-ended driver switching characteristics over recommended operating conditions (unless
otherwise noted)
†
PARAMETER
Propagation delay time, low-to-high level output
Propagation delay time, high-to-low level output
Differential output signal rise time
TEST CONDITIONS
MIN TYP
MAX
8.2
8.2
4
UNIT
ns
t
t
t
t
t
t
t
t
2.7
2.7
0.5
0.5
PLH
PHL
r
ns
V
T
= 5 V,
CC
= 25°C,
ns
A
See Figure 19
Differential output signal fall time
4
ns
f
Pulse skew (|t
– t
PHL PLH
|)
3.4
5.5
50
ns
sk(p)
sk(lim)
en
‡
Skew limit
ns
Enable time, receiver to driver
ns
See Figure 20
Propagation delay time, low-level to high-impedance output
30
ns
PLZ
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
is the maximum delay time difference between any two drivers on any two devices operating at the same supply voltage and the same
t
sk(lim)
ambient temperature.
LVD receiver electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
High-level output voltage
TEST CONDITIONS
MIN
TYP
MAX
30
UNIT
mV
mV
V
V
V
V
V
IT+
IT–
OH
OL
See Figure 21
–30
I
I
= –2 mA
= 2 mA
3.7
OH
Low-level output voltage
0.5
±1
±1
V
OL
I
I
Input current, B+ or B–
V = 0 V to 2.5 V
µA
µA
I
I
Power-off Input current, B+ or B–
V
= 0,
V = 0 V to 2.5 V
I
I(OFF)
CC
V
IH
V
IH
= 3.3 V (’976),
= 2 V (’977)
I
IH
High-level input current, DE/RE
50
µA
V
V
= 1.6 V (’976),
= 0.8 V (’977)
IL
IL
I
I
Low-level input current, DE/RE
High-impedance output current
8
µA
µA
IL
V
O
= 0 or V
CC
±30
OZ
17
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9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
LVD receiver switching characteristics over recommended operating conditions (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
10
10
3
UNIT
ns
t
t
t
t
t
t
t
t
t
Propagation delay time, low-to-high level output
Propagation delay time, high-to-low level output
4.5
4.5
PLH
PHL
sk(p)
r
ns
V
T
= 5 V,
CC
= 25°C,
Pulse skew (|t
– t
PHL PLH
|)
ns
A
See Figure 21
Output signal rise time
Output signal fall time
8
ns
8
ns
f
‡
Skew limit
5.5
42
20
26
ns
sk(lim)
PHZ
PLZ
en
Propagation delay time, high-level to high-impedance output
Propagation delay time, low-level to high-impedance output
Enable time, driver to receiver
ns
See Figure 18
ns
ns
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
is the maximum delay time difference between any two drivers on any two devices operating at the same supply voltage and the same
t
sk(lim)
ambient temperature.
single-ended receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
Positive-going input voltage threshold
Negative-going input voltage threshold
High-level output voltage
TEST CONDITIONS
MIN
TYP
1.6
1.1
4.6
0.3
MAX
UNIT
V
V
IT+
V
IT–
V
OH
V
OL
B–
B–
1.9
1
V
I
I
= –2 mA
= 2 mA
3.7
V
OH
Low-level output voltage
0.5
V
OL
I
Input current
B–
B–
V = 0 to V
±1
µA
I
I
CC
= 0 V,
V
CC
V = 0 to 5.25 V
I
Power-off Input current
High-level input current
±1
µA
µA
I(OFF)
IH
I
V
IH
V
IH
= 3.3 V (’976),
= 2 V (’977)
I
DE/RE
DE/RE
50
V
IL
V
IL
= 1.6 V (’976),
= 0.8 V (’977)
I
I
Low-level input current
8
µA
µA
IL
High-impedance output current
V
O
= 0 or V
CC
–30
OZ
single-ended receiver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
7
TYP
MAX
12.5
12.5
3.5
8
UNIT
ns
t
t
t
t
t
t
t
t
t
Propagation delay time, low-to-high level output
Propagation delay time, high-to-low level output
PLH
PHL
sk(p)
r
7
ns
V
T
= 5 V,
CC
= 25°C,
Pulse skew (|t
– t
PHL PLH
|)
ns
A
See Figure 22
Output signal rise time
Output signal fall time
ns
8
ns
f
†
Skew limit
5.5
20
ns
sk(lim)
PHZ
PLZ
en
Propagation delay time, high-level to high-impedance output
Propagation delay time, low-level to high-impedance output
Enable time, driver to receiver
ns
See Figure 20
30
ns
48
ns
†
t
is the maximum delay time difference between any two drivers on any two devices operating at the same supply voltage and the same
sk(lim)
ambient temperature.
18
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9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
I
+
OB
B+
I
I
A
I
–
V
OD
OB
V
V
OB
OB
2
V
OB+
B–
V
OC
V
I
V
OB–
Figure 15. Voltage and Current Definitions
50 Ω
100 Ω
Input
5 V
A
B–
V1
DE/RE
CDE0
CDE1
CDE2
C
C
= 10 pF
= 10 pF
+
–
L
L
1.3 V
V
OD
75 Ω
Open
Open
B+
0 V or 5 V
INV/NON
V2
100 Ω
+
–
0.7 V
(’976)
CC
2 V (’977)
INPUT
Solid line is INV/NON at 0 V.
Dashed line is INV/NON at 5 V.
0.3 V (’976)
CC
0.8 V (’977)
t
t
PHL
PLH
100%
80%
V
OUTPUT
OD(H)
0 V
V
OD(L)
20%
0%
t
t
r
f
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t or t < 1 ns, pulse repetition rate (PRR) = 10 Mpps,
r
f
pulsewidth = 50 ns ±5 ns, Z = 50 Ω.
o
B.
C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
L
Figure 16. Differential Output Signal Test Circuit, Timing, and Voltage Definitions
19
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9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
V1
50 Ω
100 Ω
Input
5 V
A
V
L
OC
B–
B+
37.5 Ω
DE/RE
CDE0
1.3 V
Open
CDE1
C
= 50 pF
Open
CDE2
37.5 Ω
100 Ω
0 V or 5 V
INV/NON
V2
0.7 V
(’976)
CC
2 V (’977)
Input
0.3 V (’976)
CC
0.8 V (’977)
V
OC(PP)
V
OC(SS)
Output
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 10 Mpps,
r
f
pulsewidth = 50 ns ±5 ns, Z = 50 Ω.
o
B.
C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
L
C. The measurement of V
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
OC(PP)
Figure 17. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
20
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9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
V1
100 Ω
C
= 50 pF
L
C
= 50 pF
A
L
B–
37.5 Ω
37.5 Ω
620 Ω
V
V
OD
Input
1.3 V
DE/RE
CDE0
B+
C = 50 pF
L
Open
CDE1
Open
CDE2
0 V or 5 V
INV/NON
100 Ω
V2
TEST CIRCUIT
V at 5 V, INV/NON at 0 V
V at 0 V, INV/NON at 5 V
0.7 V
2 V (’977)
(’976)
CC
0.7 V
2 V (’977)
(’976)
CC
Input
50%
50%
0.3 V
(’976)
0.3 V
(’976)
CC
0.8 V (’977)
CC
0.8 V (’977)
t
t
t
t
en(d)
PHZ(d)
en(d)
PHZ(d)
≈ 0.4 V
≈ 0.4 V
V
OD
0 V
0 V
≈ –0.12 V
≈ –0.12 V
t
t
en(d)
t
t
en(r)
en(d)
en(r)
5 V
5 V
V
A
1.4 V
1.4 V
≈ 0.2 V
≈ 0.2 V
VOLTAGE WAVEFORMS
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 1 Mpps,
r
f
pulsewidth = 500 ns ±50 ns, Z = 50 Ω.
C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
L
o
B.
Figure 18. LVD Transceiver Enable and Disable Time Test Circuit and Definitions
21
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9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
50 Ω
Input
0 V
A
I
O
DE/RE
CDE0
CDE1
CDE2
INV/NON
47 Ω
B–
0 V
Open
C
= 10 pF
+
–
L
Open
2.5 V
V
O
0 V or 5 V
0.7 V
(’976)
CC
2 V (’977)
Solid line is INV/NON
at a high-level input.
INPUT
0.3 V (’976)
CC
0.8 V (’977)
Dashed line is INV/NON
at a low-level input.
t
t
PHL
PLH
100%
80%
OUTPUT
1.4 V
20%
0%
t
t
r
f
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t or t < 1 ns, pulse repetition rate (PRR) = 10 Mpps,
r
f
pulsewidth = 50 ns ±5 ns, Z = 50 Ω.
o
B.
C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
L
Figure 19. Single-Ended Driver Switching Test Circuit
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
C
= 50 pF
A
L
V
A
47 Ω
B–
V
620 Ω
Input
0 V
DE/RE
C
= 10 pF
+
–
L
CDE0
2.5 V
V
B
Open
CDE1
Open
CDE2
0 V or 5 V
INV/NON
TEST CIRCUIT
V and INV/NON at 5 V
V and INV/NON at 0 V
0.7 V
50%
0.7 V
50%
CC
CC
CC
CC
Input
0.3 V
0.3 V
t
PHZ(r)
t
en(r)
t
t
en(r)
PLZ(r)
V
OL
V
A
0.5 V
V
OL
0.5 V
t
t
t
t
PLZ(d)
PLZ(d)
en(d)
en(d)
V
B
V
OL
V
OL
0.5 V
0.5 V
VOLTAGE WAVEFORMS
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 1 Mpps,
r
f
pulsewidth = 500 ns ±50 ns, Z = 50 Ω.
C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
L
o
B.
Figure 20. Single-Ended Transceiver Enable and Disable Timing Measurements
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
50 Ω
I
IB+
I
O
V
ID
V
IB
C
= 15 pF
L
50 Ω
V
O
I
IB–
V
IB–
0 V
1.3 V
DE/RE
CDE0
Open
CDE1
Open
CDE2
0 or 5 V
INV/NON
TEST CIRCUIT
V
1.4 V
1 V
IB
V
IB–
0.4 V
0 V
V
ID
–0.4 V
t
t
PLH
PHL
Solid line is INV/NON
at a high-level input.
V
OH
80%
20%
50%
V
O
V
OL
Dashed line is INV/NON
at a low-level input.
t
f
t
r
VOLTAGE WAVEFORMS
NOTES: A. Note: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate
r
f
(PRR) = 10 Mpps, pulsewidth = 50 ns ±5 ns, Z = 50 Ω.
C includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
L
o
B.
Figure 21. LVD Receiver Switching Characteristic Test Circuit
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
Input
GND
GND
Open
Open
B–
I
O
DE/RE
CDE0
CDE1
CDE2
INV/NON
A
C
= 15 pF
L
V
O
GND or V
CC
2 V
1.4 V
0.8 V
Solid line is INV/NON at a high-level input.
Dashed line is INV/NONat a low-level input.
INPUT
t
t
PLH
PHL
V
OH
100%
80%
OUTPUT
–1.4 V
20%
0%
V
OL
t
t
f
r
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t or t < 1 ns, pulse repetition rate (PRR) = 10 Mpps,
r
f
pulsewidth = 50 ns ±5 ns.
includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
B.
C
L
Figure 22. Single-Ended Receiver Timing Test Circuit
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
APPLICATION INFORMATION
U1
‘LVDM976
8.2 kΩ, 1/8 W, 5%
0.022 µF, 6 V, 10%
CDE0
DIFFSENS
U2
‘LVDM976
CDE0
U3
‘LVDM976
CDE0
Figure 23. Low-Pass Filter for Connecting DIFFSENS to CDE0
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDM976, SN75LVDM977
9-CHANNEL DUAL-MODE TRANSCEIVERS
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
MECHANICAL INFORMATION
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PIN SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
1,20 MAX
0,05 MIN
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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