SN75LVDS32_07 [TI]
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS; 高速差动线路接收器
| 型号： | SN75LVDS32_07 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-SPEED DIFFERENTIAL LINE RECEIVERS |
| 文件： | 总19页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360B – JUNE 1999 – REVISED JUNE 2001
Meets or Exceeds the Requirements of
ANSI TIA/EIA-644 Standard
SN75LVDS32D (Marked as 75LVDS32)
SN75LVDS32PW (Marked as DS32)
(TOP VIEW)
Operates With a Single 3.3-V Supply
Designed for Signaling Rate of up to
155 Mbps
1B
1A
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
4B
4A
4Y
G
1Y
Differential Input Thresholds ±100 mV Max
G
Low-Voltage TTL (LVTTL) Logic Output
Levels
2Y
2A
11 3Y
10 3A
Open-Circuit Fail Safe
2B
Characterized For Operation From
0°C to 70°C
GND
9
3B
SN75LVDS9637D (Marked as DF637 or 7L9637)
SN75LVDS9637DGK (Marked as AXI)
(TOP VIEW)
description
The SN75LVDS32 and SN75LVDS9637 are
differential line receivers that implement the
electricalcharacteristicsoflow-voltagedifferential
signaling (LVDS). This signaling technique lowers
the output voltage levels of 5-V differential
standard levels (such as EIA/TIA-422B) to reduce
the power, increase the switching speeds, and
V
1
2
3
4
8
7
6
5
1A
1B
2A
2B
CC
1Y
2Y
GND
allow operation with a 3.3-V supply rail. Any of the four differential receivers provides a valid logical output state
with a ±100 mV allow operation with a differential input voltage within the input common-mode voltage range.
The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes.
The intended application of these devices and signaling technique is both point-to-point and multidrop (one
driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The
transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance
of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the
environment.
The SN75LVDS32 and SN75LVDS9637 are characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001 Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360B – JUNE 1999 – REVISED JUNE 2001
logic diagram
’LVDS32 logic diagram
(positive logic)
’LVDS9637D logic diagram
(positive logic)
8
4
2
1A
1B
G
1Y
2Y
7
12
G
6
5
2
3
3
1A
2A
2B
1Y
1
1B
6
5
2A
2B
2Y
3Y
4Y
7
10
9
3A
3B
11
13
14
15
4A
4B
Function Tables
SN75LVDS32
DIFFERENTIAL INPUT
A, B
ENABLES
OUTPUT
Y
G
G
H
X
X
L
H
H
V
ID
≥ 100 mV
H
X
X
L
?
?
–100 mV < V < 100 mV
ID
H
X
X
L
L
L
V
ID
≤ –100 mV
X
L
H
Z
H
X
X
L
H
H
Open
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
2
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SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360B – JUNE 1999 – REVISED JUNE 2001
†
logic symbol
SN75LVDS32
≥ 1
4
G
G
EN
12
2
1
1A
1B
3
5
1Y
2Y
3Y
6
7
2A
2B
3A
3B
10
9
11
13
14
15
4A
4B
4Y
†
This symbol is in accordance with ANSI/IEEE Std
91-1984 and IEC Publication 617-12.
Function Table
†
logic symbol
SN75LVDS9637
SN75LVDS9637
8
7
6
5
DIFFERENTIAL INPUT
A, B
OUTPUT
1A
1B
2A
2B
2
3
1Y
2Y
Y
H
?
V
≥ 100 mV
ID
–100 mV < V < 100 mV
ID
V
ID
≤ –100 mV
L
†
This symbol is in accordance with ANSI/IEEE Std
91-1984 and IEC Publication 617-12.
Open
H
H = high level, L = low level, ? = indeterminate
3
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SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360B – JUNE 1999 – REVISED JUNE 2001
equivalent input and output schematic diagrams
EQUIVALENT OF EACH A OR B INPUT
EQUIVALENT OF G, G, 1,2EN OR
TYPICAL OF ALL OUTPUTS
3,4EN INPUTS
V
CC
V
CC
V
CC
300 kΩ
300 kΩ
50 Ω
5 Ω
Input
7 V
Y Output
A Input
B Input
7 V
7 V
7 V
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
CC
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
I
CC
Input voltage range, V (A or B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
I
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 C to 150 C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.
DISSIPATION RATING TABLE
‡
T
≤ 25°C
DERATING FACTOR
T = 70°C
A
POWER RATING
A
PACKAGE
POWER RATING
ABOVE T = 25°C
A
D (8)
D (16)
PW
725 mW
5.8 mW/°C
7.6 mW/°C
6.2 mW/°C
3.4 mW/°C
464 mW
950 mW
608 mW
774 mW
496 mW
DGK
425 mW
272 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board mounted and with
no air flow.
4
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SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360B – JUNE 1999 – REVISED JUNE 2001
recommended operating conditions
MIN NOM
MAX
UNIT
Supply voltage, V
CC
3
2
3.3
3.6
V
V
V
V
High-level input voltage, V
IH
G, G
G, G
Low-level input voltage, V
IL
Magnitude of differential input voltage, |V
0.8
0.6
|
0.1
|
ID
|V
|
|V
ID
ID
V
2.4
2
Common-mode input voltage, V (see Figure 1)
IC
2
V
CC
– 0.8
70
V
Operating free-air temperature, T
0
°C
A
COMMON-MODE INPUT VOLTAGE RANGE
vs
DIFFERENTIAL INPUT VOLTAGE
2.5
2
Max at V
>3.15 V
CC
Max at V
= 3 V
CC
1.5
1
0.5
0
Min
0.3
0
0.1
0.2
0.4
0.5
0.6
V
ID
– Differential Input Voltage – V
Figure 1. V Versus V and V
CC
IC
ID
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360B – JUNE 1999 – REVISED JUNE 2001
SN75LVDSxxxx electrical characteristics over recommended operating conditions (unless
otherwise noted)
SN75LVDS32,
SN75LVDS9637
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
V
V
V
V
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
High-level output voltage
100
mV
mV
V
ITH+
ITH–
OH
See Figure 2 and Table 1
‡
–100
2.4
I
I
= –8 mA
= 8 mA
OH
Low-level output voltage
0.4
18
V
OL
OL
Enabled,
Disabled
No load
No load
10
0.25
5.5
–10
–3
SN75LVDS32
I
Supply current
0.5
10
mA
CC
SN75LVDS9637
V = 0
I
–2
–20
I
I
Input current (A or B inputs)
µA
V = 2.4 V
I
–1.2
I
I
I
I
Power-off input current (A or B inputs)
High-level input current (G, or G inputs)
Low-level input current (G, or G inputs)
High-impedance output current
V
V
V
V
= 0,
V = 3.6 V
I
6
20
10
µA
µA
µA
µA
I(OFF)
CC
= 2 V
IH
IH
IL
O
= 0.8 V
= 0 or V
10
IL
±10
OZ
CC
†
‡
All typical values are at T = 25°C and with V
The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for the negative-going
differential input voltage threshold only.
= 3.3 V.
CC
A
SN75LVDSxxxx switching characteristics over recommended operating conditions (unless
otherwise noted)
SN75LVDS32,
SN75LVDS9637
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
6
t
t
t
t
t
t
t
t
t
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
2.1
2.1
0.6
0.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pLH
pHL
sk(p)
sk(o)
sk(pp)
r
6
Pulse skew (|t
– t
|)
1.5
1.5
0.6
0.6
1
PHL PLH
†
Channel-to-channel output skew
C
= 100 pF, See Figure 3
L
‡
Part-to-part skew
Output signal rise time, 20% to 80%
Output signal fall time, 80% to 20%
f
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
All typical values are at 25°C and with a 3.3-V supply.
is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output
is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together.
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, same temperature, and have identical packages and test circuits.
25
25
25
25
pHZ
pLZ
pZH
pZL
See Figure 4
†
‡
§
¶
t
t
t
sk(p)
sk(o)
sk(pp)
6
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SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360B – JUNE 1999 – REVISED JUNE 2001
PARAMETER MEASUREMENT INFORMATION
A
B
Y
V
ID
V
IA
(V + V )/2
IA IB
V
O
V
IC
V
IB
Figure 2. Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED
VOLTAGES
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON-
MODE INPUT VOLTAGE
V
IA
V
IB
V
ID
V
IC
1.25 V
1.15 V
2.4 V
2.3 V
0.1 V
0 V
1.15 V
1.25 V
2.3 V
2.4 V
0 V
100 mV
–100 mV
100 mV
–100 mV
100 mV
–100 mV
600 mV
–600 mV
600 mV
–600 mV
600 mV
–600 mV
1.2 V
1.2 V
2.35 V
2.35 V
0.05 V
0.05 V
1.2 V
1.2 V
2.1 V
2.1 V
0.3 V
0.3 V
0.1 V
0.9 V
1.5 V
1.8 V
2.4 V
0 V
1.5 V
0.9 V
2.4 V
1.8 V
0.6 V
0 V
0.6 V
7
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SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360B – JUNE 1999 – REVISED JUNE 2001
PARAMETER MEASUREMENT INFORMATION
V
ID
V
IA
V
O
C
10 pF
V
IB
L
V
V
1.4 V
1 V
IA
IB
0.4 V
0
V
ID
–0.4 V
t
t
PLH
PHL
V
OH
1.4 V
80%
20%
80%
20%
V
O
V
OL
t
t
r
f
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate
r
f
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns.
B.
C
includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
L
Figure 3. Timing Test Circuit and Wave Forms
8
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SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360B – JUNE 1999 – REVISED JUNE 2001
PARAMETER MEASUREMENT INFORMATION
B
1.2 V
500 Ω
A
10 pF
G
G
±
(see Note B)
V
O
Inputs
(see Note A)
V
TEST
2.5 V
V
TEST
A
1 V
2 V
1.4 V
0.8 V
G
2 V
1.4 V
0.8 V
G
t
t
PLZ
PLZ
t
t
PZL
PZL
Y
2.5 V
1.4 V
OL
OL
V
V
+0.5 V
V
TEST
0
1.4 V
A
G
2 V
1.4 V
0.8 V
2 V
1.4 V
0.8 V
t
PHZ
G
t
PHZ
t
t
PZH
PZH
Y
V
V
OH
OH
–0.5 V
1.4 V
0
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate
r
f
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns.
includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
B.
C
L
Figure 4. Enable/Disable Time Test Circuit and Wave Forms
9
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SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360B – JUNE 1999 – REVISED JUNE 2001
APPLICATION INFORMATION
using an LVDS receiver with RS-422 data
Receipt of data from a TIA/EIA-422 line driver may be accomplished using a TIA/EIA-644 line receiver with the
addition of an attenuator circuit. This technique gives the user a very high-speed and low-power 422 receiver.
If the ground noise between the transmitter and receiver is not a concern (less than ±1 V), the answer can be
as simple as shown below in Figure 5. The use of a resistor divider circuit in front of the LVDSreceiverattenuates
the 422 differential signal to LVDS levels.
The resistors present a total differential load of 100 Ω to match the characteristic impedance of the transmission
line and to reduce the signal 10:1. The maximum 422 differential output signal or 6 V is reduced to 600 mV. The
high input impedance of the LVDS receiver prevents input bias offsets and maintains a better than 200-mV
differential input voltage threshold at the inputs to the divider. This circuit is used in front of each LVDS channel
that also receives 422 signals.
R1
45.3 Ω
’LVDS32
R3
5.11 Ω
A
B
Y
R4
5.11 Ω
R2
45.3 Ω
NOTE A: The components used were standard values.
R1, R2 = NRC12F45R3TR, NIC Components, 45.3 Ohm, 1/8W, 1%, 1206 Package
R3, R4 = NRC12F5R11TR, NIC Components, 5.11 Ohm, 1/8W, 1%, 1206 Package
The resistor values do not need to be 1% tolerance. However, it can be difficult locating a supplier of resistors having values less than
100 Ω in stock and readily available. The user may find other suppliers with comparable parts having tolerances of 5% or even 10%.
These parts are adequate for use in this circuit.
Figure 5. RS-422 Data Input to an LVDS Receiver Under Low Ground Noise Conditions
If ground noise between the RS-422 driver and LVDS receiver is a concern, then the common-mode voltage
must be attenuated. The circuit must then be modified to connect the node between R3 and R4 to the LVDS
receiver ground. This modification to the circuit increases the common-mode voltage from ±1 V to greater than
±4.5 V.
10
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SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360B – JUNE 1999 – REVISED JUNE 2001
APPLICATIONS INFORMATION
The devices are generally used as building blocks for high-speed point-to-point data transmission where ground
differences are less than 1 V. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers
approach ECL speeds without the power and dual supply requirements.
TRANSMISSION DISTANCE
vs
SIGNALING RATE
100
30% Jitter
(see Note A)
10
5% Jitter
(see Note A)
1
24 AWG UTP 96 Ω
(PVC Dielectric)
0.1
10
100
1000
Signaling Rate – Mbps
NOTE A: This parameter is the percentage of distortion of the unit interval (UI) with a pseudorandom data pattern.
Figure 6. Typical Transmission Distance vs Signaling Rate
3.3 V
1
2
16
1B
1A
V
CC
0.1 µF
(see Note A)
0.001 µF
(see Note A)
100 Ω
15
14
4B
4A
3
4
100 Ω
(see Note B)
1Y
G
V
CC
13
12
11
5
6
4Y
G
2Y
2A
See Note C
3Y
100 Ω
7
8
10
9
3A
3B
2B
100 Ω
GND
NOTES: A. Place a 0.1 µF and a 0.001 µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between V
and the ground
CC
plane. The capacitors should be located as close as possible to the device terminals.
B. The termination resistance value should match the nominal characteristic impedance of the transmission media with ±10%.
C. Unused enable inputs should be tied to V or GND as appropriate.
CC
Figure 7. Typical Application Circuit Schematic
11
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SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360B – JUNE 1999 – REVISED JUNE 2001
APPLICATION INFORMATION
1/4 ’LVDS31
Strb/Data_TX
TpBias on
Strb/Data_Enable
Twisted-Pair A
TP
TP
’LVDS32
55 Ω
5 kΩ
Data/Strobe
1 Arb_RX
55 Ω
3.3 V
20 kΩ
500 Ω
500 Ω
VG on
Twisted-Pair B
20 kΩ
3.3 V
20 kΩ
500 Ω
500 Ω
2 Arb_RX
20 kΩ
3.3 V
Twisted-Pair B Only
Port_Status
7 kΩ
7 kΩ
10 kΩ
3.3 kΩ
NOTES: A. Resistors are leadless thick-film (0603) 5% tolerance.
B. Decoupling capacitance is not shown but recommended.
C.
V
CC
is 3 V to 3.6 V.
D. The differential output voltage of the ’LVDS31 can exceed that allowed by IEEE1394.
Figure 8. 100-Mbps IEEE 1394 Transceiver
12
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SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360B – JUNE 1999 – REVISED JUNE 2001
APPLICATION INFORMATION
fail safe
One of the most common problems with differential signaling applications is how the system responds when
no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in
that its output logic state can be indeterminate when the differential input voltage is between –100 mV and
100 mV if it is within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how
it handles the open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
will pull each line of the signal pair to near V
through 300-kΩ resistors as shown in Figure 9. The fail-safe
CC
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high level, regardless of the differential input voltage.
V
CC
300 kΩ
300 kΩ
A
B
Rt
Y
V
IT
≈ 2.3 V
Figure 9. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as
long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that
could defeat the pullup currents from the receiver and the fail-safe feature.
13
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SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360B – JUNE 1999 – REVISED JUNE 2001
APPLICATION INFORMATION
0.01 µF
≈3.6 V
16
V
CC
5 V
1
2
1B
1A
0.1 µF
(see Note A)
1N645
(2 places)
100 Ω
15
14
4B
4A
3
4
100 Ω
(see Note B)
1Y
G
V
CC
13
12
11
5
6
4Y
G
2Y
2A
See Note C
3Y
100 Ω
7
8
10
9
3A
3B
2B
100 Ω
GND
NOTES: A. Place a 0.1 µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between V
and the ground plane. The
CC
capacitor should be located as close as possible to the device terminals.
B. The termination resistance value should match the nominal characteristic impedance of the transmission media with ±10%.
C. Unused enable inputs should be tied to V or GND as appropriate.
CC
Figure 10. Operation With 5-V Supply
related information
IBISmodelingisavailableforthisdevice. PleasecontactthelocalTIsalesofficeortheTIWebsiteatwww.ti.com
for more information.
For more application guidelines, please see the following documents:
Low-Voltage Differential Signalling Design Notes (TI literature SLLA014)
Interface Circuits for TIA/EIA-644 (LVDS) (TI literature SLLA038)
Reducing EMI with LVDS (TI literature SLLA030)
Slew Rate Control of LVDS Circuits (TI literature SLLA034)
Using an LVDS Receiver with RS-422 Data (TI literature SLLA031)
Evaluating the LVDS EVM (TI literature SLLA033)
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360B – JUNE 1999 – REVISED JUNE 2001
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–8°
0.044 (1,12)
A
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360B – JUNE 1999 – REVISED JUNE 2001
MECHANICAL INFORMATION
DGK (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
M
0,65
8
0,25
5
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
0°–6°
1
4
0,69
3,05
2,95
0,41
Seating Plane
0,10
0,15
0,05
1,07 MAX
4073329/B 04/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-187
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360B – JUNE 1999 – REVISED JUNE 2001
MECHANICAL INFORMATION
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
PACKAGING INFORMATION
Orderable Device
SN75LVDS32D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
8
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75LVDS32DG4
SN75LVDS32DR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75LVDS9637D
SN75LVDS9637DG4
SN75LVDS9637DR
SN75LVDS9637DRG4
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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